CN103236415B - A kind of thin-film hybrid integrated circuit electro-plating method - Google Patents
A kind of thin-film hybrid integrated circuit electro-plating method Download PDFInfo
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- CN103236415B CN103236415B CN201210594109.3A CN201210594109A CN103236415B CN 103236415 B CN103236415 B CN 103236415B CN 201210594109 A CN201210594109 A CN 201210594109A CN 103236415 B CN103236415 B CN 103236415B
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Abstract
The invention provides a kind of thin-film hybrid integrated circuit electro-plating method, first be utilize magnetron vacuum sputter to be deposited on successively on microstrip substrate by TaN-TiWu-Au laminated film, then mask is done with photoresist, etch away layer gold wherein and titanium tungsten layer by wet-etching technology and complete retain tantalum nitride layer, interconnected in order to what realize when electroplating local isolated island circuit; Next in the drying box of 200 DEG C ~ 280 DEG C, thermal oxidation 180min ~ 360min is carried out, make surface production one deck tantalum oxide of tantalum nitride layer, local circuit conducting under above process just can realize electroplating conditions and the opposing insulation of non-plating surface, thus realize selective local plating.The present invention measures the production development trend that few production cost is low, meet environmental protection with photoresist.<!--1-->
Description
Technical field
The present invention relates to a kind of electroplating technology, particularly a kind of thin-film hybrid integrated circuit electro-plating method.
Background technology
Along with the continuous progress of microwave and millimeter wave technology, thin-film hybrid integrated circuit manufacturing process technical merit also significantly improves, because the film thickness by vacuum sputtering or evaporation is only less than 1 micron, in order to ensure that circuit loss is little as much as possible, need 3 ∽ 5 times thickness being increased to skin depth, need to thicken with electric plating method for this reason, and the material of current thin film circuit is in the majority with gold, because its stable performance, not oxidizable, be not subject to acid and alkali corrosion, and electric conductivity is excellent, circuit loss is low, but in circuit always there is the circuit of isolated island form in local, the electroplating technology of this kind of local circuit of current solution mainly contains three kinds: the first is electric plating of whole board, namely first carry out full wafer plating to thicken, then photoetching corrosion goes out circuitous pattern, the second is that first photoetching corrosion goes out figure, then passes through the interconnected of gold wire bonding realizing circuit, finally carries out plating and thickeies, the third is graphic plating, namely first protects plating with photoresist, and then goes out circuitous pattern by photoetching corrosion.
At present these three kinds of technology coming with some shortcomings all in various degree in application process, such as the first electric plating of whole board, because plating rete is thicker, wet etching is adopted to there is larger corrosion factor, make that band linear dimension diminishes, deterioration in accuracy, and the waste of this technique noble metal is serious, production cost is high; If the second is then need gold wire bonding and go spun gold operation, inevitably produces a large amount of coin marking and burr for this reason, add circuit loss and standing-wave ratio, and gold wire bonding and go that the labor intensity of spun gold is large, efficiency is low; The third graphic plating technology be then when be with glue carry out, in electroplating process, photoresist can incorporate in plating solution gradually, the electroplating current density that can bear after electroplate liquid is contaminated diminish production efficiency reduce, cause electroplate liquid to scrap time serious.
Therefore, prior art existing defects, needs to improve.
Summary of the invention
Technical problem to be solved by this invention is for the deficiencies in the prior art, provides a kind of thin-film hybrid integrated circuit electro-plating method.
Technical scheme of the present invention is as follows:
A kind of thin-film hybrid integrated circuit electro-plating method, wherein, comprises the following steps:
A: magnetron sputtering deposition tantalum nitride membrane resistance on substrate, adopts high-purity tantalum target, and sputtering reacting gas is nitrogen and argon gas;
B: sputtered titanium W film and gold thin film successively on tantalum nitride membrane, use titanium tungsten target and high-purity gold target, sputtering reacting gas is argon gas;
C: do mask with photoresist, etches away unwanted gold outside design configuration with the golden corrosive liquid of iodine and the configuration of KI mixed aqueous solution, falls unwanted titanium tungsten film outside design configuration with titanium tungsten corrosive liquid wet etching;
D: after removing photoresist with potassium hydroxide solution, after rinsing with high purity water, then with analyzing the wiping of pure grade acetone solution;
E: adopt the method for thermal oxidation after the Surface Creation oxide film that tantalum nitride membrane is exposed, carry out plating and finally etch circuitous pattern;
F: by thermal oxidation under the substrate vacuum drying chamber predetermined temperature that cleans up, make tantalum nitride Surface Creation one deck tantalum oxide films;
G: at room temperature respectively through degreaser oil removal treatment and high purity water cleaning, and then activate and high purity water cleaning through the salt picking acid of 10%;
H: the electric current getting scheduled current density is electroplated, circuit deposits one deck gold, and plating terminates rear high purity water and cleans 60s, then poach in boiling water;
I: erode tantalum oxide and tantalum nitride obtains designing circuit pattern with the corrosive liquid of ammonium fluoride and nitric acid mixing.
Described method, wherein, in described steps A, described nitrogen and partial pressure of ar gas are than being N2:Ar=1:35; The sheet resistance value of described sputtering tantalum nitride membrane is 5 ∽ 15 Ω/ lower than design load.
Described method, wherein, in described step B, described titanium tungsten film is 0.05 micron; Described gold thin film is 0.2 micron; The flow of the gas of described argon gas is 70sccm.
Described method, wherein, in described step C, in described golden corrosive liquid, content of iodine is 60g/L and KI content is 200g/L.
Described method, wherein, in described step C, described titanium tungsten corrosive liquid is the hydrogen peroxide solution of 30%, and etching time is 10 ∽ 12min.
Described method, wherein, in described step D, described potassium hydroxide solution is 10%; Described high purity water washing time is 60s.
Described method, wherein, in described step F, described vacuum drying chamber predetermined temperature is arranged between 200 DEG C of ∽ 280 DEG C; Described oxidization time is 180min ∽ 360min.
Described method, wherein, in described step G, the described degreaser oil removal treatment time is 30s ∽ 60s; Described high purity water scavenging period is 60s; Described salt picking acid soak time is 30s ∽ 60s.
Described method, wherein, in described step H, described scheduled current density is 0.1 ∽ 0.3A/dm2; The described poach time is 10min.
Described method, wherein, in described step I, described ammonium fluoride and described nitric acid weight ratio are 1:5.
Adopt such scheme, the present invention not only solves prior art Problems existing, and obviously has following advantage:
1, the plating of isolated island formula local circuit in thin-film hybrid integrated circuit can be realized under the state without gold wire bonding connection and glue localised protection, not only simple to operate, and also can not have an impact to electroplate liquid quality and useful life without coin marking.
2, just can realize the plating of integrated circuit without the need to carrying out the plating of electric plating of whole board, gold wire bonding and band glue, and there is the advantages such as circuit precision is high, little, the surperficial no marking of side corrosion, simple to operate, production efficiency is high, production cost is low.
3, the present invention measures the production development trend that few production cost is low, meet environmental protection with photoresist.
Accompanying drawing explanation
Fig. 1 a-c utilizes magnetron sputtering technique on substrate, sputter a laminated film and circuitous pattern structure flow chart is showed in photoetching;
Fig. 1 a is compound TaN-TiWu-Au thin film deposition schematic diagram;
Fig. 1 b is photoresist mask wet etching circuit diagram;
Fig. 1 c is schematic diagram after removal photoresist mask;
Fig. 2 a-c is the structure flow chart electroplated after carrying out thermal oxidation to tantalum nitride;
Fig. 2 a thermal oxidation tantalum nitride membrane produces tantalum oxide schematic diagram;
Schematic diagram after Fig. 2 b electroplates;
Fig. 2 c etching oxidation tantalum and tantalum nitride schematic diagram;
Fig. 3 is that the application finally forms product stereogram.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Embodiment one
As shown in Fig. 1 a to Fig. 3, the application provides a technical scheme, first overall technological scheme of the present invention is utilize magnetron vacuum sputter to be deposited on successively on microstrip substrate by TaN-TiWu-Au laminated film, by regulating and controlling reaction gas flow ratio and time, control the sheet resistance value of sputtering rear film lower than design load 5 Ω ∽ 15 Ω, the sputtering thickness of TiWu layer and Au layer then sputters according to designing requirement; Then do mask with photoresist, etch away layer gold wherein and titanium tungsten layer by wet-etching technology and complete retain tantalum nitride layer, interconnected in order to what realize when electroplating local isolated island circuit; Next at 200 DEG C--carry out thermal oxidation 180min ∽ 360min in the drying box of 280 DEG C, make surface production one deck tantalum oxide of tantalum nitride layer, local circuit conducting under above process just can realize electroplating conditions and the opposing insulation of non-plating surface, thus realize selective local plating; Through plating add thicker than substrate directly or the circuit adopting the method for photoresist localised protection resistance to etch away tantalum nitride and tantalum oxide layers can to obtain designing.
Embodiment two
On the basis of above-described embodiment, carry out local electric for the production of the thin-film hybrid integrated circuit of 50 Ω/ gold-plated.
As shown in Figure 1, be on Magnetron Sputtering Thin Film, etch the complete circuitous pattern remaining tantalum nitride layer.
As shown in Figure 1a, magnetron sputtering deposition tantalum nitride membrane resistance 102 on substrate 101, adopt high-purity tantalum target, sputtering reacting gas is nitrogen and argon gas, the flow voltage ratio of gas is N2:Ar=1:35, the thickness of tantalum nitride membrane is at 0.06 micron, sputtering the sheet resistance obtained is 36 ∽ 45 Ω/, then titanium tungsten target and high-purity gold target is used, sputtering reacting gas is argon gas, the flow of gas is 70sccm, and it is the titanium tungsten film 103 of 0.05 micron and the gold thin film 104 of 0.2 micron that tantalum nitride membrane sputters thickness successively.
As shown in Figure 1 b, 107 do mask wet etching and fall unwanted gold and titanium tungsten film outside design configuration with photoresist, wherein golden corrosive liquid is iodine and KI mixed aqueous solution, and wherein its content of iodine is 60g/L, KI content is 200g/L, and titanium tungsten corrosive liquid is the hydrogen peroxide solution of 30%.
As illustrated in figure 1 c, remove photoresist 107 with 10% potassium hydroxide solution, then rinse 60s with high purity water, finally again with analyzing pure grade acetone solution wiped clean.
As shown in Figure 2 a, be adopt the method for thermal oxidation at the exposed Surface Creation oxide film of tantalum nitride membrane 102, then carry out plating and also finally etch circuitous pattern.
As shown in Figure 2 a, the substrate vacuum drying chamber cleaned up is oxidized 180min ∽ 360min under the state of 200 DEG C of ∽ 280 DEG C, makes tantalum nitride Surface Creation one deck tantalum oxide 105 film.
As shown in Figure 2 a, at room temperature respectively through the degreaser oil removal treatment of 30s ∽ 60s and the high purity water cleaning of 60s, and then through the 10% salt picking acid activation of 30s ∽ 60s and the high purity water cleaning of 60s.
As shown in Figure 2 b, electroplate, circuit deposits one deck gold 106 with the electric current that current density is 0.1 ∽ 0.3A/dm2, plating terminates last high purity water and cleans 60s, then poach 10min in boiling water.
As shown in Figure 2 c, tantalum oxide is eroded with the corrosive liquid that ammonium fluoride and nitric acid weight ratio are 1:5 and tantalum nitride obtains designing circuit pattern.
As shown in Figure 3, adopting said method to generate is final production product three-dimensional effect diagram of the present invention.
Embodiment three
On the basis of above-described embodiment, as shown in Fig. 1 a to Fig. 3, a kind of thin-film hybrid integrated circuit electro-plating method, wherein, comprises the following steps:
A: magnetron sputtering deposition tantalum nitride membrane resistance on substrate, adopts high-purity tantalum target, and sputtering reacting gas is nitrogen and argon gas;
B: sputtered titanium W film and gold thin film successively on tantalum nitride membrane, use titanium tungsten target and high-purity gold target, sputtering reacting gas is argon gas;
C: do mask with photoresist, etches away unwanted gold outside design configuration with the golden corrosive liquid of iodine and the configuration of KI mixed aqueous solution, falls unwanted titanium tungsten film outside design configuration with titanium tungsten corrosive liquid wet etching;
D: after removing photoresist with potassium hydroxide solution, after rinsing with high purity water, then with analyzing the wiping of pure grade acetone solution;
E: adopt the method for thermal oxidation after the Surface Creation oxide film that tantalum nitride membrane is exposed, carry out plating and finally etch circuitous pattern;
F: by thermal oxidation under the substrate vacuum drying chamber predetermined temperature that cleans up, make tantalum nitride Surface Creation one deck tantalum oxide films;
G: at room temperature respectively through degreaser oil removal treatment and high purity water cleaning, and then activate and high purity water cleaning through the salt picking acid of 10%;
H: the electric current getting scheduled current density is electroplated, circuit deposits one deck gold, and plating terminates rear high purity water and cleans 60s, then poach in boiling water;
I: erode tantalum oxide and tantalum nitride obtains designing circuit pattern with the corrosive liquid of ammonium fluoride and nitric acid mixing.
Described method, wherein, in described steps A, described nitrogen and partial pressure of ar gas are than being N2:Ar=1:35; The sheet resistance value of described sputtering tantalum nitride membrane is 5 ∽ 15 Ω/ lower than design load.
Described method, wherein, in described step B, described titanium tungsten film is 0.05 micron; Described gold thin film is 0.2 micron; The flow of the gas of described argon gas is 70sccm.
Described method, wherein, in described step C, in described golden corrosive liquid, content of iodine is 60g/L and KI content is 200g/L.
Described method, wherein, in described step C, described titanium tungsten corrosive liquid is the hydrogen peroxide solution of 30%, and etching time is 10 ∽ 12min.
Described method, wherein, in described step D, described potassium hydroxide solution is 10%; Described high purity water washing time is 60s.
Described method, wherein, in described step F, described vacuum drying chamber predetermined temperature is arranged between 200 DEG C of ∽ 280 DEG C; Described oxidization time is 180min ∽ 360min.
Described method, wherein, in described step G, the described degreaser oil removal treatment time is 30s ∽ 60s; Described high purity water scavenging period is 60s; Described salt picking acid soak time is 30s ∽ 60s.
Described method, wherein, in described step H, described scheduled current density is 0.1 ∽ 0.3A/dm2; The described poach time is 10min.
Described method, wherein, in described step I, described ammonium fluoride and described nitric acid weight ratio are 1:5.
Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, and all these improve and convert the protection range that all should belong to claims of the present invention.
Claims (10)
1. a thin-film hybrid integrated circuit electro-plating method, is characterized in that, comprises the following steps:
A: magnetron sputtering deposition tantalum nitride membrane resistance on substrate, adopts high-purity tantalum target, and sputtering reacting gas is nitrogen and argon gas;
B: sputtered titanium W film and gold thin film successively on tantalum nitride membrane, use titanium tungsten target and high-purity gold target, sputtering reacting gas is argon gas;
C: do mask with photoresist, etches away unwanted gold outside design configuration with the golden corrosive liquid of iodine and the configuration of KI mixed aqueous solution, falls unwanted titanium tungsten film outside design configuration with titanium tungsten corrosive liquid wet etching;
D: after removing photoresist with potassium hydroxide solution, after rinsing with high purity water, then with analyzing the wiping of pure grade acetone solution;
E: adopt the method for thermal oxidation after the Surface Creation oxide film that tantalum nitride membrane is exposed, carry out plating and finally etch circuitous pattern; Described step e specifically comprises the following steps:
F: by thermal oxidation under the substrate vacuum drying chamber predetermined temperature that cleans up, make tantalum nitride Surface Creation one deck tantalum oxide films;
G: at room temperature respectively through degreaser oil removal treatment and high purity water cleaning, and then activate and high purity water cleaning through the salt picking acid of 10%;
H: the electric current getting scheduled current density is electroplated, circuit deposits one deck gold, and plating terminates rear high purity water and cleans 60s, then poach in boiling water;
I: erode tantalum oxide and tantalum nitride obtains designing circuit pattern with the corrosive liquid of ammonium fluoride and nitric acid mixing.
2. the method for claim 1, is characterized in that, in described steps A, described nitrogen and partial pressure of ar gas are than being N
2: Ar=1:35; The sheet resistance value of described sputtering tantalum nitride membrane is lower than design load 5 ~ 15 Ω/.
3. method as claimed in claim 2, it is characterized in that, in described step B, described titanium tungsten film is 0.05 micron; Described gold thin film is 0.2 micron; The flow of the gas of described argon gas is 70sccm.
4. method as claimed in claim 3, it is characterized in that, in described step C, in described golden corrosive liquid, content of iodine is 60g/L and KI content is 200g/L.
5. method as claimed in claim 4, it is characterized in that, in described step C, described titanium tungsten corrosive liquid is the hydrogen peroxide solution of 30%, and etching time is 10 ~ 12min.
6. method as claimed in claim 5, it is characterized in that, in described step D, described potassium hydroxide solution is 10%; Described high purity water washing time is 60s.
7. method as claimed in claim 6, it is characterized in that, in described step F, described vacuum drying chamber predetermined temperature is arranged between 200 DEG C ~ 280 DEG C; Described oxidization time is 180min ~ 360min.
8. method as claimed in claim 7, it is characterized in that, in described step G, the described degreaser oil removal treatment time is 30s ~ 60s; Described high purity water scavenging period is 60s; Described salt picking acid soak time is 30s ~ 60s.
9. method as claimed in claim 8, it is characterized in that, in described step H, described scheduled current density is 0.1 ~ 0.3A/dm
2; The described poach time is 10min.
10. method as claimed in claim 9, it is characterized in that, in described step I, described ammonium fluoride and described nitric acid weight ratio are 1:5.
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| CN103579107B (en) * | 2013-11-21 | 2015-10-14 | 中国电子科技集团公司第四十一研究所 | A kind of thin film circuit cutting-up method based on mask plating |
| CN106057785B (en) * | 2016-05-18 | 2018-08-14 | 中国电子科技集团公司第四十一研究所 | The method that two kinds of sheet resistance interconnection film resistors of TaN materials are integrated on the same plane of dielectric substrate |
| CN106206402B (en) * | 2016-08-16 | 2017-10-13 | 苏州华博电子科技有限公司 | Accurate film circuit fabrication method on a kind of curved surface |
| CN110715681B (en) * | 2018-07-12 | 2021-02-19 | 山东大学 | Method for preparing high-reflection film optical cavity by gold hot-pressing bonding |
| CN109536889A (en) * | 2018-12-29 | 2019-03-29 | 广州创天电子科技有限公司 | A kind of forming method of ceramic membrane circuit and its splash-proofing sputtering metal coating |
| CN110983276A (en) * | 2019-12-27 | 2020-04-10 | 无锡奥夫特光学技术有限公司 | Preparation method and preparation equipment of tantalum nitride film resistor |
| CN111063619B (en) * | 2019-12-31 | 2021-12-24 | 中国电子科技集团公司第十三研究所 | Electroplating method |
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| CN86104099A (en) * | 1986-11-11 | 1988-05-25 | 上海大学工学院 | P +N diode Noncolloid electroplating for silver salient point electrode |
| CN1221808A (en) * | 1997-10-30 | 1999-07-07 | 国际商业机器公司 | Process improvements for titanium-tungsten etching in presence of electroplated C4'S |
| TW587103B (en) * | 2001-04-06 | 2004-05-11 | Phoenix Prec Technology Corp | Circuit board Ni/Au electroplating process without electroplated wires |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20050035357A (en) * | 2003-10-13 | 2005-04-18 | 주식회사 하이닉스반도체 | Method for fabricating chip size package |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN86104099A (en) * | 1986-11-11 | 1988-05-25 | 上海大学工学院 | P +N diode Noncolloid electroplating for silver salient point electrode |
| CN1221808A (en) * | 1997-10-30 | 1999-07-07 | 国际商业机器公司 | Process improvements for titanium-tungsten etching in presence of electroplated C4'S |
| TW587103B (en) * | 2001-04-06 | 2004-05-11 | Phoenix Prec Technology Corp | Circuit board Ni/Au electroplating process without electroplated wires |
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