CN1032285C - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN1032285C CN1032285C CN92105037A CN92105037A CN1032285C CN 1032285 C CN1032285 C CN 1032285C CN 92105037 A CN92105037 A CN 92105037A CN 92105037 A CN92105037 A CN 92105037A CN 1032285 C CN1032285 C CN 1032285C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims description 101
- 229910052751 metal Inorganic materials 0.000 claims abstract description 224
- 239000002184 metal Substances 0.000 claims abstract description 224
- 239000010410 layer Substances 0.000 claims abstract description 136
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 61
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 60
- 229910052710 silicon Inorganic materials 0.000 claims description 52
- 239000004411 aluminium Substances 0.000 claims description 47
- 239000010703 silicon Substances 0.000 claims description 43
- 230000004888 barrier function Effects 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 28
- 238000010438 heat treatment Methods 0.000 claims description 23
- 238000011049 filling Methods 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 7
- 150000002736 metal compounds Chemical class 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 239000011261 inert gas Substances 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052723 transition metal Inorganic materials 0.000 claims description 3
- 150000003624 transition metals Chemical class 0.000 claims description 3
- 229910018575 Al—Ti Inorganic materials 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims 2
- 229910018182 Al—Cu Inorganic materials 0.000 claims 1
- 229910000765 intermetallic Inorganic materials 0.000 claims 1
- 238000012797 qualification Methods 0.000 claims 1
- 238000012421 spiking Methods 0.000 abstract description 2
- 235000010210 aluminium Nutrition 0.000 description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 40
- 238000000151 deposition Methods 0.000 description 10
- 238000001556 precipitation Methods 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 6
- 230000005012 migration Effects 0.000 description 5
- 238000013508 migration Methods 0.000 description 5
- 230000001590 oxidative effect Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- KMWBBMXGHHLDKL-UHFFFAOYSA-N [AlH3].[Si] Chemical compound [AlH3].[Si] KMWBBMXGHHLDKL-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000010992 reflux Methods 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- 229910018125 Al-Si Inorganic materials 0.000 description 3
- 229910018520 Al—Si Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000000637 aluminium metallisation Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 3
- 229910052742 iron Inorganic materials 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000004062 sedimentation Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 241000860832 Yoda Species 0.000 description 1
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 150000001399 aluminium compounds Chemical class 0.000 description 1
- 238000006701 autoxidation reaction Methods 0.000 description 1
- 239000003518 caustics Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910001338 liquidmetal Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Method of fabricating a semiconductor device, comprising the steps of forming: an insulating interlayer, provided with a hole, on a semiconductor substrate; a metal layer on the semiconductor intermediate, heat-treating the metal layer to fill the hole with the metal, forming a second metal layer on the first metal layer, and heat-treating the second layer to planarize it. As an alternative, the semiconductor device comprises a semiconductor wafer (semiconductor slice). For the metal layer, pure Al or an aluminium alloy without Si component is used. In the semiconductor device, a contact hole is entirely filled with the metal. No Si deposit is formed on the surface after a wiring pattern has been applied, and no Al spiking occurs.
Description
The present invention relates to a kind of method of making semiconductor device, more particularly, relate to a kind of method that in semiconductor device, forms a complanation metal level.The present invention is the improvement of common unsettled U.S. Patent application (sequence number is 07/585,218, and the applying date the is September 19 nineteen ninety) theme to the inventor, and the disclosure of this document is cited as list of references in this application.
Along with semiconductor device processing technology develops towards ultra-large integrated (ULSI), metallization processes has more and more determined output, performance (as: speed of service) and the reliability of device, therefore, people regard metallization processes as in the semiconductor device processing technology most important aspect.And for the semiconductor device of the lower prior art of density, aspect ratio (depth-width ratio) big, contact hole is less because they have physical dimension, and characteristic such as ladder is more shallow, is not a very important problem so the metal ladder covers.Yet along with the semiconductor device integration density increases, it is very little that contact hole has become, and the doped layer that forms on the surface of semiconductor chip has become extremely thin simultaneously.With regard to existing high-density semiconductor device, because the aspect ratio of contact hole becomes increasing, the combined cause that the ladder degree of depth becomes increasing, in order to realize the standard design target of semiconductor device high speed performance, high yield, high reliability, be necessary traditional aluminium (Al) metallization processes is improved.More particularly, in the course of processing of existing high-density semiconductor device, the conventional aluminum metallization processes that uses has brought some such problems, as: the reliability reduction that bad ladder covering higher owing to the contact hole aspect ratio and sputtered aluminum causes and the interior connection fault of aluminium; The contact impedance that is caused by silicon (Si) deposition increases; And the shallow junction characteristic that is caused by aluminium peak value (Al spking) reduces.
Provide at present various new technologies to overcome these problems in the conventional aluminum metallization process.For example, following technology has been proposed, reduce owing to connecting the semiconductor reliability that fault causes in the aluminium in order to preventing, wherein, the cause that connects fault in the aluminium be because the contact hole aspect ratio is big and the aluminum metallization process in the bad ladder covering of sputtered aluminum cause.
People's such as Yukiyosu Sugano Japanese Unexamined Patent Publication No is 62-132348, announced the conforming method of the film that a kind of improvement forms on the steep ladder of semiconductor device, this method is included in metal wiring layer of (it is positioned on the semiconductor chip) formation on the steep ladder, then in such a way with this wiring layer heat fusing, so that the metal wiring layer complanation.People's such as Shinpei Iijma Japanese patent application, publication number is 63-99546, announced and a kind ofly improved the wiring reliability, and can form the method for multilayer interconnection that wherein metal wiring layer is by its heating and fusing are formed on a substrate with contact hole and ladder.Particularly, people such as Shinpei Iijma have proposed a kind of method of making semiconductor device, this method comprises the following steps: to form a plurality of devices on a semiconductor chip, insulating barrier of deposit on a plurality of devices, in insulating barrier, form the contact hole that can lead to the device predeterminated position, surface at insulating barrier and contact hole forms one deck titanium nitride film, deposit one metallization wiring layer on the whole surface of titanium nitride film, be heated then so that its fusing, flow, thereby make the surface planarization of metal level, and according to this metal surface of wiring pattern etching of design in advance and nitrided iron film to form at least the first wiring layer.
People's such as Masahiro Shimizu Japanese patent application, publication number 62-10341, proposed a kind of can prevent the wiring open circuit, to improve the method for semiconductor device reliability, this method comprises that (for example on a contact hole on dielectric film surface) forms the aluminium conducting film with good spreadability on a certain ladder.
Particularly, people such as Masahiro Shimizu have disclosed a kind of method of making semiconductor device, and this method comprises: be coated with the solution that last layer contains liquid aluminium (or aluminium compound) on silicon chip, then it solidified to form the aluminium conducting film.
According to all above-mentioned methods, can and make it reflux filling contact hole by the fusing aluminum or aluminum alloy.Generally speaking, in reflow step, the aluminum or aluminum alloy metal level is heated to it more than fusing point, molten metal can flow to contact hole and with its filling as a result, and this reflow step exists following shortcoming with not enough.At first, semiconductor wafer must be horizontally disposed with so that contact hole can be flowed, the molten metal material is filled rightly.The second, the liquid-metal layer that flows to contact hole has one than low surface tension, therefore when solidified, thereby may shrink or the crooked bottom semi-conducting material that exposes.Further, can't accurately control heat treatment temperature, so just be difficult to produce again expected result.In addition, although these methods can be come filling contact hole with the deposite metal of metal level, yet the other parts of metal level (contact hole outside) may become coarse, thereby can damage follow-up protective coating processing.So,, then have necessity and carry out the second metal level coating processing for these coarse parts that make metal level become smooth or complanation.
Know at present,, improve semi-conductive reliability, form a barrier layer in the contact hole that can on semiconductor wafer, form by stoping the reduction of the shallow junction characteristic that causes by the aluminium peak value.For example, people's such as Natsuki Yokoyama United States Patent (USP) has been set forth a kind of semiconductor device for the 4th, 897, No. 709, this semiconductor device has a titanium nitride film that forms (barrier layer) on contact hole, in order to prevent the reaction between metal wiring layer and the semiconductor chip.This titanium nitride film can form with a kind of low pressure chemical vapor deposition method, and this low pressure chemical vapor deposition method can realize with a cold mould CVD device.Consequent film has very excellent characteristic, can provide excellent step to cover for the quite tiny hole of wide aspect ratio.After forming titanium nitride film, use aluminium alloy to form a metal wiring layer with sputtering method.
People's such as Clarence J.Tracy United States Patent (USP) has been announced a kind of multilevel metallization processing method for the 4th, 970, No. 176, and it can substitute fusing aluminum or aluminum alloy filling contact hole, and can improve the covering of metal ladder.According to above-mentioned patent, be deposited on the first of metal level predetermined thickness on the semiconductor wafer at low temperatures; Then, temperature is increased to about 400 ℃-500 ℃, this can make metal level reflux when the remainder of deposited metal.This metal level refluxes passes through granularity and increases, recrystallizes and whole diffusion is carried out.
People such as One have disclosed, and when the semiconductor chip temperature was higher than 500 ℃, the fluidity of aluminium-silicon can increase (referring to VMIC conference proceedings in 11 to 12 June of nineteen ninety, the 76th page to 82 pages, people's such as Hisako One paper) suddenly.According to people's such as One result of study, near 500 ℃ the time, the stress of Al-1%Si film meeting flip-flop, and under this temperature, stress decay can appear rapidly in Al-1%Si film.In addition, for filling contact hole satisfactorily, the temperature of semiconductor chip must maintain between 500 ℃-550 ℃.The mechanism difference that promotion metal level in people (4,970, the 176) patents such as this mechanism and Tracy refluxes.
The invention of one of present inventor unsettled being entitled as before the last project of United States Patent (USP) trademark office (U.S.P.T.O) " a kind of method that in semiconductor device, forms metal level " (" AMethed for Forming a Metal Layer in a Semiconductor Device ").This invention relates to a kind of method that forms the metal wiring layer that passes contact hole in semiconductor device, the method comprising the steps of: (below 200 ℃) depositing metal at low temperatures, then temperature be this depositing metal material fusing point 80% to the scope between its fusing point, heating metals deposited material.
Figure 1A, 1B, 1C have provided a kind of method that forms metal level according to foregoing invention, and with reference to Figure 1A, it has provided the process that forms the first metal layer, and contact hole 2 forms on semiconductor chip 10.Then, this substrate is put into (not shown) in the sputter reative cell, in this reative cell, forms the first metal layer 4 by depositing metal (Al or Al alloy), its temperature is below 200 ℃ or 200 ℃, and carries out under predetermined level of vacuum.Layer 4 has the polycrystalline kernel structure.
Figure 1B has described the method for filling contact hole, with reference to Figure 1B, the substrate structure that is obtained by last process is moved to another sputter reative cell (not shown), then, not opening vacuum, temperature is under 550 ℃ the situation, heats at least 2 minutes, thereby makes metal filled contact hole.Simultaneously, the pressure of reative cell is preferably low as far as possible, so that the aluminium atom has higher surface free energy.In this way, metal filling contact hole more easily.Parameter 4a represents the metal of filling contact hole 2.
Heat-treatment temperature range shown in Figure 1B in the process must be between 80% and melting point metal of melting point metal, and changes according to used special aluminum alloy or aluminium.
Because the heat treated temperature of metal level is lower than 660 ℃ of the fusing points of aluminium, so metal level does not melt.For example at 550 ℃, when the heat treatment of higher temperature, these are deposited the aluminium atom sputter below 150 ℃, are not fusing but migration.Can increase this migration when surf zone during inhomogeneous or polycrystalline grain, this is because the cause that the energy of those surface atoms that do not contact fully with atom on every side increases.So, in the heat treatment amount, initial sputter, the polycrystalline granulosa can increase the migration of atom.
Fig. 1 C has provided the process that forms second metal level 5, and especially, second metal level 5 is that the remainder by the required whole metal layer thickness of deposit forms, and its deposition temperature is selected according to the reliability of required semiconductor device.So just finished the formation of whole (compound) metal level.
According to said method, by the use sputtering equipment identical, and cool off depositing metal gradually with the traditional hot sedimentation, just can use metal complete filling contact hole at an easy rate.Even so the contact hole that aspect ratio is very big, also can be by complete filling.
But, when in contact hole, having the space to form or cover when insufficient when the ladder of metal level, although can be with deposit the semiconductor wafer of metal level maintain under a predetermined temperature and the vacuum level, still can't filling contact hole.Further, although second metal level that can on the semiconductor wafer of existing deposit initial metal layer, form subsequently, but still can't guarantee that excellent contact hole ladder covers, so the reliability of the semiconductor device of manufacturing will descend.
In the silicon technology stage the earliest, the contact structures of employing are direct deposit fine aluminiums on silicon.Yet aluminium-silicon contact shows some bad contact performances, as the knot peak value during watering knot (junction spiking).This sintering step is carved at contacting metal film Bei Dian Ji And that pattern carries out later on.For aluminium-silicon contact point situation, this sintering can cause that the natural oxidizing layer that aluminium and silicon face form reacts.As aluminium and thin SiO
2When layer reacts, can produce Al
2O
3If, and be in the good Ohmic contact, this natural oxidizing layer is finally understood full consumption and is fallen.So, the Al of aluminium by generating
2O
3Layer is diffused into silicon face, forms metal-silicon contact closely.Aluminium must pass through Al
2O
3Layer is diffused into remaining SiO
2On.Along with Al
2O
3The increase of layer thickness, it needs the longer time aluminium infiltration.So, if natural oxidizing layer is too thick, Al
2O
3Layer finally also can become blocked up, so that aluminium can't be by its diffusion.In this case, just can not be with all SiO
2Consume, and will produce bad ohmic contact.Al permeates Al
2O
3Speed be the function of temperature, for sintering temperature of allowing and sintering number, Al
2O
3Thickness should be between 5-10 dust scopes.Because maximum Al
2O
3The autoxidation layer thickness of thickness and consumption is the same order of magnitude, so should determine the upper limit of the permission thickness of natural oxidizing layer.The time that silicon face is exposed in the aerobic environment is long more, and natural oxidizing layer is thick more.So, in most of contact layer technologies, be before wafer is placed into the deposition chamber that is used for the metal deposit, to finish the surface cleaning program.
Between 450 ℃-500 ℃ of contact alloy temperature, aluminium absorbs 0.5%-1% silicon.If aluminum layer is heated to 450 ℃, and provide a silicon source, under solution state, aluminium will absorb silicon and reach 0.5wt% (percentage by weight) up to the concentration of silicon so.Semiconductor chip is as this silicon source, when temperature raises, and will be from the silicon of substrate by diffusing into aluminium.If a large amount of aluminium is arranged, will be diffused into the aluminium film from a large amount of silicon under Al-Si interface.Simultaneously, can promptly move from the aluminium of aluminium film and go to fill the space that forms by free silica.If the aluminium length of penetration is greater than the PN-junction depth under the contact-making surface, so, knot can present very big leakage current, even becomes short circuit.This phenomenon is called the PN junction peak value.
In order to alleviate contact-making surface PN junction spike problem, when deposit aluminium, in the aluminium film, add silicon.When making the integrated circuit contact-making surface with interior the connection, extensively adopted aluminium-silicon alloy (silicon is put 1.0 percentage by weights), use aluminium-silicon alloy to substitute fine aluminium and can alleviate the knot spike problem, but unfortunately, this will cause the another one problem again.Say that more specifically in the cooling cycle of annealing in process, the solubility of the silicon in the aluminium can reduce along with the reduction of temperature.So aluminium is with respect to the silicon supersaturation that becomes, this will cause from the silicon of aluminium-silicon solution assembles and precipitation.This Al-the SiO that is deposited in the contact-making surface
2Interface and Al-Si interface will occur.If these are deposited on the contact interface and form and generation n
+Si can cause the increase of undesirable contact impedance so.In addition, at n
+Si precipitation is approximately greater than 1.5 μ places, will produce very big flux divergence (flwx-divergence) in electric current.This will cause losing efficacy owing to the early stage conductor that electron transfer induction open-circuit condition produces.
Fig. 2 has described after the metallization, the silicon precipitation that forms on surface of semiconductor chip.Obviously, these silicon precipitations should be eliminated.Up to the present, can only use sand milling, cross the method for etching or wet etching, perhaps contain the corrosive agent that to eliminate the group of precipitation from substrate, remove siliceous deposits by use.
But when deposited metal at high temperature, the silicon precipitation is difficult for removing.When etching away siliceous deposits with mistake, its figure can be sent to basalis, and these figures can left behind after etching is finished excessively.So the surface quality of semiconductor chip and outward appearance are still bad.
Based on above reason, need a kind of method that can in semiconductor device, form a planar metal wiring layer, it can overcome shortcoming and deficiency in all above-mentioned existing technical processs.This top invention then at can satisfy this requirement.
Therefore, the purpose of this invention is to provide a kind of improving one's methods of metal wiring layer that form in semiconductor device, wherein, semiconductor device has the contact hole that forms on semiconductor chip.The method comprising the steps of: a kind of metal of deposit, complete filling contact hole then is to obtain reliable metal wiring layer.
Another object of the present invention provides a kind of for the metal line pattern forms improving one's methods of a metal level, and this method can not produce any silicon precipitation in subsequent process.
According to the present invention, a kind of method of making semiconductor device is provided, the method comprising the steps of: form an insulating interlayer on semiconductor chip; At the opening that provides on semiconductor chip, to form on the insulating interlayer; On semiconductor wafer, form a first metal layer; This first metal layer is heat-treated, with described metal filled opening; On the first metal layer, form one second metal level, then second metal level is heat-treated, so that this layer planeization.
The first metal layer is to form by a kind of metal such as aluminum or aluminum alloy of deposit under the condition of low temperature, vacuum.Suitable aluminium alloy comprises, Al-0.5%Cu for example, and Al-1%Si, Al-1%Si-O.5%Cu or the like.The deposit the first metal layer is preferably carrying out below 150 ℃.Temperature is low more, and when follow-up heat treatment, metallic atom is easy more to be moved to opening part./ 3rd to 2/3rds of whole (compound) metal layer thickness (being first and second metal layer thickness sum) that the thickness of the first metal layer is preferably predetermined.
Form in a vacuum after the first metal layer, under the situation of not opening vacuum, this metal level is heat-treated.This heat treatment is in a kind of 10 milli torrs or the inert gas environment below the 10 milli torrs, or 5 * 10
-7Torr or 5 * 10
-7In the following vacuum, using gases conduction method or RTA (fast fast thermal annealing) method, the heating semiconductor chip realizes, its temperature range O.8Tm-change between the Tm, preferably at 500 ℃-550 ℃, wherein Tm is the fusing point of this metal.The fusing point of fine aluminium is 660 ℃ herein.For aluminium alloy, then can see its eutectic point as fusing point.Al-1%Si alloy, the eutectic point of Al-0.5%Cu alloy and Al-0.5%Cu-1%Si alloy is respectively 577 ℃, 548 ℃ and 520 ℃.Heat treatment is (as N at inert gas
2, Ar) or a kind of reducing gas (H
2) environment under carry out.When metal level is heat-treated, move to opening in order to reduce the surface free energy metallic atom.Consequently opening is by metal filled.Along with metallic atom moves to opening, metal surface area can reduce.So the protuberance branch of metal level disappears from the top of opening, it is big that the porch of opening becomes.Therefore, during later deposit second metal level, can obtain good metal layer ladder and cover.
If in above-mentioned heat treatment step, open vacuum, will cause that oxidation forms Al
2O
3Film, this Al
2O
3Film can stop the aluminium atom to move to opening part under said temperature, so opening just can not be fully by metal filled, clearly, this is that people are undesirable.When adopting hydrogen conduction method, above-mentioned heat treatment step preferably continues 1-5 minutes, and when using RTA equipment, the heat treatment of metal level is then preferably needed several 20-30 seconds cycles, or continue about 2 minutes.
After this, by the identical mode of above-mentioned formation the first metal layer, form second metal level by depositing metal, but the temperature of latter's metal deposit is below 350 ℃.After second metal level forms, also to second metal level be heat-treated according to the mode same with the first metal layer heat treatment phase.
All above-mentioned steps all are at a kind of 10 milli torrs or 10 millis in the inert gas below the torrs, perhaps 5 * 10
-7Torr or 5 * 10
-7Carry out in the vacuum below the torr, and do not open vacuum, this is one of most important characteristic of the present invention.
According to one embodiment of present invention, on semiconductor chip, form after the opening, on whole semiconductor substrate (comprising opening) surface, form a diffusion impervious layer.This barrier layer, as titanium or titanium nitride and is made up of the compound of a kind of transition metal or transition metal.
When the wiring layer of being made by aluminum or aluminum alloy is connected by the surface of contact hole with a doping thin layer district, and when having finished heat treatment, aluminium is diffused into doped region and penetrates PN-knot, and this just causes PN-knot peak value and might damage PN-knot.
In order to prevent the reaction between aluminium and the semiconductor chip, a kind of method is provided, this method is included between the surface of the wiring layer of the one-tenth that is made of aluminum or aluminum alloy and semiconductor chip a barrier layer that is made of titanium nitride is set.For example, at J.Vac.Sci.Technol., A
4(4) announced the technology that forms nitrided iron with a kind of active sputtering method in (1986, the 1850-1854 page).United States Patent (USP) the 4th, 897 is also announced for No. 709, and on the inner surface in the superfine hole of a wide aspect ratio, the good titanium nitride film of used thickness uniform properties is as the barrier layer.
In addition, people such as Yoda Dakashi have also proposed a kind of method of making semiconductor device, the method comprising the steps of: form double-deck barrier layer with stop wiring layer and semiconductor chip or and the contact hole inner surface on insulating barrier between react, contact hole as described in heating semiconductor chip to a design temperature, filling then with depositing metal (as aluminium alloy) (referring to No. the 90-15227, the 01-No. 061557 corresponding South Korea publication application of Japanese patent application of submission on March 14th, 1 989).
Get back to the present invention now,, can both on the inner surface of contact openings of the present invention, form a diffusion impervious layer at an easy rate by using above-mentioned any technology.This barrier layer preferably includes first barrier layer (as titanium coating) and second barrier layer (as the nitrided iron layer).The thickness on first barrier layer is 100-300 dusts preferably, and the thickness on second barrier layer is 200-1500 dusts preferably.
According to a further aspect in the invention, on second metal level, form an anti-reflecting layer, carve harmful reflection of step to prevent subsequent optical, thereby improve the reliability of metal wiring layer.
Further, according to the present invention, a kind of method of making semiconductor device is provided, the method comprising the steps of: the semiconductor wafer that opening is provided above providing, on this wafer, form a metal level, then this metal level is heat-treated using metal filled opening, the metal that wherein forms metal layers is the aluminum or aluminum alloy of siliceous composition not.Opening of the present invention preferably has the contact hole of a ladder at an upper portion thereof.
Be used for realizing that more suitable metal of the present invention comprises, for example: fine aluminium, aluminium-copper and aluminium-titanium.In addition, the eutectic point of Al-Ti alloy is 665 ℃.According to a preferable example of executing of the present invention, metal level is formed by such method, and the method comprising the steps of: form the first metal layer by the deposit the first metal layer, the first metal layer is heat-treated, then deposit second metal level on the first metal layer.It is fine aluminium or the aluminium alloy that does not contain element silicon that one deck is arranged in first or second metal level, and another layer then is the aluminium alloy that contains element silicon.Metal level also can form by a kind of metal and a kind of metal that contains element silicon that does not contain element silicon of consecutive deposition, and wherein every kind of deposit is carried out once at least.The metal that does not contain element silicon when temperature reduces absorbs silicon atom from the metal that contains element silicon.So, can eliminate and form siliceous deposits on the surface of semiconductor chip.In addition, the metal that does not contain element silicon absorbs silicon atom from the metal that contains element silicon to absorb silicon atom than semiconductor chip easier, so can eliminate the aluminium peak value effectively.
According to a further aspect in the invention, after forming opening, on whole semiconductor wafer surface, form a barrier layer, react between metal level and semiconductor chip or the insulating barrier so that prevent.This barrier layer comprises a kind of high-melting point metal compound that has.Opening can be a contact hole that a ladder is arranged at an upper portion thereof, and its aspect ratio is more than 1.0 or 1.0.
Metal level is to form in the vacuum sputtering chamber below 150 ℃ in temperature preferably.The temperature of heat-treated metal layer can be 0.8Tm-Tm.The step of all above-mentioned formation metal wiring layers is preferably carried out in a vacuum, and does not open vacuum between each step.
By following detailed description relevant of the present invention with reference to accompanying drawing, will help to understand better aforementioned purpose of the present invention, in the drawings:
Figure 1A, 1B, 1C have described the method (described as Application No. 07/585,218) of the formation metal level of prior art;
Fig. 2 has described in the prior art method of Fig. 1 after the metallization, the silicon precipitation that forms on the surface of semiconductor chip;
Fig. 3 A-3D represents an embodiment according to the method for formation metal wiring layer of the present invention;
Fig. 4 A-4D represents according to another of the method for formation metal wiring layer of the present invention
Embodiment;
Fig. 5 is a SEM figure, and it has provided an opening by the metal complete filling, and wherein metal is to form on the semiconductor chip that an a method according to the present present invention obtains;
Fig. 6 has described the final pure surface of semiconductor chip that obtains of a method according to the present present invention.
The description of preferred embodiment:
Embodiment 1
Fig. 3 A-3D has described according to the present invention, has formed an embodiment of the method for a metal wiring structure.
Fig. 3 A has described a step that forms the first metal layer.More specifically, on the semiconductor chip that has insulating interlayer (22) (21), forming diameter is 0.8 μ m, and the opening (23) of ladder part is arranged on it, purifies substrate (21) then.
Next step will comprise that barrier layer (24) such as the high melting point metal compound of TiN is deposited on the expose portion of the whole surface of insulating interlayer (22) and semiconductor chip (21).The thickness on barrier layer (24) is preferably between 200-1500 dusts.Then substrate (21) is put in the sputter reative cell (not drawing among the figure), this by deposit such as aluminium or not the aluminium alloy of siliceous composition form the first metal layer, its thickness be whole (compound) metal level 2/3rds (when the phase of whole metal level, thickness was 6000 dusts, it is 4000 dusts), its temperature approximately is 150 ℃, and under predetermined vacuum level, so the first metal layer that forms has little aluminium grain and high surface free energy.
Fig. 3 B has described the step of filling opening 23, furtherly, under the situation of not opening vacuum chamber, semiconductor wafer is moved on to another sputter reative cell (not shown),, the first metal layer (25) is heat-treated at this, preferably 550 ℃ and lasting 3 minutes of its temperature, thereby cause that aluminium grain locates migration to opening (23), the migration of aluminium grain causes that surface free energy reduces, thereby its surface area is reduced and can usefulness aluminium complete filling opening shown in Fig. 3 B.
Fig. 3 C has described at the first metal layer (25) and has gone up the step that forms second metal level (26), more particularly, in temperature below 350 ℃, by the remainder of the required gross thickness of the whole metal level of deposit, form second metal level (26), thereby finish the formation of whole metal level.What form second metal level (26) use is such as Al-Si, or the aluminium alloy of Al-Cu-siliceous compositions such as Si.
Fig. 3 D has described by using with Chuan Tong De Erosion process at quarter (as is known in semiconductor processes widely used) and has removed the metal line pattern that the predetermined portions of second metal level (26), the first metal layer (25) and barrier layer (24) forms.
Embodiment 2
Fig. 4 A-4D has described according to the present invention, forms another embodiment of metal line method of patterning.
Fig. 4 A has described the step that forms the first metal layer, in more detail, has SiO
2On the semiconductor chip (31) of the insulating barrier (33) that constitutes, form diameter 0.8 μ m, and have the opening (35) of ladder at an upper portion thereof, purify substrate (31) then.For stop wiring layer and semiconductor chip (31) or and insulating barrier (33) between reaction, on whole insulating barrier (33) surface and comprise on the expose portion of semiconductor chip (31) of opening (35), form first diffusion impervious layer of forming by Ti (37); Its thickness is preferably between 100-500 dusts; Go up formation second diffusion impervious layer (39) at first diffusion impervious layer (37), it forms (its thickness is preferably between 200-1500 dusts) by TiN.
Next step is approximately 450 ℃ N in temperature
2Under the gaseous environment whole semiconductor wafer is heat-treated, continue half an hour.Then, go up deposit the first metal layer (41) at second diffusion impervious layer (39), its thickness is 2000-4000 dusts preferably, and the alloy of use is Al-0.5%Cu for example.Al-1%Si, or Al-0.5%Cu-1%Si, heating-up temperature is below 150 ℃ or 150 ℃, the method for use or sputtering method or vacuum evapn sedimentation.
Fig. 4 B has described a first step of heat-treated metal layer (41), furtherly, is under the situation of not opening vacuum, and using gases conduction method is at temperature 0.8Tm-Tm, 10
-2Torr or 10
-2In a kind of inert gas below the torr, or 5 * 10
-7Torr or 5 * 10
-7In the following vacuum of torr, metal level (41) is carried out heat treatment in 1-5 minutes.
Fig. 4 C has described the step that forms second metal level (43), and under the situation of not opening vacuum, temperature is below 350 ℃, forms second metal level on the whole surface of the first metal layer (41), and its thickness is preferably between 2000-4000 dusts.
Fig. 4 D has described first second step that second metal level (43) is heat-treated, thereby makes the surface planarization of metal level.This step is under the condition of not opening vacuum, by carrying out with the same mode of first heat treatment step.Thereby form an anti-reflecting layer that comprises such as the transistion metal compound of TiN on the surface of second metal level (43), its thickness is preferably between 200-500 dusts.Then, carve process, can obtain a metal line pattern (not shown) according to Chuan Tong De Erosion.
According to principle of the present invention, when metal level was heat-treated, the metallic atom of the metal level that forms on semiconductor wafer moved to opening.When metal level under lower temperature during deposit, in follow-up heat treatment, metallic atom is easier to be moved to opening part.In addition, after first deposited metal was heat-treated, deposit second metal level was then heat-treated it at low temperatures.In this way, can obtain the complanation metal level, and be easy to and carry out follow-up De Erosion effectively and carve step.And according to the present invention, by suitably handling second deposited metal, opening can be fully by metal filled.The microphoto of Fig. 5 has been described this result.
Further, according to the present invention, contain the metal of element silicon with do not contain the metal of element silicon can be continuously or be deposited simultaneously to form complex metal layer, when the temperature of semiconductor chip reduced, the metal level that does not contain element silicon absorbed the silicon atom of the metal level that contains element silicon.So, after forming wiring pattern, do not form the silicon precipitation on the surface of semiconductor device, and can eliminate the Al peak value fully.As shown in Figure 6, can realize a pure surface of semiconductor chip, thereby, a reliable metal line pattern can be obtained.
Although with reference to specific embodiment, the present invention has been described, this professional skilled person can make various modifications under defined spirit of the present invention and range of condition as the accompanying Claim book.
Claims (38)
1. method of making semiconductor device comprises step:
On semiconductor chip 31, form an insulating interlayer 33;
An opening 35 is provided on described insulating interlayer 33;
On described insulating interlayer, form the first metal layer 41;
Described the first metal layer 41 is heat-treated to use the metal filled described opening 35 of described the first metal layer 41;
On described the first metal layer, form one second metal level 43, thereby a complex metal layer is provided; With
The method that is used in the surface planarization of second metal level 43 that makes generation under the temperature in 0.8Tm～Tm scope is heat-treated second metal level 43, and wherein, Tm is the fusing point of the metal of described second metal level.
2. according to the process of claim 1 wherein: described opening 35 extends to the surface of described semiconductor chip 31, thereby exposes the part on described semiconductor chip 31 surfaces; With
The step that forms described the first metal layer is included in the step that forms described the first metal layer 41 above the surface portion of exposure of described insulating interlayer 33 and described semiconductor chip 31.
3. according to the method for claim 2, also comprise the following steps: on the surface of described insulating interlayer 33 and limit on the semiconductor chip 31 of described opening 35 to form diffusion impervious layer 37,39.
4. according to the method for claim 3, wherein, described diffusion impervious layer 37,39 is made of a kind of metal of selecting from comprise transition metal and transistion metal compound.
5. according to the method for claim 3, wherein, described diffusion impervious layer 37,39 is made of the material of selecting from comprise titanium and titanium nitride.
6. according to the method for claim 3, wherein, the formation step of described diffusion impervious layer 37,39 comprises step:
On the semiconductor chip 31 of described insulating interlayer 33 and the described opening 35 of qualification, form first diffusion impervious layer 37; With
On described first diffusion impervious layer 37, form second diffusion impervious layer 39.
7. according to the method for claim 6, wherein, described first barrier layer 37 is made of Ti, and described second barrier layer is made of titanium nitride.
8. according to the method for claim 6, wherein, the thickness on described first barrier layer is 100-500 dusts, and the thickness on second barrier layer is 200-1500 dusts.
9. according to the method for claim 2, wherein, described the first metal layer forms step and comprises: in a vacuum, under the low temperature, metal is deposited on the exposed surface portion thereof of described insulating interlayer 33 and described semiconductor chip 31.
10. according to the method for claim 9, wherein said low temperature is below 150 ℃.
11. according to the process of claim 1 wherein, described to the first metal layer step of heat treatment range of temperature for O.8Tm-carry out under the Tm, wherein Tm is the fusing point of this metal.
12. according to the method for claim 9, wherein, described is to carry out under the condition of not opening vacuum to the first metal layer step of heat treatment.
13. according to the process of claim 1 wherein, the thickness of described the first metal layer 41 is 1/3rd to 2/3rds of described composite bed predetermined thickness.
14. according to the process of claim 1 wherein, described second metal form step be included in temperature be below 350 ℃ the time on described the first metal layer the step of a kind of metal of deposit.
15. according to the process of claim 1 wherein that the thickness of described second metal level 43 is 1/3rd to 2/3rds of described composite bed predetermined thickness.
16. according to the process of claim 1 wherein, all under vacuum, carry out in steps, and do not open vacuum between each step.
17. according to the process of claim 1 wherein, in a kind of inert gas environment, carry out in steps.
18. according to the process of claim 1 wherein, in a kind of reducing gas environment, carry out in steps.
19. according to the method for claim 17, wherein, described step be pressure be equal to or less than 10 the milli torrs inert gas environment in carry out.
20., further be included in the step that forms an anti-reflecting layer 46 on described second metal level according to the method for claim 2.
21. according to the method for claim 20, wherein, described anti-reflecting layer 45 is made of a kind of transistion metal compound.
22. according to the method for claim 21, wherein, described transistion metal compound is a titanium nitride.
23. according to the method for claim 2, wherein, described first and second metal level 41,43 is made of a kind of metal of selecting from the one group of material that comprises aluminium and aluminium alloy.
24. according to the process of claim 1 wherein, described opening 35 is contact holes that a ladder is arranged at an upper portion thereof.
25. according to the process of claim 1 wherein, described the first metal layer 41 is by from aluminium with do not conform to a kind of metal of selecting the aluminium alloy of element silicon and constitute, described second metal level 43 is then by from aluminium with contain a kind of metal of selecting the aluminium alloy of element silicon and constitute.
26. according to the process of claim 1 wherein described the first metal layer 41 by from aluminium with contain a kind of metal of selecting the aluminium alloy of element silicon and constitute, described second metal level 43 is then by from aluminium with do not conform to a kind of metal of selecting the aluminium alloy of element silicon and constitute.
27. a method of making semiconductor device comprises step:
On Semiconductor substrate 21, form an insulating interlayer 22;
On described insulating interlayer 22, form an opening 23 to expose the part surface of described Semiconductor substrate 21;
On that part of surface of the inner surface of described insulating interlayer, described opening 23 and the described Semiconductor substrate that exposes, form metal level 25; And
Described metal level 25 is heat-treated, so that with the described opening 23 of the metal complete filling of described metal level;
Wherein, the metal of described metal level 25 is made of a kind of metal of selecting from the aluminium alloy family of fine aluminium and siliceous composition not.
28., further be included in the step that forms a barrier layer 24 on the whole surface of the described semiconductor wafer that contains the surface that limits described opening 23 according to a kind of method of claim 27.29. a kind of methods according to claim 27, wherein, described aluminium alloy is Al-Cu alloy and Al-Ti alloy.
30. according to a kind of method of claim 27, wherein, described opening 23 comprises and forms a contact hole that a step portion is arranged thereon.
31. according to a kind of method of claim 27, wherein, described metal level forms step and realizes by using sputter procedure a kind of metal of deposit on described semiconductor wafer in a vacuum.
32. according to the process of claim 1 wherein, it is to carry out being equal to or less than under 150 ℃ the temperature that described metal level forms step.
33. according to the method for claim 27, wherein, the aspect ratio of described opening 23 is greater than 1.0.
34. according to the method for claim 27, wherein, described metal level heat treatment step is under vacuum and does not open under the condition of vacuum and carry out in sputtering chamber.
35. according to the method for claim 27, wherein, described metal level heat treatment step is to carry out under its scope is temperature between 80% and the described melting point metal of described melting point metal.
36. according to the method for claim 28, wherein, described barrier layer 24 is made of the high-melting point metal compound.
37. according to the method for claim 36, wherein, described metallic compound is a titanium nitride.
38. according to a kind of method of claim 27, further be included in the step that forms another metal level 26 on the described metal level 25, described another metal level 26 contains element silicon.
39. according to a kind of method of claim 27, wherein, described metal level forms step and comprises use sputtering technology deposit the first metal layer 25 step of deposit second metal level 26 on described the first metal layer 25 again.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR91-10766 | 1991-06-27 | ||
| KR910010766 | 1991-06-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1068681A CN1068681A (en) | 1993-02-03 |
| CN1032285C true CN1032285C (en) | 1996-07-10 |
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ID=19316392
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN92105037A Expired - Lifetime CN1032285C (en) | 1991-06-27 | 1992-06-25 | Method for manufacturing semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR950010042B1 (en) |
| CN (1) | CN1032285C (en) |
| NL (1) | NL194710C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW402778B (en) * | 1996-07-12 | 2000-08-21 | Applied Materials Inc | Aluminum hole filling using ionized metal adhesion layer |
| KR100244432B1 (en) * | 1996-11-19 | 2000-03-02 | 김영환 | A method for forming aluminum layer in semiconductor device |
| KR100414746B1 (en) * | 1996-12-31 | 2004-03-31 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device |
| KR100649972B1 (en) * | 2005-06-10 | 2006-11-27 | 주식회사 하이닉스반도체 | Method for manufacturing metal line in semiconductor device |
| CN101694835A (en) * | 2009-10-13 | 2010-04-14 | 上海宏力半导体制造有限公司 | Manufacture method of metal layer |
| CN104409325B (en) * | 2014-11-17 | 2017-05-10 | 福建福顺微电子有限公司 | Method for reducing aluminum bar gap in thick aluminum evaporating coating process of integrated circuit |
| KR102034394B1 (en) * | 2018-09-17 | 2019-10-18 | 주식회사 코윈디에스티 | Method for forming fine wiring using laser chemical vapor deposition |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS62293740A (en) * | 1986-06-13 | 1987-12-21 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0727879B2 (en) * | 1989-03-14 | 1995-03-29 | 株式会社東芝 | Method for manufacturing semiconductor device |
-
1992
- 1992-05-06 KR KR1019920007671A patent/KR950010042B1/en not_active IP Right Cessation
- 1992-06-19 NL NL9201095A patent/NL194710C/en not_active IP Right Cessation
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| NL194710B (en) | 2002-08-01 |
| CN1068681A (en) | 1993-02-03 |
| KR950010042B1 (en) | 1995-09-06 |
| NL194710C (en) | 2002-12-03 |
| NL9201095A (en) | 1993-01-18 |
| KR930001311A (en) | 1993-01-16 |
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