CN103219950A - High-efficiency power amplification circuit with three-path combination secondary compensation function - Google Patents
High-efficiency power amplification circuit with three-path combination secondary compensation function Download PDFInfo
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- CN103219950A CN103219950A CN2013100812993A CN201310081299A CN103219950A CN 103219950 A CN103219950 A CN 103219950A CN 2013100812993 A CN2013100812993 A CN 2013100812993A CN 201310081299 A CN201310081299 A CN 201310081299A CN 103219950 A CN103219950 A CN 103219950A
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Abstract
The invention discloses a high-efficiency power amplification circuit with a three-path combination secondary compensation function. The circuit comprises three paths of final-stage amplification circuits, a reference signal circuit, an error signal extraction circuit, a first combiner and a second combiner, wherein the three paths of final-stage amplification circuits comprise a first final-stage amplification circuit, a second final-stage amplification circuit and a third final-stage amplification circuit. An amplified signal is extracted from any of the three paths of final-stage amplification circuits, and is subtracted from an undistorted main signal to obtain an error signal, the error signal is divided into two paths for regulation, the two paths of the error signal are input into the other two paths of final-stage amplification circuits respectively, output signals of two of the three paths of final amplification circuits are primarily compensated by the first combiner, and output signals of the first combiner and the other one path of final-stage amplification circuit are secondarily compensated by the second combiner. Distorted signals generated by a power amplifier are compensated by the primary and secondary compensation, and a good linear effect is achieved.
Description
Technical field
The present invention relates to power amplification circuit, relate in particular to and a kind ofly have three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function.
Background technology
Current digital pre-distortion technology is widely used at wireless communication base station system, feed forward power amplifier still is used in some application scenario, yet the shortcoming of traditional Feed Forward Power Amplifier based on main amplifier and error amplifier is, because error amplifier itself does not have contribution to the power output of power amplifier, and error amplifier itself has power consumption, therefore cause the efficient of conventional feed forward power amplifier lower, even adopted the Doherty technical efficiency also can only reach about 22%.Therefore can work out a kind of high efficiency, simultaneously but also can need not extra circuit and realize that linearisation is when the previous further problem of further investigation that is worth of not only having had.
Summary of the invention
The object of the present invention is to provide a kind ofly to have three the tunnel and close the high efficiency power amplifier that the road secondary offsets function, this amplifier can be realized the high efficiency of the radiofrequency signal of mobile communication frequency range and high linear amplification.
The technical solution adopted for the present invention to solve the technical problems is:
Provide a kind of and have three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function, comprise that three tunnel end amplifying circuits, reference signal circuit, error signal extract circuit, first mixer and second mixer; Described three tunnel end amplifying circuits comprise the first final stage amplifying circuit, the second final stage amplifying circuit and the 3rd final stage amplifying circuit;
Undistorted main signal is carried out amplitude to described reference signal circuit and phase adjusted obtains reference signal;
Described error signal is extracted in any one tunnel final stage amplifying circuit of circuit extraction through amplifying signal, this contains distorted signal and main signal through amplifying signal, described first error signal is extracted circuit and should be subtracted each other through amplifying signal and described reference signal, and the error signal that obtains after subtracting each other carried out amplitude and phase adjusted respectively, obtain the first error conditioning signal and the second error conditioning signal, and be input to respectively in the other two-way final stage amplifying circuit;
Described first mixer carries out first time error signal to the output signal of two-way final stage amplifying circuit wherein and offsets;
Described second mixer carries out the error signal counteracting second time to the output signal of described first mixer and the output signal of other one tunnel final stage amplifying circuit.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, wherein:
The described first final stage amplifying circuit comprises first power splitter, driving amplifying circuit, second power splitter, first final amplifier, first coupler and first delayer that connects successively; The input of described first power splitter inserts main signal; The output of described first delayer connects an input of described first mixer;
Described reference signal circuit comprises reference signal regulating circuit and subtracter, the input of described reference signal regulating circuit connects an output of first power splitter, and two inputs of described subtracter connect a coupled end of the output and first coupler of described reference signal regulating circuit respectively;
Described error signal is extracted circuit and is comprised the 3rd power splitter, the first error signal regulating circuit and the second error signal regulating circuit, the input of described the 3rd power splitter connects the output of subtracter, the input of the described first error signal regulating circuit connects an output of described the 3rd power splitter, and the output of the described first error signal regulating circuit is exported the second error conditioning signal; The input of the described second error signal regulating circuit connects another output of described the 3rd power splitter, and the output of the described second error signal regulating circuit is exported the first error conditioning signal;
The described second final stage amplifying circuit comprises the 4th power splitter and time-delay of first final stage and amplifying circuit, the input of described the 4th power splitter connects an output of described second power splitter, described first final stage time-delay is connected an output of described the 4th power splitter with an input of amplifying circuit, described first final stage time-delay inserts the described first error conditioning signal with another input of amplifying circuit, and described first final stage time-delay is connected another input of described first mixer with the output of amplifying circuit;
Described the 3rd final stage amplifying circuit comprises time-delay of second final stage and amplifying circuit, described second final stage time-delay is connected another output of described the 4th power splitter with an input of amplifying circuit, described second final stage time-delay inserts the second error conditioning signal with another input of amplifying circuit; Described second final stage time-delay is connected an input of second mixer with the output of amplifying circuit; Another input of described second mixer connects the output of described first mixer.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, wherein:
The described first final stage amplifying circuit comprises first power splitter, driving amplifying circuit, second power splitter, the 4th power splitter, first final amplifier, first coupler and first delayer that connects successively; The input of described first power splitter inserts main signal; The output of described first delayer connects an input of described first mixer;
Described reference signal circuit comprises reference signal regulating circuit and subtracter, the input of described reference signal regulating circuit connects an output of first power splitter, and two inputs of described subtracter connect a coupled end of the output and first coupler of described reference signal regulating circuit respectively;
Described error signal is extracted circuit and is comprised the 3rd power splitter, the first error signal regulating circuit and the second error signal regulating circuit, the input of described the 3rd power splitter connects the output of subtracter, the input of the described first error signal regulating circuit connects an output of described the 3rd power splitter, and the output of the described first error signal regulating circuit is exported the second error conditioning signal; The input of the described second error signal regulating circuit connects another output of described the 3rd power splitter, and the output of the described second error signal regulating circuit is exported the first error conditioning signal;
The described second final stage amplifying circuit comprises time-delay of first final stage and amplifying circuit, described first final stage time-delay is connected an output of described second power splitter with an input of amplifying circuit, described first final stage time-delay inserts the described first error conditioning signal with another input of amplifying circuit, and described first final stage time-delay is connected another input of described first mixer with the output of amplifying circuit;
Described the 3rd final stage amplifying circuit comprises time-delay of second final stage and amplifying circuit, described second final stage time-delay is connected an output of described the 4th power splitter with an input of amplifying circuit, described second final stage time-delay inserts the second error conditioning signal with another input of amplifying circuit; Described second final stage time-delay is connected an input of second mixer with the output of amplifying circuit; Another input of described second mixer connects the output of described first mixer.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, wherein:
The described first final stage amplifying circuit comprises first power splitter, driving amplifying circuit, second power splitter, the 4th power splitter, first final amplifier, first coupler and first delayer that connects successively; The input of described first power splitter inserts main signal; The output of described first delayer connects an input of described second mixer; Another input of described second mixer connects the output of described first mixer;
Described reference signal circuit comprises reference signal regulating circuit and subtracter, the input of described reference signal regulating circuit connects an output of first power splitter, and two inputs of described subtracter connect a coupled end of the output and first coupler of described reference signal regulating circuit respectively;
Described error signal is extracted circuit and is comprised the 3rd power splitter, the first error signal regulating circuit and the second error signal regulating circuit, the input of described the 3rd power splitter connects the output of subtracter, the input of the described first error signal regulating circuit connects an output of described the 3rd power splitter, and the output of the described first error signal regulating circuit is exported the second error conditioning signal; The input of the described second error signal regulating circuit connects another output of described the 3rd power splitter, and the output of the described second error signal regulating circuit is exported the first error conditioning signal;
The described second final stage amplifying circuit comprises time-delay of first final stage and amplifying circuit, described first final stage time-delay is connected an output of described the 4th power splitter with an input of amplifying circuit, described first final stage time-delay inserts the second error conditioning signal with another input of amplifying circuit; Described first final stage time-delay is connected an input of first mixer with the output of amplifying circuit;
Described the 3rd final stage amplifying circuit comprises time-delay of second final stage and amplifying circuit, described second final stage time-delay is connected an output of described second power splitter with an input of amplifying circuit, described second final stage time-delay inserts the described first error conditioning signal with another input of amplifying circuit, and described second final stage time-delay is connected another input of described first mixer with the output of amplifying circuit.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, and the input signal time delay of two inputs of described subtracter equates, and the error signal phase place in the input signal is opposite, and amplitude equates.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, and described first final stage time-delay equates that with the input signal time delay of two inputs of amplifying circuit phase place is identical.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, and described second final stage time-delay equates that with the input signal time delay of two inputs of amplifying circuit phase place is identical.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, and the input signal time delay of two inputs of described first mixer equates, and the error signal phase place in the input signal is opposite, and amplitude does not wait.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, and the input signal time delay of two inputs of described second mixer equates, and the error signal phase place in the input signal is opposite, and amplitude equates.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, and the described first final stage time-delay comprises second delayer, second coupler and second final amplifier that is connected successively with amplifying circuit or the time-delay of described second final stage with amplifying circuit.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, and the described first final stage time-delay comprises the 3rd delayer, the 3rd final amplifier and the 3rd coupler that is connected successively with amplifying circuit or the time-delay of described second final stage with amplifying circuit.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, and described driving amplifier comprises N amplifier tube, and wherein N is a natural number.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, and the 3rd delayer is any in delay line, integrated delayer or the filtering wave by prolonging time device.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit that the road secondary offsets function, and first final amplifier, second final amplifier or the 3rd final amplifier comprise N series connection or amplifier tube in parallel, and wherein N is a natural number.
The beneficial effect that the present invention produces is: the present invention is by any a tunnel extracting through amplifying signal from three tunnel final stage amplifying circuits, and subtract each other with undistorted main signal and to obtain error signal, divide two-way to regulate and be input to respectively in the other two-way final stage amplifying circuit error signal, first mixer carries out the first time to the output signal of two-way final stage amplifying circuit wherein and offsets; Second mixer carries out the counteracting second time to the output signal of described first mixer and the output signal of other one tunnel final stage amplifying circuit.Since can carry out the counteracting of twice error signal, can be more relatively low to the required precision of circuit.All be eliminated through the distorted signal that power amplifier produced after twice counteracting, obtained the favorable linearity effect.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the schematic block circuit diagram of first embodiment of the invention;
Fig. 2 is the schematic block circuit diagram of second embodiment of the invention;
Fig. 3 is the schematic block circuit diagram of third embodiment of the invention;
Fig. 4 is the schematic block circuit diagram one of time-delay of of the present invention first or second final stage and amplifying circuit;
Fig. 5 is the schematic block circuit diagram two of time-delay of of the present invention first or second final stage and amplifying circuit;
Fig. 6 is the theory diagram of reference signal regulating circuit of the present invention;
Fig. 7 is the first error signal regulating circuit of the present invention or the second error signal regulating circuit theory diagram;
Fig. 8 is the structural representation one of first final amplifier in the embodiment of the invention, second final amplifier or the 3rd final amplifier;
Fig. 9 is the structural representation two of first final amplifier in the embodiment of the invention, second final amplifier or the 3rd final amplifier;
Figure 10 is the structural representation three of first final amplifier in the embodiment of the invention, second final amplifier or the 3rd final amplifier.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In order to realize high efficiency and high linear amplification to the radiofrequency signal of mobile communication frequency range, the embodiment of the invention has three the tunnel and closes the high efficiency power amplification circuit that the road secondary offsets function, comprises three tunnel end amplifying circuits, reference signal circuit, error signal extraction circuit, first mixer and second mixer; Three tunnel end amplifying circuits comprise the first final stage amplifying circuit, the second final stage amplifying circuit and the 3rd final stage amplifying circuit;
Undistorted main signal is carried out amplitude to reference signal circuit and phase adjusted obtains reference signal;
Error signal is extracted in any one tunnel final stage amplifying circuit of circuit extraction through amplifying signal, this contains distorted signal and main signal through amplifying signal, first error signal is extracted circuit and should be subtracted each other through amplifying signal and reference signal, and the error signal that obtains after subtracting each other carried out amplitude and phase adjusted respectively, obtain the first error conditioning signal and the second error conditioning signal, and be input to respectively in the other two-way final stage amplifying circuit;
First mixer carries out first time error signal to the output signal of two-way final stage amplifying circuit wherein and offsets;
Second mixer carries out the error signal counteracting second time to the output signal of first mixer and the output signal of other one tunnel final stage amplifying circuit.
The first embodiment of the present invention as shown in Figure 1, the first final stage amplifying circuit comprises successively first power splitter 1 that connects, drives amplifying circuit 2, second power splitter 4, first final amplifier 5, first coupler 6 and first delayer 7; The input of first power splitter 1 inserts main signal; The output of first delayer 7 connects an input of first mixer 15.Be specially: main signal is imported from first power splitter, 1 input A1, output to the input A3 of driving amplifier 2 from first output terminals A 2 of first power splitter 1, the signal of 2 pairs of inputs of driving amplifier amplifies, then output to the input A5 of second power splitter 4 from the output terminals A 4 of driving amplifier 2, output to the input B2 of first final amplifier 5 from the second output B1 of second power splitter 4,5 pairs of signals of first final amplifier amplify, can produce distorted signal simultaneously, signal that is exaggerated and distorted signal output to the input B4 of first coupler 6 from the output B3 of first final amplifier 5, output to the second input D2 of subtracter 8 then from the coupled end D1 of first coupler 6.The output B5 output signal of first coupler 6 is to the input B6 of first delayer 7, and the output B7 of first delayer 7 outputs signal to the first input end B8 of first mixer 15.
Reference signal circuit comprises reference signal regulating circuit 3 and subtracter 8, the input C2 of reference signal regulating circuit 3 connects the second output C1 of first power splitter 1, an input C4 of subtracter 8 connects the output C3 of reference signal regulating circuit 3, and another input D2 of subtracter 8 connects the coupled end D1 of first coupler 6;
Error signal is extracted circuit and is comprised the 3rd power splitter 9, the first error signal regulating circuit 10 and the second error signal regulating circuit 11, the input E2 of the 3rd power splitter 9 connects the output E1 of subtracter 8, the input E4 of the first error signal regulating circuit 10 connects an output E3 of the 3rd power splitter 9, and the output E5 of the first error signal regulating circuit 10 exports the second error conditioning signal; The input F2 of the second error signal regulating circuit 11 connects another output F1 of the 3rd power splitter 9, and the output F3 of the second error signal regulating circuit 11 exports the first error conditioning signal;
The second final stage amplifying circuit comprises the 4th power splitter 12 and time-delay of first final stage and amplifying circuit 13, the input A7 of the 4th power splitter 12 connects an output terminals A 6 of second power splitter 4, the time-delay of first final stage is connected an output G1 of the 4th power splitter 12 with an input G2 of amplifying circuit 13, the time-delay of first final stage inserts the first error conditioning signal with another input of amplifying circuit 13, promptly connects the output F3 of the second error signal regulating circuit 11.The time-delay of first final stage is connected another input G4 of first mixer 15 with the output G3 of amplifying circuit 13; First final stage time-delay is delayed time with 13 pairs of signals of amplifying circuit, the injection of amplification and error signal, can produce distorted signal simultaneously.
The 3rd final stage amplifying circuit comprises time-delay of second final stage and amplifying circuit 14, the time-delay of second final stage is connected another output H1 of the 4th power splitter 12 with an input H2 of amplifying circuit 14, the time-delay of second final stage inserts the second error conditioning signal with another input of amplifying circuit 14, promptly connects the output E5 of the first error signal regulating circuit 10; The time-delay of second final stage is connected an input H4 of second mixer 16 with the output H3 of amplifying circuit 14; Another input G6 of second mixer 16 connects the output G5 of first mixer 15.Second final stage time-delay is delayed time with 14 pairs of signals of amplifying circuit, the injection of amplification and error signal, can produce distorted signal simultaneously.
The second embodiment of the present invention, as shown in Figure 2, the first final stage amplifying circuit comprises first power splitter 1, driving amplifying circuit 2, second power splitter 4, the 4th power splitter 12, first final amplifier 5, first coupler 6 and first delayer 7 that connects successively; The input of first power splitter 1 inserts main signal; The output of first delayer 7 connects an input of first mixer 15; Be specially: main signal is imported from first power splitter, 1 input A1, output to the input A3 of driving amplifier 2 from first output terminals A 2 of first power splitter 1, the signal of 2 pairs of inputs of driving amplifier amplifies, then output to the input A5 of second power splitter 4 from the output terminals A 4 of driving amplifier 2, output to the input A7 of the 4th power splitter 12 from the second output G1 of second power splitter 4, the output B1 of the 4th power splitter 12 connects the input B2 of first final amplifier 5,5 pairs of signals of first final amplifier amplify, can produce distorted signal simultaneously, signal that is exaggerated and distorted signal output to the input B4 of first coupler 6 from the output B3 of first final amplifier 5, output to the second input D2 of subtracter 8 then from the coupled end D1 of first coupler 6.The output B5 output signal of first coupler 6 is to the input B6 of first delayer 7, and the output B7 of first delayer 7 outputs signal to the first input end B8 of first mixer 15.
Reference signal circuit comprises reference signal regulating circuit 3 and subtracter 8, the input C2 of reference signal regulating circuit 3 connects an output C1 of first power splitter 1, an input C4 of subtracter 8 connects the output C3 of reference signal regulating circuit 3, and another input D2 of subtracter 8 connects a coupled end D1 of first coupler 6;
Error signal is extracted circuit and is comprised the 3rd power splitter 9, the first error signal regulating circuit 10 and the second error signal regulating circuit 11, the input E2 of the 3rd power splitter 9 connects the output E1 of subtracter 8, the input E4 of the first error signal regulating circuit 10 connects an output E3 of the 3rd power splitter 9, the output E5 of the first error signal regulating circuit 10 exports the second error conditioning signal, and output E5 is connected with the input E6 of amplifying circuit 14 with the time-delay of second final stage; The input F2 of the second error signal regulating circuit 11 connects another output F1 of the 3rd power splitter 9, the output F3 of the second error signal regulating circuit 11 exports the first error conditioning signal, and output F3 is connected with the input F4 of amplifying circuit 13 with the time-delay of first final stage;
The second final stage amplifying circuit comprises time-delay of first final stage and amplifying circuit 13, the time-delay of first final stage is connected an output G1 of second power splitter 4 with an input G2 of amplifying circuit 13, the time-delay of first final stage inserts the first error conditioning signal with another input F4 of amplifying circuit 13, and the time-delay of first final stage is connected another input G4 of first mixer 15 with the output G3 of amplifying circuit 13;
The 3rd final stage amplifying circuit comprises time-delay of second final stage and amplifying circuit 14, the time-delay of second final stage is connected an output H1 of the 4th power splitter 12 with an input H2 of amplifying circuit 14, the time-delay of second final stage inserts the second error conditioning signal with another input E6 of amplifying circuit 14; The time-delay of second final stage is connected an input H4 of second mixer 16 with the output H3 of amplifying circuit 14; Another input G6 of second mixer 16 connects the output G5 of first mixer 15.
Third embodiment of the invention as shown in Figure 3, the first final stage amplifying circuit comprises successively first power splitter 1 that connects, drives amplifying circuit 2, second power splitter 4, the 4th power splitter 12, first final amplifier 5, first coupler 6 and first delayer 7; The input of first power splitter 1 inserts main signal; The output of first delayer 7 connects an input of second mixer 16; Another input of second mixer 16 connects the output of first mixer 15; The first final stage amplifying circuit comprises first power splitter 1, driving amplifying circuit 2, second power splitter 4, the 4th power splitter 12, first final amplifier 5, first coupler 6 and first delayer 7 that connects successively; The input of first power splitter 1 inserts main signal; Be specially: main signal is imported from first power splitter, 1 input A1, output to the input A3 of driving amplifier 2 from first output terminals A 2 of first power splitter 1, the signal of 2 pairs of inputs of driving amplifier amplifies, then output to the input A5 of second power splitter 4 from the output terminals A 4 of driving amplifier 2, output to the input A7 of the 4th power splitter 12 from the output terminals A 6 of second power splitter 4, the output B1 of the 4th power splitter 12 connects the input B2 of first final amplifier 5,5 pairs of signals of first final amplifier amplify, can produce distorted signal simultaneously, signal that is exaggerated and distorted signal output to the input B4 of first coupler 6 from the output B3 of first final amplifier 5, output to the second input D2 of subtracter 8 then from the coupled end D1 of first coupler 6.The output B5 output signal of first coupler 6 is to the input B6 of first delayer 7, and the output B7 of first delayer 7 outputs signal to the first input end B8 of second mixer 16.
Reference signal circuit comprises reference signal regulating circuit 3 and subtracter 8, the input C2 of reference signal regulating circuit 3 connects an output C1 of first power splitter 1, an input C4 of subtracter 8 connects the output C3 of reference signal regulating circuit 3, and another input D2 of subtracter 8 connects a coupled end D1 of first coupler 6;
Error signal is extracted circuit and is comprised the 3rd power splitter 9, the first error signal regulating circuit 10 and the second error signal regulating circuit 11, the input E2 of the 3rd power splitter 9 connects the output E1 of subtracter 8, the input E4 of the first error signal regulating circuit 10 connects an output E3 of the 3rd power splitter 9, the output E5 of the first error signal regulating circuit 10 exports the second error conditioning signal, is connected with an input E6 of amplifying circuit 13 with the time-delay of first final stage; The input F2 of the second error signal regulating circuit 11 connects another output F1 of the 3rd power splitter 9, the output F3 of the second error signal regulating circuit 11 exports the first error conditioning signal, is connected with an input F4 of amplifying circuit 14 with the time-delay of second final stage;
The second final stage amplifying circuit comprises time-delay of first final stage and amplifying circuit 13, the time-delay of first final stage is connected an output G1 of the 4th power splitter 12 with an input G2 of amplifying circuit 13, the time-delay of first final stage inserts the second error conditioning signal with another input E6 of amplifying circuit 13; The time-delay of first final stage is connected an input G4 of first mixer 15 with the output G3 of amplifying circuit 13;
The 3rd final stage amplifying circuit comprises time-delay of second final stage and amplifying circuit 14, the time-delay of second final stage is connected an output H1 of second power splitter 4 with an input H2 of amplifying circuit 14, the time-delay of second final stage inserts the first error conditioning signal with another input F4 of amplifying circuit 14, and the time-delay of second final stage is connected another input H4 of first mixer 15 with the output H3 of amplifying circuit 14.
The input signal time delay of 8 two inputs of subtracter equates, and the error signal phase place in the input signal is opposite, and amplitude equates.
Further, in the above-described embodiments, the time-delay of first final stage equates that with the input signal time delay of two inputs of amplifying circuit 13 phase place is identical.
Further, in the above-described embodiments, the time-delay of second final stage equates that with the input signal time delay of two inputs of amplifying circuit 14 phase place is identical.
Further, in the above-described embodiments, the input signal time delay of two inputs of first mixer 15 equates, and the error signal phase place in the input signal is opposite, amplitude does not wait, the amplitude of the error signal of first final amplifier, 5 outputs is bigger, and offset the first time that is implemented in first mixer, 15 place's error signals.
Further, in the above-described embodiments, the input signal time delay of two inputs of second mixer 16 equates, and the error signal phase place in the input signal is opposite, and amplitude equates, realizes that finally offset the second time of error signal.
Further, in the above-described embodiments, as shown in Figure 4, the time-delay of first final stage comprises second delayer 17, second coupler 19 and second final amplifier 18 that is connected successively with amplifying circuit 13 or the time-delay of second final stage with amplifying circuit 14.Promptly the output of second delayer 17 connects the input of second coupler 19, and the output of second coupler 19 connects the input of second final amplifier 18.
Further, in the above-described embodiments, as shown in Figure 5, the time-delay of first final stage comprises the 3rd delayer 20, the 3rd final amplifier 21 and the 3rd coupler 22 that is connected successively with amplifying circuit 13 or the time-delay of second final stage with amplifying circuit 14, promptly the output of the 3rd delayer 20 connects the input of the 3rd final amplifier 21, the input of output the 3rd coupler 22 of the 3rd final amplifier 21.
Further, error signal is extracted also can extracting through amplifying signal of circuit extraction in the foregoing description from second final amplifier 18 or the 3rd final amplifier 21.
Further, driving amplifier 2 comprises N amplifier tube in the foregoing description, and wherein N is a natural number.
Further, first delayer 7, second delayer 17 and the 3rd delayer 20 are any in delay line, integrated delayer or the filtering wave by prolonging time device in the foregoing description.
Further, first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21 comprise N series connection or amplifier tube in parallel in the foregoing description, and wherein N is a natural number.
Be illustrated in figure 6 as the theory diagram of the reference signal regulating circuit 3 among the present invention, the reference signal regulating circuit comprises first amplitude modulator 23, first phase modulator 24, the 4th delay line 25 and first prime amplifier 26.
The input that is input to first amplitude modulator 23 from the main signal of the output C1 of first power splitter 1 output carries out amplitude modulation, the output of first amplitude modulator 23 is connected to the input of first phase modulator 24, the signal of 24 pairs of inputs of first phase modulator carries out phase modulation, the output of first phase modulator 24 is connected to the input of the 4th delay line 25, the signal of 25 pairs of inputs of the 3rd delay line carries out time delay, the output of the 3rd delay line 25 is connected to the input of first prime amplifier 26, the signal of 26 pairs of inputs of first prime amplifier amplifies, and exports the signal that is exaggerated by output.
Be illustrated in figure 7 as the first error signal regulating circuit 10 among the present invention and the theory diagram of the second error signal regulating circuit 11, comprise second amplitude modulator 27, second phase modulator 28 and second prime amplifier 29.
Be input to the input of second amplitude modulator 27 through the error signal of the 3rd power splitter 9 outputs, 27 pairs of error signals of second amplitude modulator are carried out amplitude modulation, the output of second amplitude modulator 27 is connected to the input of second phase modulator 28, the signal of 28 pairs of inputs of second phase modulator carries out phase modulation, the output of second phase modulator 28 is connected to the input of second prime amplifier 29, the signal of 29 pairs of inputs of second prime amplifier amplifies, the output output error conditioning signal of second prime amplifier 29.
Shown in Fig. 8,9,10, be the structural representation of three kinds of embodiment of first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21.Among Fig. 8, first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21 comprise amplifier 23 and amplifier 24 in parallel, and an end of its parallel connection connects power splitter 28, and the other end connects mixer 31; Among Fig. 9, first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21 comprise amplifier 33, amplifier 34 and amplifier 35 in parallel, and an end of its parallel connection connects power splitter 32, and the other end connects mixer 36; Among Figure 10, first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21 comprise amplifier 38, amplifier 39, amplifier 40 and amplifier 41 in parallel, and an end of its parallel connection connects power splitter 37, and the other end connects mixer 42.
In implementation process of the present invention, it is to be made of single or a plurality of amplifier tubes series connection that driving amplifier 2 can be selected according to the gain needs of the power amplifier complete machine of reality, in like manner first final amplifier 5, second final amplifier 18 or the 3rd final amplifier 21 can be that independently single amplifier tube constitutes, also can be to close the road by N amplifier tube to constitute, wherein N is more than or equal to 2, concrete enforcement will be according to the demanded power output of Feed Forward Power Amplifier, and the type selecting of final stage amplifier tube and deciding.Because driving amplifier 2 itself has enough rollbacks and all is operated in category-A, therefore linear distortion can be ignored substantially, other first final amplifier 5, amplifier in the first final stage delay amplification circuit 13 and the second final stage delay amplification circuit 14 also is to be operated in category-A or AB class when designing, therefore the linear distortion of amplifier generation itself is also less relatively, the first final stage amplifying circuit can be operated in different states as required, can be that the AB class also can be the C class, the amplifier that is operated in C time-like and the first final stage delay amplification circuit 13 and the second final stage delay amplification circuit 14 when first final amplifier constitutes a Doherty amplifying circuit.In the implementation process of this programme, the first final stage delay amplification circuit 13 and the second final stage delay amplification circuit 14 are used as the error amplifier use, owing to there is not special error amplifier, therefore with respect to traditional Feed Forward Power Amplifier, both saved hardware cost, simultaneously reduce power consumption again, made the efficient of power amplifier product effectively improve.The efficient that works in complete machine power amplifier under the condition of C class A amplifier A at first final amplifier 5 can reach between the 40-50% according to the difference of signal peak-to-average ratio.
Should be understood that, for those of ordinary skills, can be improved according to the above description or conversion, and all these improvement and conversion all should belong to the protection range of claims of the present invention.
Claims (14)
1. one kind has three the tunnel and closes the high efficiency power amplification circuit that the road secondary offsets function, it is characterized in that, comprises that three tunnel end amplifying circuits, reference signal circuit, error signal extract circuit, first mixer (15) and second mixer (16); Described three tunnel end amplifying circuits comprise the first final stage amplifying circuit, the second final stage amplifying circuit and the 3rd final stage amplifying circuit;
Undistorted main signal is carried out amplitude to described reference signal circuit and phase adjusted obtains reference signal;
Described error signal is extracted in any one tunnel final stage amplifying circuit of circuit extraction through amplifying signal, this contains distorted signal and main signal through amplifying signal, described first error signal is extracted circuit and should be subtracted each other through amplifying signal and described reference signal, and the error signal that obtains after subtracting each other carried out amplitude and phase adjusted respectively, obtain the first error conditioning signal and the second error conditioning signal, and be input to respectively in the other two-way final stage amplifying circuit;
Described first mixer carries out first time error signal to the output signal of two-way final stage amplifying circuit wherein and offsets;
Described second mixer carries out the error signal counteracting second time to the output signal of described first mixer and the output signal of other one tunnel final stage amplifying circuit.
2. according to claim 1 have three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function, it is characterized in that, wherein:
The described first final stage amplifying circuit comprises first power splitter (1), driving amplifying circuit (2), second power splitter (4), first final amplifier (5), first coupler (6) and first delayer (7) that connects successively; The input of described first power splitter (1) inserts main signal; The output of described first delayer (7) connects an input of described first mixer (15);
Described reference signal circuit comprises reference signal regulating circuit (3) and subtracter (8), the input of described reference signal regulating circuit (3) connects an output of first power splitter (1), and two inputs of described subtracter (8) connect a coupled end of the output and first coupler (6) of described reference signal regulating circuit (3) respectively;
Described error signal is extracted circuit and is comprised the 3rd power splitter (9), the first error signal regulating circuit (10) and the second error signal regulating circuit (11), the input of described the 3rd power splitter (9) connects the output of subtracter (8), the input of the described first error signal regulating circuit (10) connects an output of described the 3rd power splitter (9), and the output of the described first error signal regulating circuit (10) is exported the second error conditioning signal; The input of the described second error signal regulating circuit (11) connects another output of described the 3rd power splitter (9), and the output of the described second error signal regulating circuit (11) is exported the first error conditioning signal;
The described second final stage amplifying circuit comprises the 4th power splitter (12) and time-delay of first final stage and amplifying circuit (13), the input of described the 4th power splitter (12) connects an output of described second power splitter (4), described first final stage time-delay is connected an output of described the 4th power splitter (12) with an input of amplifying circuit (13), described first final stage time-delay inserts the described first error conditioning signal with another input of amplifying circuit (13), and described first final stage time-delay is connected another input of described first mixer (15) with the output of amplifying circuit (13);
Described the 3rd final stage amplifying circuit comprises time-delay of second final stage and amplifying circuit (14), described second final stage time-delay is connected another output of described the 4th power splitter (12) with an input of amplifying circuit (14), described second final stage time-delay inserts the second error conditioning signal with another input of amplifying circuit (14); Described second final stage time-delay is connected an input of second mixer (16) with the output of amplifying circuit (14); Another input of described second mixer (16) connects the output of described first mixer (15).
3. according to claim 1 have three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function, it is characterized in that, wherein:
The described first final stage amplifying circuit comprises first power splitter (1), driving amplifying circuit (2), second power splitter (4), the 4th power splitter (12), first final amplifier (5), first coupler (6) and first delayer (7) that connects successively; The input of described first power splitter (1) inserts main signal; The output of described first delayer (7) connects an input of described first mixer (15);
Described reference signal circuit comprises reference signal regulating circuit (3) and subtracter (8), the input of described reference signal regulating circuit (3) connects an output of first power splitter (1), and two inputs of described subtracter (8) connect a coupled end of the output and first coupler (6) of described reference signal regulating circuit (3) respectively;
Described error signal is extracted circuit and is comprised the 3rd power splitter (9), the first error signal regulating circuit (10) and the second error signal regulating circuit (11), the input of described the 3rd power splitter (9) connects the output of subtracter (8), the input of the described first error signal regulating circuit (10) connects an output of described the 3rd power splitter (9), and the output of the described first error signal regulating circuit (10) is exported the second error conditioning signal; The input of the described second error signal regulating circuit (11) connects another output of described the 3rd power splitter (9), and the output of the described second error signal regulating circuit (11) is exported the first error conditioning signal;
The described second final stage amplifying circuit comprises time-delay of first final stage and amplifying circuit (13), described first final stage time-delay is connected an output of described second power splitter (4) with an input of amplifying circuit (13), described first final stage time-delay inserts the described first error conditioning signal with another input of amplifying circuit (13), and described first final stage time-delay is connected another input of described first mixer (15) with the output of amplifying circuit (13);
Described the 3rd final stage amplifying circuit comprises time-delay of second final stage and amplifying circuit (14), described second final stage time-delay is connected an output of described the 4th power splitter (12) with an input of amplifying circuit (14), described second final stage time-delay inserts the second error conditioning signal with another input of amplifying circuit (14); Described second final stage time-delay is connected an input of second mixer (16) with the output of amplifying circuit (14); Another input of described second mixer (16) connects the output of described first mixer (15).
4. according to claim 1 have three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function, it is characterized in that, wherein:
The described first final stage amplifying circuit comprises first power splitter (1), driving amplifying circuit (2), second power splitter (4), the 4th power splitter (12), first final amplifier (5), first coupler (6) and first delayer (7) that connects successively; The input of described first power splitter (1) inserts main signal; The output of described first delayer (7) connects an input of described second mixer (16); Another input of described second mixer (16) connects the output of described first mixer (15);
Described reference signal circuit comprises reference signal regulating circuit (3) and subtracter (8), the input of described reference signal regulating circuit (3) connects an output of first power splitter (1), and two inputs of described subtracter (8) connect a coupled end of the output and first coupler (6) of described reference signal regulating circuit (3) respectively;
Described error signal is extracted circuit and is comprised the 3rd power splitter (9), the first error signal regulating circuit (10) and the second error signal regulating circuit (11), the input of described the 3rd power splitter (9) connects the output of subtracter (8), the input of the described first error signal regulating circuit (10) connects an output of described the 3rd power splitter (9), and the output of the described first error signal regulating circuit (10) is exported the second error conditioning signal; The input of the described second error signal regulating circuit (11) connects another output of described the 3rd power splitter (9), and the output of the described second error signal regulating circuit (11) is exported the first error conditioning signal;
The described second final stage amplifying circuit comprises time-delay of first final stage and amplifying circuit (13), described first final stage time-delay is connected an output of described the 4th power splitter (12) with an input of amplifying circuit (13), described first final stage time-delay inserts the second error conditioning signal with another input of amplifying circuit (13); Described first final stage time-delay is connected an input of first mixer (15) with the output of amplifying circuit (13);
Described the 3rd final stage amplifying circuit comprises time-delay of second final stage and amplifying circuit (14), described second final stage time-delay is connected an output of described second power splitter (4) with an input of amplifying circuit (14), described second final stage time-delay inserts the described first error conditioning signal with another input of amplifying circuit (14), and described second final stage time-delay is connected another input of described first mixer (15) with the output of amplifying circuit (14).
5. according to each describedly has three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function among the claim 2-4, it is characterized in that, the input signal time delay of (8) two inputs of described subtracter equates, and the error signal phase place in the input signal is opposite, and amplitude equates.
6. according to each describedly has three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function among the claim 2-4, it is characterized in that, described first final stage time-delay equates that with the input signal time delay of two inputs of amplifying circuit (13) phase place is identical.
7. according to each describedly has three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function among the claim 2-4, it is characterized in that, described second final stage time-delay equates that with the input signal time delay of two inputs of amplifying circuit (14) phase place is identical.
8. according to each describedly has three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function among the claim 2-4, it is characterized in that, the input signal time delay of two inputs of described first mixer (15) equates, and the error signal phase place in the input signal is opposite, and amplitude does not wait.
9. according to each describedly has three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function among the claim 2-4, it is characterized in that, the input signal time delay of two inputs of described second mixer (16) equates, and the error signal phase place in the input signal is opposite, and amplitude equates.
10. according to each describedly has three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function among the claim 2-4, it is characterized in that described first final stage time-delay comprises second delayer (17), second coupler (19) and second final amplifier (18) that is connected successively with amplifying circuit (13) or the time-delay of described second final stage with amplifying circuit (14).
11. according to each describedly has three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function among the claim 2-4, it is characterized in that described first final stage time-delay comprises the 3rd delayer (20), the 3rd final amplifier (21) and the 3rd coupler (22) that is connected successively with amplifying circuit (13) or the time-delay of described second final stage with amplifying circuit (14).
12. according to each describedly has three the tunnel and close the high efficiency power amplification circuit that the road secondary offsets function among the claim 2-4, it is characterized in that described driving amplifier (2) comprises N amplifier tube, wherein N is a natural number.
13. three the tunnel close the high efficiency power amplification circuit that the road secondary offsets function, it is characterized in that the 3rd delayer (20) is any in delay line, integrated delayer or the filtering wave by prolonging time device according to having described in the claim 11.
14. three the tunnel close the high efficiency power amplification circuit that the road secondary offsets function according to having described in the claim 12, it is characterized in that, first final amplifier (5) or the 3rd final amplifier (21) comprise N series connection or amplifier tube in parallel, and wherein N is a natural number.
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| CN201310081299.3A CN103219950B (en) | 2013-03-14 | 2013-03-14 | There is the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions |
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| CN201310081299.3A CN103219950B (en) | 2013-03-14 | 2013-03-14 | There is the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions |
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| CN103219950B CN103219950B (en) | 2016-04-27 |
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| US5877653A (en) * | 1995-11-16 | 1999-03-02 | Samsung Electronics Co., Ltd. | Linear power amplifier and method for removing intermodulation distortion with predistortion system and feed forward system |
| CN1321356A (en) * | 1999-09-01 | 2001-11-07 | 三菱电机株式会社 | Feedforward amplifier |
| CN203278753U (en) * | 2013-03-14 | 2013-11-06 | 武汉正维电子技术有限公司 | Efficient amplifier with three-circuit combining and twice offsetting functions |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1098572A (en) * | 1993-04-19 | 1995-02-08 | 美国电话电报公司 | Low-distortion feed-forward amplifier |
| US5877653A (en) * | 1995-11-16 | 1999-03-02 | Samsung Electronics Co., Ltd. | Linear power amplifier and method for removing intermodulation distortion with predistortion system and feed forward system |
| CN1321356A (en) * | 1999-09-01 | 2001-11-07 | 三菱电机株式会社 | Feedforward amplifier |
| CN203278753U (en) * | 2013-03-14 | 2013-11-06 | 武汉正维电子技术有限公司 | Efficient amplifier with three-circuit combining and twice offsetting functions |
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