CN203278753U - Efficient amplifier with three-circuit combining and twice offsetting functions - Google Patents
Efficient amplifier with three-circuit combining and twice offsetting functions Download PDFInfo
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- CN203278753U CN203278753U CN201320115968XU CN201320115968U CN203278753U CN 203278753 U CN203278753 U CN 203278753U CN 201320115968X U CN201320115968X U CN 201320115968XU CN 201320115968 U CN201320115968 U CN 201320115968U CN 203278753 U CN203278753 U CN 203278753U
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Abstract
The utility model discloses an efficient amplifier with three-circuit combining and twice offsetting functions. The efficient amplifier comprises three final stage amplifying circuits, a reference signal circuit, an error signal extracting circuit, a first combiner and a second combiner, wherein the three final stage amplifying circuits include a first final stage amplifying circuit, a second final stage amplifying circuit and a third final stage amplifying circuit. According to the efficient amplifier disclosed by the utility model, amplified signals are extracted from any one final stage amplifying circuit in the three final stage amplifying circuits and are subtracted with an undistorted main signal to obtain error signals, the error signals are adjusted in two paths and are respectively input into the other two final stage amplifying circuits, and first offsetting is carried out on the output signals of two final stage amplifying circuits by the first combiner; and second offsetting is carried out on the output signals of the first combiner and another final stage amplifying circuit by the second combiner. After two times of offsetting, distorted signals generated by the power amplifier are all eliminated, and a good linear effect is obtained.
Description
Technical field
The present invention relates to power amplification circuit, relate in particular to and a kind ofly have three the tunnel and close the high efficiency power amplification circuit of road cancellation function.
Background technology
The Contemporary Digital pre-distortion technology is widely used at wireless communication base station system, feed forward power amplifier still is used in some application scenario, yet the shortcoming of traditional Feed Forward Power Amplifier based on main amplifier and error amplifier is, because error amplifier itself does not have contribution to the power output of power amplifier, and error amplifier itself has power consumption, therefore cause the efficient of conventional feed forward power amplifier lower, even adopted the Doherty technical efficiency also can only reach 22% left and right.Therefore can work out a kind of high efficiency, simultaneously but also can need not extra circuit and realize that linearisation is when the previous further problem of further investigation that is worth of not only having had.
Summary of the invention
The object of the present invention is to provide a kind ofly to have three the tunnel and close the high efficiency power amplifier of road cancellation function, this amplifier can be realized the high efficiency of the radiofrequency signal of mobile communication frequency range and high linear the amplification.
The technical solution adopted for the present invention to solve the technical problems is:
Provide a kind of and have three the tunnel and close the high efficiency power amplification circuit of road cancellation function, comprise three tunnel end amplifying circuits, reference signal circuit, error signal extraction circuit, the first mixer and the second mixer; Described three tunnel end amplifying circuits comprise the first final stage amplifying circuit, the second final stage amplifying circuit and the 3rd final stage amplifying circuit;
Undistorted main signal is carried out amplitude to described reference signal circuit and phase adjusted obtains reference signal;
In any one tunnel final stage amplifying circuit of described error signal extraction circuit extraction through amplifying signal, this contains distorted signal and main signal through amplifying signal, described error signal extraction circuit should subtract each other through amplifying signal and described reference signal again, and the error signal that obtains after subtracting each other is carried out respectively amplitude and phase adjusted, obtain the first regulating error signal and the second regulating error signal, and be input to respectively in other two-way final stage amplifying circuit;
Described the first mixer carries out for the first time error signal to the output signal of two-way final stage amplifying circuit wherein and offsets;
Described the second mixer carries out error signal counteracting for the second time to the output signal of described the first mixer and the output signal of other one tunnel final stage amplifying circuit.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, wherein:
Described the first final stage amplifying circuit comprises the first power splitter, drive amplification circuit, the second power splitter, the first final amplifier, the first coupler and the first delayer that connects successively; The input access main signal of described the first power splitter; The output of described the first delayer connects an input of described the first mixer;
Described reference signal circuit comprises reference signal regulating circuit and subtracter, the input of described reference signal regulating circuit connects an output of the first power splitter, and two inputs of described subtracter connect respectively a coupled end of output and first coupler of described reference signal regulating circuit;
Described error signal extraction circuit comprises the 3rd power splitter, the first error signal regulating circuit and the second error signal regulating circuit, the input of described the 3rd power splitter connects the output of subtracter, the input of described the first error signal regulating circuit connects an output of described the 3rd power splitter, the output output second regulating error signal of described the first error signal regulating circuit; The input of described the second error signal regulating circuit connects another output of described the 3rd power splitter, the output output first regulating error signal of described the second error signal regulating circuit;
Described the second final stage amplifying circuit comprises the 4th power splitter and the time-delay of the first final stage and amplifying circuit, the input of described the 4th power splitter connects an output of described the second power splitter, described the first final stage time-delay is connected an output of described the 4th power splitter with an input of amplifying circuit, described the first final stage time-delay accesses described the first regulating error signal with another input of amplifying circuit, and described the first final stage time-delay is connected another input of described the first mixer with the output of amplifying circuit;
Described the 3rd final stage amplifying circuit comprises the second final stage time-delay and amplifying circuit, described the second final stage time-delay is connected another output of described the 4th power splitter with an input of amplifying circuit, described the second final stage time-delay accesses second regulating error signal with another input of amplifying circuit; Described the second final stage time-delay is connected an input of the second mixer with the output of amplifying circuit; Another input of described the second mixer connects the output of described the first mixer.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, wherein:
Described the first final stage amplifying circuit comprises the first power splitter, drive amplification circuit, the second power splitter, the 4th power splitter, the first final amplifier, the first coupler and the first delayer that connects successively; The input access main signal of described the first power splitter; The output of described the first delayer connects an input of described the first mixer;
Described reference signal circuit comprises reference signal regulating circuit and subtracter, the input of described reference signal regulating circuit connects an output of the first power splitter, and two inputs of described subtracter connect respectively a coupled end of output and first coupler of described reference signal regulating circuit;
Described error signal extraction circuit comprises the 3rd power splitter, the first error signal regulating circuit and the second error signal regulating circuit, the input of described the 3rd power splitter connects the output of subtracter, the input of described the first error signal regulating circuit connects an output of described the 3rd power splitter, the output output second regulating error signal of described the first error signal regulating circuit; The input of described the second error signal regulating circuit connects another output of described the 3rd power splitter, the output output first regulating error signal of described the second error signal regulating circuit;
Described the second final stage amplifying circuit comprises the first final stage time-delay and amplifying circuit, described the first final stage time-delay is connected an output of described the second power splitter with an input of amplifying circuit, described the first final stage time-delay accesses described the first regulating error signal with another input of amplifying circuit, and described the first final stage time-delay is connected another input of described the first mixer with the output of amplifying circuit;
Described the 3rd final stage amplifying circuit comprises the second final stage time-delay and amplifying circuit, described the second final stage time-delay is connected an output of described the 4th power splitter with an input of amplifying circuit, described the second final stage time-delay accesses second regulating error signal with another input of amplifying circuit; Described the second final stage time-delay is connected an input of the second mixer with the output of amplifying circuit; Another input of described the second mixer connects the output of described the first mixer.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, wherein:
Described the first final stage amplifying circuit comprises the first power splitter, drive amplification circuit, the second power splitter, the 4th power splitter, the first final amplifier, the first coupler and the first delayer that connects successively; The input access main signal of described the first power splitter; The output of described the first delayer connects an input of described the second mixer; Another input of described the second mixer connects the output of described the first mixer;
Described reference signal circuit comprises reference signal regulating circuit and subtracter, the input of described reference signal regulating circuit connects an output of the first power splitter, and two inputs of described subtracter connect respectively a coupled end of output and first coupler of described reference signal regulating circuit;
Described error signal extraction circuit comprises the 3rd power splitter, the first error signal regulating circuit and the second error signal regulating circuit, the input of described the 3rd power splitter connects the output of subtracter, the input of described the first error signal regulating circuit connects an output of described the 3rd power splitter, the output output second regulating error signal of described the first error signal regulating circuit; The input of described the second error signal regulating circuit connects another output of described the 3rd power splitter, the output output first regulating error signal of described the second error signal regulating circuit;
Described the second final stage amplifying circuit comprises the first final stage time-delay and amplifying circuit, described the first final stage time-delay is connected an output of described the 4th power splitter with an input of amplifying circuit, described the first final stage time-delay accesses second regulating error signal with another input of amplifying circuit; Described the first final stage time-delay is connected an input of the first mixer with the output of amplifying circuit;
Described the 3rd final stage amplifying circuit comprises the second final stage time-delay and amplifying circuit, described the second final stage time-delay is connected an output of described the second power splitter with an input of amplifying circuit, described the second final stage time-delay accesses described the first regulating error signal with another input of amplifying circuit, and described the second final stage time-delay is connected another input of described the first mixer with the output of amplifying circuit.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, and the input signal time delay of two inputs of described subtracter equates, and the error signal single spin-echo in input signal, and amplitude equates.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, and described the first final stage time-delay equates with the input signal time delay of two inputs of amplifying circuit, and phase place is identical.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, and described the second final stage time-delay equates with the input signal time delay of two inputs of amplifying circuit, and phase place is identical.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, and the input signal time delay of two inputs of described the first mixer equates, and the error signal single spin-echo in input signal, and amplitude does not wait.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, and the input signal time delay of two inputs of described the second mixer equates, and the error signal single spin-echo in input signal, and amplitude equates.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, and described the first final stage time-delay comprises with amplifying circuit the second delayer, the second coupler and the second final amplifier that is connected successively with amplifying circuit or described the second final stage time-delay.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, and described the first final stage time-delay comprises with amplifying circuit the 3rd delayer, the 3rd final amplifier and the 3rd coupler that is connected successively with amplifying circuit or described the second final stage time-delay.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, and described driving amplifier comprises N amplifier tube, and wherein N is natural number.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, and the 3rd delayer is any in delay line, integrated delayer or filtering wave by prolonging time device.
Of the present invention have three the tunnel and close in the high efficiency power amplification circuit of road cancellation function, and the first final amplifier, the second final amplifier or the 3rd final amplifier comprise N series connection or amplifier tube in parallel, and wherein N is natural number.
The beneficial effect that the present invention produces is: the present invention is by any a tunnel extracting through amplifying signal from three tunnel final stage amplifying circuits, and subtract each other with undistorted main signal and obtain error signal, divide two-way to regulate and be input to respectively in other two-way final stage amplifying circuit error signal, the first mixer is offset for the first time to the output signal of two-way final stage amplifying circuit wherein; The second mixer is offset for the second time to the output signal of described the first mixer and the output signal of other one tunnel final stage amplifying circuit.Owing to can carrying out the counteracting of twice error signal, can be more relatively low to the required precision of circuit.The distorted signal that produces through power amplifier after twice counteracting all is eliminated, and has obtained good linear effects.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in accompanying drawing:
Fig. 1 is the schematic block circuit diagram of first embodiment of the invention;
Fig. 2 is the schematic block circuit diagram of second embodiment of the invention;
Fig. 3 is the schematic block circuit diagram of third embodiment of the invention;
Fig. 4 is the schematic block circuit diagram one of the of the present invention first or second final stage time-delay and amplifying circuit;
Fig. 5 is the schematic block circuit diagram two of the of the present invention first or second final stage time-delay and amplifying circuit;
Fig. 6 is the theory diagram of reference signal regulating circuit of the present invention;
Fig. 7 is the first error signal regulating circuit of the present invention or the second error signal regulating circuit theory diagram;
Fig. 8 is the structural representation one of the first final amplifier in the embodiment of the present invention, the second final amplifier or the 3rd final amplifier;
Fig. 9 is the structural representation two of the first final amplifier in the embodiment of the present invention, the second final amplifier or the 3rd final amplifier;
Figure 10 is the structural representation three of the first final amplifier in the embodiment of the present invention, the second final amplifier or the 3rd final amplifier.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
In order to realize high efficiency and high linear amplification the to the radiofrequency signal of mobile communication frequency range, the embodiment of the present invention has three the tunnel and closes the high efficiency power amplification circuit of road cancellation function, comprises three tunnel end amplifying circuits, reference signal circuit, error signal extraction circuit, the first mixer and the second mixer; Three tunnel end amplifying circuits comprise the first final stage amplifying circuit, the second final stage amplifying circuit and the 3rd final stage amplifying circuit;
Undistorted main signal is carried out amplitude to reference signal circuit and phase adjusted obtains reference signal;
In any one tunnel final stage amplifying circuit of error signal extraction circuit extraction through amplifying signal, this contains distorted signal and main signal through amplifying signal, the error signal extraction circuit should subtract each other through amplifying signal and reference signal again, and the error signal that obtains after subtracting each other is carried out respectively amplitude and phase adjusted, obtain the first regulating error signal and the second regulating error signal, and be input to respectively in other two-way final stage amplifying circuit;
The first mixer carries out for the first time error signal to the output signal of two-way final stage amplifying circuit wherein and offsets;
The second mixer carries out error signal counteracting for the second time to the output signal of the first mixer and the output signal of other one tunnel final stage amplifying circuit.
The first embodiment of the present invention as shown in Figure 1, the first final stage amplifying circuit comprises successively the first power splitter 1, drive amplification circuit 2, the second power splitter 4, the first final amplifier 5, the first coupler 6 and the first delayer 7 that connects; The input access main signal of the first power splitter 1; The output of the first delayer 7 connects an input of the first mixer 15.be specially: main signal is from the first power splitter 1 input A1 input, output to the input A3 of driving amplifier 2 from the first output terminals A 2 of the first power splitter 1, the signal of 2 pairs of inputs of driving amplifier amplifies, then output to the input A5 of the second power splitter 4 from the output terminals A 4 of driving amplifier 2, output to the input B2 of the first final amplifier 5 from the second output B1 of the second power splitter 4, the first 5 pairs of final amplifiers signal amplifies, can produce distorted signal simultaneously, the signal that is exaggerated and distorted signal output to the input B4 of the first coupler 6 from the output B3 of the first final amplifier 5, then output to the second input D2 of subtracter 8 from the coupled end D1 of the first coupler 6.The output B5 output signal of the first coupler 6 is to the input B6 of the first delayer 7, and the output B7 of the first delayer 7 outputs signal to the first input end B8 of the first mixer 15.
Reference signal circuit comprises reference signal regulating circuit 3 and subtracter 8, the input C2 of reference signal regulating circuit 3 connects the second output C1 of the first power splitter 1, an input C4 of subtracter 8 connects the output C3 of reference signal regulating circuit 3, and another input D2 of subtracter 8 connects the coupled end D1 of the first coupler 6;
The error signal extraction circuit comprises the 3rd power splitter 9, the first error signal regulating circuit 10 and the second error signal regulating circuit 11, the input E2 of the 3rd power splitter 9 connects the output E1 of subtracter 8, the input E4 of the first error signal regulating circuit 10 connects an output E3 of the 3rd power splitter 9, the output E5 output second regulating error signal of the first error signal regulating circuit 10; The input F2 of the second error signal regulating circuit 11 connects another output F1 of the 3rd power splitter 9, the output F3 output first regulating error signal of the second error signal regulating circuit 11;
The second final stage amplifying circuit comprises the 4th power splitter 12 and the time-delay of the first final stage and amplifying circuit 13, the input A7 of the 4th power splitter 12 connects an output terminals A 6 of the second power splitter 4, the first final stage time-delay is connected an output G1 of the 4th power splitter 12 with an input G2 of amplifying circuit 13, the first final stage time-delay accesses first regulating error signal with another input of amplifying circuit 13, namely connects the output F3 of the second error signal regulating circuit 11.The first final stage time-delay is connected another input G4 of the first mixer 15 with the output G3 of amplifying circuit 13; The first final stage time-delay is delayed time with 13 pairs of signals of amplifying circuit, the injection of amplification and error signal, can produce distorted signal simultaneously.
The 3rd final stage amplifying circuit comprises the second final stage time-delay and amplifying circuit 14, the second final stage time-delay is connected another output H1 of the 4th power splitter 12 with an input H2 of amplifying circuit 14, the second final stage time-delay accesses second regulating error signal with another input of amplifying circuit 14, namely connects the output E5 of the first error signal regulating circuit 10; The second final stage time-delay is connected an input H4 of the second mixer 16 with the output H3 of amplifying circuit 14; Another input G6 of the second mixer 16 connects the output G5 of the first mixer 15.The second final stage time-delay is delayed time with 14 pairs of signals of amplifying circuit, the injection of amplification and error signal, can produce distorted signal simultaneously.
the second embodiment of the present invention, as shown in Figure 2, the first final stage amplifying circuit comprises the first power splitter 1, drive amplification circuit 2, the second power splitter 4, the 4th power splitter 12, the first final amplifier 5, the first coupler 6 and the first delayer 7 that connects successively, the input access main signal of the first power splitter 1, the output of the first delayer 7 connects an input of the first mixer 15, be specially: main signal is from the first power splitter 1 input A1 input, output to the input A3 of driving amplifier 2 from the first output terminals A 2 of the first power splitter 1, the signal of 2 pairs of inputs of driving amplifier amplifies, then output to the input A5 of the second power splitter 4 from the output terminals A 4 of driving amplifier 2, output to the input A7 of the 4th power splitter 12 from the second output G1 of the second power splitter 4, the output B1 of the 4th power splitter 12 connects the input B2 of the first final amplifier 5, the first 5 pairs of final amplifiers signal amplifies, can produce distorted signal simultaneously, the signal that is exaggerated and distorted signal output to the input B4 of the first coupler 6 from the output B3 of the first final amplifier 5, then output to the second input D2 of subtracter 8 from the coupled end D1 of the first coupler 6.The output B5 output signal of the first coupler 6 is to the input B6 of the first delayer 7, and the output B7 of the first delayer 7 outputs signal to the first input end B8 of the first mixer 15.
Reference signal circuit comprises reference signal regulating circuit 3 and subtracter 8, the input C2 of reference signal regulating circuit 3 connects an output C1 of the first power splitter 1, an input C4 of subtracter 8 connects the output C3 of reference signal regulating circuit 3, and another input D2 of subtracter 8 connects a coupled end D1 of the first coupler 6;
The error signal extraction circuit comprises the 3rd power splitter 9, the first error signal regulating circuit 10 and the second error signal regulating circuit 11, the input E2 of the 3rd power splitter 9 connects the output E1 of subtracter 8, the input E4 of the first error signal regulating circuit 10 connects an output E3 of the 3rd power splitter 9, the output E5 output second regulating error signal of the first error signal regulating circuit 10, output E5 is connected with the input E6 of amplifying circuit 14 with the second final stage time-delay; The input F2 of the second error signal regulating circuit 11 connects another output F1 of the 3rd power splitter 9, the output F3 output first regulating error signal of the second error signal regulating circuit 11, output F3 is connected with the input F4 of amplifying circuit 13 with the first final stage time-delay;
The second final stage amplifying circuit comprises the first final stage time-delay and amplifying circuit 13, the first final stage time-delay is connected an output G1 of the second power splitter 4 with an input G2 of amplifying circuit 13, the first final stage time-delay accesses the first regulating error signal with another input F4 of amplifying circuit 13, and the first final stage time-delay is connected another input G4 of the first mixer 15 with the output G3 of amplifying circuit 13;
The 3rd final stage amplifying circuit comprises the second final stage time-delay and amplifying circuit 14, the second final stage time-delay is connected an output H1 of the 4th power splitter 12 with an input H2 of amplifying circuit 14, the second final stage time-delay accesses the second regulating error signal with another input E6 of amplifying circuit 14; The second final stage time-delay is connected an input H4 of the second mixer 16 with the output H3 of amplifying circuit 14; Another input G6 of the second mixer 16 connects the output G5 of the first mixer 15.
third embodiment of the invention as shown in Figure 3, the first final stage amplifying circuit comprises successively the first power splitter 1, drive amplification circuit 2, the second power splitter 4, the 4th power splitter 12, the first final amplifier 5, the first coupler 6 and the first delayer 7 that connects, the input access main signal of the first power splitter 1, the output of the first delayer 7 connects an input of the second mixer 16, another input of the second mixer 16 connects the output of the first mixer 15, the first final stage amplifying circuit comprises the first power splitter 1, drive amplification circuit 2, the second power splitter 4, the 4th power splitter 12, the first final amplifier 5, the first coupler 6 and the first delayer 7 that connects successively, the input access main signal of the first power splitter 1, be specially: main signal is from the first power splitter 1 input A1 input, output to the input A3 of driving amplifier 2 from the first output terminals A 2 of the first power splitter 1, the signal of 2 pairs of inputs of driving amplifier amplifies, then output to the input A5 of the second power splitter 4 from the output terminals A 4 of driving amplifier 2, output to the input A7 of the 4th power splitter 12 from the output terminals A 6 of the second power splitter 4, the output B1 of the 4th power splitter 12 connects the input B2 of the first final amplifier 5, the first 5 pairs of final amplifiers signal amplifies, can produce distorted signal simultaneously, the signal that is exaggerated and distorted signal output to the input B4 of the first coupler 6 from the output B3 of the first final amplifier 5, then output to the second input D2 of subtracter 8 from the coupled end D1 of the first coupler 6.The output B5 output signal of the first coupler 6 is to the input B6 of the first delayer 7, and the output B7 of the first delayer 7 outputs signal to the first input end B8 of the second mixer 16.
Reference signal circuit comprises reference signal regulating circuit 3 and subtracter 8, the input C2 of reference signal regulating circuit 3 connects an output C1 of the first power splitter 1, an input C4 of subtracter 8 connects the output C3 of reference signal regulating circuit 3, and another input D2 of subtracter 8 connects a coupled end D1 of the first coupler 6;
The error signal extraction circuit comprises the 3rd power splitter 9, the first error signal regulating circuit 10 and the second error signal regulating circuit 11, the input E2 of the 3rd power splitter 9 connects the output E1 of subtracter 8, the input E4 of the first error signal regulating circuit 10 connects an output E3 of the 3rd power splitter 9, the output E5 output second regulating error signal of the first error signal regulating circuit 10 is connected with an input E6 of amplifying circuit 13 with the first final stage time-delay; The input F2 of the second error signal regulating circuit 11 connects another output F1 of the 3rd power splitter 9, the output F3 output first regulating error signal of the second error signal regulating circuit 11 is connected with an input F4 of amplifying circuit 14 with the second final stage time-delay;
The second final stage amplifying circuit comprises the first final stage time-delay and amplifying circuit 13, the first final stage time-delay is connected an output G1 of the 4th power splitter 12 with an input G2 of amplifying circuit 13, the first final stage time-delay accesses the second regulating error signal with another input E6 of amplifying circuit 13; The first final stage time-delay is connected an input G4 of the first mixer 15 with the output G3 of amplifying circuit 13;
The 3rd final stage amplifying circuit comprises the second final stage time-delay and amplifying circuit 14, the second final stage time-delay is connected an output H1 of the second power splitter 4 with an input H2 of amplifying circuit 14, the second final stage time-delay accesses the first regulating error signal with another input F4 of amplifying circuit 14, and the second final stage time-delay is connected another input H4 of the first mixer 15 with the output H3 of amplifying circuit 14.
The input signal time delay of 8 two inputs of subtracter equates, and the error signal single spin-echo in input signal, and amplitude equates.
Further, in the above-described embodiments, the first final stage time-delay equates with the input signal time delay of two inputs of amplifying circuit 13, and phase place is identical.
Further, in the above-described embodiments, the second final stage time-delay equates with the input signal time delay of two inputs of amplifying circuit 14, and phase place is identical.
Further, in the above-described embodiments, the input signal time delay of two inputs of the first mixer 15 equates, and the error signal single spin-echo in input signal, amplitude does not wait, the amplitude of the error signal of the first final amplifier 5 outputs is bigger, realizes offseting for the first time in first mixer 15 place's error signals.
Further, in the above-described embodiments, the input signal time delay of two inputs of the second mixer 16 equates, and the error signal single spin-echo in input signal, and amplitude equates, finally realizes offseting for the second time of error signal.
Further, in the above-described embodiments, as shown in Figure 4, the first final stage time-delay comprises with amplifying circuit 14 the second delayer 17, the second coupler 19 and the second final amplifier 18 that is connected successively with amplifying circuit 13 or the time-delay of the second final stage.Namely the output of the second delayer 17 connects the input of the second coupler 19, and the output of the second coupler 19 connects the input of the second final amplifier 18.
Further, in the above-described embodiments, as shown in Figure 5, the first final stage time-delay comprises with amplifying circuit 14 the 3rd delayer 20, the 3rd final amplifier 21 and the 3rd coupler 22 that is connected successively with amplifying circuit 13 or the time-delay of the second final stage, namely the output of the 3rd delayer 20 connects the input of the 3rd final amplifier 21, the input of output the 3rd coupler 22 of the 3rd final amplifier 21.
Further, also can the extracting from the second final amplifier 18 or the 3rd final amplifier 21 through amplifying signal of error signal extraction circuit extraction in above-described embodiment.
Further, in above-described embodiment, driving amplifier 2 comprises N amplifier tube, and wherein N is natural number.
Further, in above-described embodiment, the first delayer 7, the second delayer 17 and the 3rd delayer 20 are any in delay line, integrated delayer or filtering wave by prolonging time device.
Further, in above-described embodiment, the first final amplifier 5, the second final amplifier 18 or the 3rd final amplifier 21 comprise N series connection or amplifier tube in parallel, and wherein N is natural number.
Be illustrated in figure 6 as the theory diagram of the reference signal regulating circuit 3 in the present invention, the reference signal regulating circuit comprises the first amplitude modulator 23, the first phase modulator 24, the 4th delay line 25 and the first prime amplifier 26.
the input that is input to the first amplitude modulator 23 from the main signal of the output C1 of the first power splitter 1 output carries out amplitude modulation, the output of the first amplitude modulator 23 is connected to the input of the first phase modulator 24, the signal of 24 pairs of inputs of the first phase modulator carries out phase modulation, the output of the first phase modulator 24 is connected to the input of the 4th delay line 25, the signal of 25 pairs of inputs of the 3rd delay line carries out time delay, the output of the 3rd delay line 25 is connected to the input of the first prime amplifier 26, the signal of 26 pairs of inputs of the first prime amplifier amplifies, and export the signal that is exaggerated by output.
Be illustrated in figure 7 as the first error signal regulating circuit 10 in the present invention and the theory diagram of the second error signal regulating circuit 11, comprise the second amplitude modulator 27, the second phase modulator 28 and the second prime amplifier 29.
Be input to the input of the second amplitude modulator 27 through the error signal of the 3rd power splitter 9 outputs, the second 27 pairs of amplitude modulators error signal is carried out amplitude modulation, the output of the second amplitude modulator 27 is connected to the input of the second phase modulator 28, the signal of 28 pairs of inputs of the second phase modulator carries out phase modulation, the output of the second phase modulator 28 is connected to the input of the second prime amplifier 29, the signal of 29 pairs of inputs of the second prime amplifier amplifies, the output output error conditioning signal of the second prime amplifier 29.
As shown in Fig. 8,9,10, it is the structural representation of three kinds of embodiment of the first final amplifier 5, the second final amplifier 18 or the 3rd final amplifier 21.In Fig. 8, the first final amplifier 5, the second final amplifier 18 or the 3rd final amplifier 21 comprise amplifier 23 and amplifier 24 in parallel, and an end of its parallel connection connects power splitter 28, and the other end connects mixer 31; In Fig. 9, the first final amplifier 5, the second final amplifier 18 or the 3rd final amplifier 21 comprise amplifier 33, amplifier 34 and amplifier 35 in parallel, and an end of its parallel connection connects power splitter 32, and the other end connects mixer 36; In Figure 10, the first final amplifier 5, the second final amplifier 18 or the 3rd final amplifier 21 comprise amplifier 38, amplifier 39, amplifier 40 and amplifier 41 in parallel, and an end of its parallel connection connects power splitter 37, and the other end connects mixer 42.
In implementation process of the present invention, it is to be made of single or a plurality of amplifier tubes series connection that driving amplifier 2 can be selected according to the gain needs of the power amplifier complete machine of reality, in like manner the first final amplifier 5, the second final amplifier 18 or the 3rd final amplifier 21 can be that independently single amplifier tube consists of, can be also to close the road by N amplifier tube to consist of, wherein N is more than or equal to 2, concrete enforcement will be according to the demanded power output of Feed Forward Power Amplifier, and the type selecting of final stage amplifier tube and deciding.because driving amplifier 2 itself has enough rollbacks and all is operated in category-A, therefore linear distortion can be ignored substantially, other the first final amplifier 5, amplifier in the first final stage delay amplification circuit 13 and the second final stage delay amplification circuit 14 is also to be operated in category-A or AB class when designing, therefore also less of the linear distortion of amplifier itself generation, the first final stage amplifying circuit can be operated in different states as required, can be that the AB class can be also the C class, when the first final amplifier is operated in the C class and the amplifier in the first final stage delay amplification circuit 13 and the second final stage delay amplification circuit 14 consist of a Doherty amplifying circuit.In the implementation process of this programme, the first final stage delay amplification circuit 13 and the second final stage delay amplification circuit 14 are used as the error amplifier use, owing to there is no special error amplifier, therefore both saved hardware cost with respect to traditional Feed Forward Power Amplifier, simultaneously reduce again power consumption, made the efficient of power amplifier product effectively improve.The efficient that works in complete machine power amplifier under the condition of C class A amplifier A at the first final amplifier 5 can reach between 40-50% according to the difference of signal peak-to-average ratio.
Should be understood that, for those of ordinary skills, can be improved according to the above description or conversion, and all these improve and conversion all should belong to the protection range of claims of the present invention.
Claims (14)
1. one kind has three the tunnel and closes the high efficiency power amplification circuit of road cancellation function, it is characterized in that, comprises three tunnel end amplifying circuits, reference signal circuit, error signal extraction circuit, the first mixer (15) and the second mixer (16); Described three tunnel end amplifying circuits comprise the first final stage amplifying circuit, the second final stage amplifying circuit and the 3rd final stage amplifying circuit;
Undistorted main signal is carried out amplitude to described reference signal circuit and phase adjusted obtains reference signal;
In any one tunnel final stage amplifying circuit of described error signal extraction circuit extraction through amplifying signal, this contains distorted signal and main signal through amplifying signal, described error signal extraction circuit should subtract each other through amplifying signal and described reference signal again, and the error signal that obtains after subtracting each other is carried out respectively amplitude and phase adjusted, obtain the first regulating error signal and the second regulating error signal, and be input to respectively in other two-way final stage amplifying circuit;
Described the first mixer carries out for the first time error signal to the output signal of two-way final stage amplifying circuit wherein and offsets;
Described the second mixer carries out error signal counteracting for the second time to the output signal of described the first mixer and the output signal of other one tunnel final stage amplifying circuit.
2. according to claim 1 have three the tunnel and close the high efficiency power amplification circuit of road cancellation function, it is characterized in that, wherein:
Described the first final stage amplifying circuit comprises the first power splitter (1), drive amplification circuit (2), the second power splitter (4), the first final amplifier (5), the first coupler (6) and the first delayer (7) that connects successively; The input access main signal of described the first power splitter (1); The output of described the first delayer (7) connects an input of described the first mixer (15);
Described reference signal circuit comprises reference signal regulating circuit (3) and subtracter (8), the input of described reference signal regulating circuit (3) connects an output of the first power splitter (1), and two inputs of described subtracter (8) connect respectively a coupled end of output and first coupler (6) of described reference signal regulating circuit (3);
Described error signal extraction circuit comprises the 3rd power splitter (9), the first error signal regulating circuit (10) and the second error signal regulating circuit (11), the input of described the 3rd power splitter (9) connects the output of subtracter (8), the input of described the first error signal regulating circuit (10) connects an output of described the 3rd power splitter (9), the output output second regulating error signal of described the first error signal regulating circuit (10); The input of described the second error signal regulating circuit (11) connects another output of described the 3rd power splitter (9), the output output first regulating error signal of described the second error signal regulating circuit (11);
described the second final stage amplifying circuit comprises the 4th power splitter (12) and the time-delay of the first final stage and amplifying circuit (13), the input of described the 4th power splitter (12) connects an output of described the second power splitter (4), described the first final stage time-delay is connected an output of described the 4th power splitter (12) with an input of amplifying circuit (13), described the first final stage time-delay accesses described the first regulating error signal with another input of amplifying circuit (13), described the first final stage time-delay is connected another input of described the first mixer (15) with the output of amplifying circuit (13),
Described the 3rd final stage amplifying circuit comprises the second final stage time-delay and amplifying circuit (14), described the second final stage time-delay is connected another output of described the 4th power splitter (12) with an input of amplifying circuit (14), described the second final stage time-delay accesses second regulating error signal with another input of amplifying circuit (14); Described the second final stage time-delay is connected an input of the second mixer (16) with the output of amplifying circuit (14); Another input of described the second mixer (16) connects the output of described the first mixer (15).
3. according to claim 1 have three the tunnel and close the high efficiency power amplification circuit of road cancellation function, it is characterized in that, wherein:
Described the first final stage amplifying circuit comprises the first power splitter (1), drive amplification circuit (2), the second power splitter (4), the 4th power splitter (12), the first final amplifier (5), the first coupler (6) and the first delayer (7) that connects successively; The input access main signal of described the first power splitter (1); The output of described the first delayer (7) connects an input of described the first mixer (15);
Described reference signal circuit comprises reference signal regulating circuit (3) and subtracter (8), the input of described reference signal regulating circuit (3) connects an output of the first power splitter (1), and two inputs of described subtracter (8) connect respectively a coupled end of output and first coupler (6) of described reference signal regulating circuit (3);
Described error signal extraction circuit comprises the 3rd power splitter (9), the first error signal regulating circuit (10) and the second error signal regulating circuit (11), the input of described the 3rd power splitter (9) connects the output of subtracter (8), the input of described the first error signal regulating circuit (10) connects an output of described the 3rd power splitter (9), the output output second regulating error signal of described the first error signal regulating circuit (10); The input of described the second error signal regulating circuit (11) connects another output of described the 3rd power splitter (9), the output output first regulating error signal of described the second error signal regulating circuit (11);
Described the second final stage amplifying circuit comprises the first final stage time-delay and amplifying circuit (13), described the first final stage time-delay is connected an output of described the second power splitter (4) with an input of amplifying circuit (13), described the first final stage time-delay accesses described the first regulating error signal with another input of amplifying circuit (13), and described the first final stage time-delay is connected another input of described the first mixer (15) with the output of amplifying circuit (13);
Described the 3rd final stage amplifying circuit comprises the second final stage time-delay and amplifying circuit (14), described the second final stage time-delay is connected an output of described the 4th power splitter (12) with an input of amplifying circuit (14), described the second final stage time-delay accesses second regulating error signal with another input of amplifying circuit (14); Described the second final stage time-delay is connected an input of the second mixer (16) with the output of amplifying circuit (14); Another input of described the second mixer (16) connects the output of described the first mixer (15).
4. according to claim 1 have three the tunnel and close the high efficiency power amplification circuit of road cancellation function, it is characterized in that, wherein:
Described the first final stage amplifying circuit comprises the first power splitter (1), drive amplification circuit (2), the second power splitter (4), the 4th power splitter (12), the first final amplifier (5), the first coupler (6) and the first delayer (7) that connects successively; The input access main signal of described the first power splitter (1); The output of described the first delayer (7) connects an input of described the second mixer (16); Another input of described the second mixer (16) connects the output of described the first mixer (15);
Described reference signal circuit comprises reference signal regulating circuit (3) and subtracter (8), the input of described reference signal regulating circuit (3) connects an output of the first power splitter (1), and two inputs of described subtracter (8) connect respectively a coupled end of output and first coupler (6) of described reference signal regulating circuit (3);
Described error signal extraction circuit comprises the 3rd power splitter (9), the first error signal regulating circuit (10) and the second error signal regulating circuit (11), the input of described the 3rd power splitter (9) connects the output of subtracter (8), the input of described the first error signal regulating circuit (10) connects an output of described the 3rd power splitter (9), the output output second regulating error signal of described the first error signal regulating circuit (10); The input of described the second error signal regulating circuit (11) connects another output of described the 3rd power splitter (9), the output output first regulating error signal of described the second error signal regulating circuit (11);
Described the second final stage amplifying circuit comprises the first final stage time-delay and amplifying circuit (13), described the first final stage time-delay is connected an output of described the 4th power splitter (12) with an input of amplifying circuit (13), described the first final stage time-delay accesses second regulating error signal with another input of amplifying circuit (13); Described the first final stage time-delay is connected an input of the first mixer (15) with the output of amplifying circuit (13);
Described the 3rd final stage amplifying circuit comprises the second final stage time-delay and amplifying circuit (14), described the second final stage time-delay is connected an output of described the second power splitter (4) with an input of amplifying circuit (14), described the second final stage time-delay accesses described the first regulating error signal with another input of amplifying circuit (14), and described the second final stage time-delay is connected another input of described the first mixer (15) with the output of amplifying circuit (14).
5. any one is described according to claim 2-4 has three the tunnel and closes the high efficiency power amplification circuit of road cancellation function, it is characterized in that, the input signal time delay of (8) two inputs of described subtracter equates, and the error signal single spin-echo in input signal, and amplitude equates.
6. any one is described according to claim 2-4 has three the tunnel and closes the high efficiency power amplification circuit of road cancellation function, it is characterized in that, described the first final stage time-delay equates with the input signal time delay of two inputs of amplifying circuit (13), and phase place is identical.
7. any one is described according to claim 2-4 has three the tunnel and closes the high efficiency power amplification circuit of road cancellation function, it is characterized in that, described the second final stage time-delay equates with the input signal time delay of two inputs of amplifying circuit (14), and phase place is identical.
8. any one is described according to claim 2-4 has three the tunnel and closes the high efficiency power amplification circuit of road cancellation function, it is characterized in that, the input signal time delay of two inputs of described the first mixer (15) equates, and the error signal single spin-echo in input signal, and amplitude does not wait.
9. any one is described according to claim 2-4 has three the tunnel and closes the high efficiency power amplification circuit of road cancellation function, it is characterized in that, the input signal time delay of two inputs of described the second mixer (16) equates, and the error signal single spin-echo in input signal, and amplitude equates.
10. any one is described according to claim 2-4 has three the tunnel and closes the high efficiency power amplification circuit of road cancellation function, it is characterized in that, described the first final stage time-delay comprises with amplifying circuit (14) the second delayer (17), the second coupler (19) and the second final amplifier (18) that is connected successively with amplifying circuit (13) or described the second final stage time-delay.
Have three the tunnel and close the high efficiency power amplification circuit of road cancellation function 11. according to claim 2-4, any one is described, it is characterized in that, described the first final stage time-delay comprises with amplifying circuit (14) the 3rd delayer (20), the 3rd final amplifier (21) and the 3rd coupler (22) that is connected successively with amplifying circuit (13) or described the second final stage time-delay.
Have three the tunnel and close the high efficiency power amplification circuit of road cancellation function 12. according to claim 2-4, any one is described, it is characterized in that, described driving amplifier (2) comprises N amplifier tube, and wherein N is natural number.
13. having according to claim 11 three the tunnel closed the high efficiency power amplification circuit of road cancellation function, it is characterized in that, the 3rd delayer (20) is any in delay line, integrated delayer or filtering wave by prolonging time device.
14. having according to claim 12 three the tunnel closed the high efficiency power amplification circuit of road cancellation function, it is characterized in that, the first final amplifier (5) or the 3rd final amplifier (21) comprise N series connection or amplifier tube in parallel, and wherein N is natural number.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320115968XU CN203278753U (en) | 2013-03-14 | 2013-03-14 | Efficient amplifier with three-circuit combining and twice offsetting functions |
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| CN201320115968XU CN203278753U (en) | 2013-03-14 | 2013-03-14 | Efficient amplifier with three-circuit combining and twice offsetting functions |
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| CN203278753U true CN203278753U (en) | 2013-11-06 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219950A (en) * | 2013-03-14 | 2013-07-24 | 武汉正维电子技术有限公司 | High-efficiency power amplification circuit with three-path combination secondary compensation function |
| CN108390651A (en) * | 2018-02-09 | 2018-08-10 | 厚元技术控股有限公司 | A kind of radio-frequency power amplifier and counteracting method of adaptive feedback canceller distorted signal |
-
2013
- 2013-03-14 CN CN201320115968XU patent/CN203278753U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219950A (en) * | 2013-03-14 | 2013-07-24 | 武汉正维电子技术有限公司 | High-efficiency power amplification circuit with three-path combination secondary compensation function |
| CN103219950B (en) * | 2013-03-14 | 2016-04-27 | 武汉正维电子技术有限公司 | There is the High-efficiency power amplification circuit of three conjunction road, tunnel cancellation functions |
| CN108390651A (en) * | 2018-02-09 | 2018-08-10 | 厚元技术控股有限公司 | A kind of radio-frequency power amplifier and counteracting method of adaptive feedback canceller distorted signal |
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