CN103187284A - Field effect transistor manufacturing method - Google Patents

Abstract

A method for manufacturing a field effect transistor, comprising: providing a substrate; forming a first opening on the substrate; forming a plurality of first multi-fin structures arranged at intervals in the first opening; Filling the first opening of the first multi-fin structure with an organic material; forming a photoresist layer on the organic material, and patterning the photoresist layer; using the patterned photoresist layer as a mask, Part of the first multi-fin structure is removed to form a second multi-fin structure. The present invention adjusts the multi-fin structure with the same line/space (line/space) structure, so that a suitable pitch size between fins can be obtained according to process requirements.

Description

How to make a Field Effect Transistor

technical field

The invention relates to the field of semiconductor manufacturing technology, in particular to a manufacturing method of a multi-fin field effect transistor.

Background technique

With the continuous development of semiconductor industry technology, the adjustment of semiconductor device size has become the main factor to promote the improvement of integrated circuit manufacturing. The structure of conventional MOS field effect transistors can no longer meet the needs of device performance. Therefore, the multi-gate field effect transistor has been developed. Device structures such as transistors (MuGFETs) are used to address this technical challenge. A multi-gate field-effect transistor is a MOSFET with multiple gates, that is, the channel is surrounded by several gates on multiple surfaces, allowing better suppression of leakage currents and enhanced on-state drive current, resulting in enhanced device performance.

A fin field effect transistor (Fin FET) is a common multi-gate structure, and FIG. 1 shows a schematic diagram of a three-dimensional structure of a fin field effect transistor in the prior art. As shown in Figure 1, the Fin FET comprises: a semiconductor substrate 1, on which a protruding fin (Fin) 4 is formed; an oxide layer 2, covering the surface of the semiconductor substrate 1 and the fin A part of the sidewall of 4; the gate structure spans on the fin 4 and covers the top and sidewall of the fin 4. The gate structure includes a gate dielectric layer (not shown in the figure) and is located at the gate The gate electrode 3 on the dielectric layer. For the Fin FET, the part of the fin part 4 in contact with the gate structure forms a channel region, which is beneficial to increase the driving current and improve device performance.

The size of the fin, including the vertical direction (fin height) and the lateral or horizontal direction (fin width), has a great influence on the driving current performance, short channel effect and gate-induced drain leakage (GIDL) ) have a significant impact, however, it is more difficult to control the size of the fin in the Fin FET device according to the current semiconductor process and to be able to continuously reduce the size. The currently used Directed self-assembly (DSA) technology forms a field-effect transistor with a multi-fin structure. Compared with the traditional photolithography process, it can obtain a smaller fin size. The multi-fin pattern of the same line/space (line/space) structure is very limited for the practical application of the semiconductor process.

For example, US Patent Application Publication No. US2010/0087664 A1 discloses a method for directional self-assembly using block copolymers.

In view of this, there is a need for a method for manufacturing a multi-fin field effect transistor, which solves the problem that the line/space (line/space) structure of the multi-fin structure formed by the existing DSA technology is roughly the same, that is, the line width of the fin portion is the same as The spacing between the fins is approximately the same, which cannot meet the actual production process requirements.

Contents of the invention

The invention provides a manufacturing method of a field effect transistor, which can adjust the pitch size between fins according to the process requirements.

In order to solve the above technical problems, an embodiment of the present invention provides a method for manufacturing a field effect transistor, including:

provide the substrate;

forming a first opening on the substrate;

forming a plurality of first multi-fin structures arranged at intervals in the first opening;

Filling the first opening formed with the first multi-fin structure with an organic material;

forming a photoresist layer on the organic material, and patterning the photoresist layer;

Using the patterned photoresist layer as a mask, part of the first multi-fin structure is removed to form a second multi-fin structure.

Optionally, the patterning of the photoresist layer includes setting the pattern of the photoresist layer according to the required pitch of the fins of the second multi-fin structure.

Optionally, the pitch of the fins of the second multi-fin structure is equal.

Optionally, the pitch of the fins of the second multi-fin structure is different.

Optionally, the method for forming a plurality of first multi-fin structures arranged at intervals in the first opening includes:

forming a self-assembled layer within the first opening;

performing annealing treatment on the self-assembled layer to form a strip-shaped first structure and a second structure, and the first structure and the second structure are arranged in parallel with each other;

removing the first structure to form a self-assembled layer having a plurality of second openings;

Using the self-assembled layer with multiple second openings as a mask, etching part of the substrate to form multiple first multi-fin structures arranged at intervals.

Optionally, the material of the self-assembly layer includes polystyrene-polymethyl methacrylate diblock copolymer, the material of the first structure is PMMA, and the material of the second structure is PS.

Optionally, the annealing temperature is below 200°C, and the annealing time is 4-6 minutes.

Optionally, the width of the first structure and the second structure is between 10nm and 20nm.

Optionally, the organic material is a bottom anti-reflection coating.

Optionally, the thickness of the filled organic material at least fills the first opening of the substrate.

Optionally, the removed part of the first multi-fin structure adopts a dry etching process.

Optionally, the etching gas includes HCl and H ₂ , the flow rate of the HCl is 150-300 sccm, and the flow rate of the H ₂ is 15-30 slm.

Optionally, the etching process parameters are: temperature 20˜70° C., pressure 2 mTorr˜100 mTorr.

Optionally, the substrate includes an SOI substrate, and the SOI substrate includes at least an active semiconductor layer, and etching part of the substrate refers to etching a part of the active semiconductor layer to form a first multi-fin structure.

Optionally, the active semiconductor layer includes silicon, SiGe, SiC, Ge or any combination thereof.

Optionally, the substrate includes bulk silicon.

Compared with the prior art, the embodiment of the present invention has the following advantages: through the manufacturing method of the field effect transistor provided by the present invention, it solves the problem of the multi-fin structure formed by DSA technology, and its line/space (line/space) structure is not correct. To meet the requirements of the actual production process, the present invention can adjust the spacing between multiple fins according to the actual process requirements while forming fins with smaller line widths. In the prior art, it is very difficult to form the above-mentioned multi-fin field effect transistor structure through the exposure of the photolithography process. Therefore, compared with the prior art, the process implementation method of the present invention is simpler.

Description of drawings

FIG. 1 is a schematic diagram of a three-dimensional structure of a fin field effect transistor in the prior art;

2 is a schematic flow diagram of a method for manufacturing a multi-fin field effect transistor according to an embodiment of the present invention;

3 to 10 are schematic cross-sectional structural views of an intermediate structure of a method for manufacturing a multi-fin field effect transistor according to an embodiment of the present invention;

FIG. 11 is a schematic flowchart of a manufacturing method of a multi-fin field effect transistor according to an embodiment of the present invention.

Detailed ways

Directed self-assembly (DSA) technology is to deposit block copolymer (blockcopolymer) or polymer blend (polymer blend) on the substrate, usually by spin coating, and through the annealing process to "command" It forms an ordered structure. DSA is compatible with traditional 193nm lithography equipment, eliminating the need for double exposure steps.

As mentioned in the background art, as a possible solution to form smaller-sized patterns, forming patterns by using directional self-assembly technology has attracted the attention of the industry. However, the multi-fin pattern formed by the existing directed self-assembly technology usually has the same line/space (line/space) structure, which means that while obtaining a relatively smaller fin line width, the fin The pitch size between the fins is also very small, which is very limited for the practical application of the semiconductor process, which is not conducive to adjusting the pitch size between the fins according to actual needs.

The purpose of the present invention is to provide a method for manufacturing a multi-fin field effect transistor, which can adjust the fin pitch size of the multi-fin field effect transistor according to actual production process requirements.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

In order to solve the above-mentioned technical problems, the present invention provides a method for manufacturing a multi-fin field effect transistor, as shown in FIG. 2 , which is a schematic flow chart of a method for manufacturing a multi-fin field effect transistor according to an embodiment of the present invention. The method includes at least The following steps:

Step S1: providing a substrate;

Step S2: forming a first opening on the substrate;

Step S2: forming a plurality of first multi-fin structures arranged at intervals in the first opening;

Step S3: filling the first opening formed with the first multi-fin structure with an organic material;

Step S4: forming a photoresist layer on the organic material, and patterning the photoresist layer;

Step S5: Using the patterned photoresist layer as a mask, removing part of the first multi-fin structure to form a second multi-fin structure.

The manufacturing method of the multi-fin field effect transistor of the present invention will be described in detail below with reference to FIG. 2 and FIGS. 3 to 10 . The present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the structure of the device will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the present invention. scope of protection. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

Referring to steps S1 , S2 and FIG. 3 , a substrate is provided on which the first opening 13 is formed.

At present, two kinds of substrates are mainly used to form the fin field effect transistor (Fin FET) device structure, one of which uses a silicon-on-insulator (SOI) substrate, and the other uses a bulk silicon (bulk silicon) substrate.

As an embodiment of the present invention, the substrate in step S1 includes an SOI substrate, and the SOI substrate includes at least a stack of an active semiconductor layer 12 , a buried insulating layer 11 and a bottom substrate 10 .

The SOI substrate can be made of any material known to those skilled in the art, for example, it can include silicon-on-insulator, silicon-germanium-on-insulator, and other semiconductor material stacks on insulator. The active semiconductor layer 12 includes silicon, SiGe, SiC or Ge.

As another embodiment of the present invention, the substrate may also be a bulk silicon substrate.

In step S2, a first opening 13 is formed on the substrate. The first opening 13 is used to define a position for subsequent formation of a self-assembled multi-fin structure. The first opening is used to fill the opening with a self-assembled material. The forming process of the first opening 13 is an etching process, such as dry etching. Since the dry etching process is well known to those skilled in the art, it will not be repeated here.

Since the multi-fin structure is formed on the bulk silicon, unlike the SOI substrate which has an obvious etching stop layer (buried insulating layer 11), the etching depth on the bulk silicon depends entirely on the etching time. Therefore, as a preferred embodiment of the present invention, silicon-on-insulator is used as the substrate, and the fabrication of multi-fin field effect transistors on the SOI substrate will be described in detail below as an example.

Step S3, forming a plurality of first multi-fin structures arranged at intervals in the first opening. Please refer to FIG. 11 for the method of forming the first multi-fin structure. FIG. 11 is a multi-fin field effect according to an embodiment of the present invention. Schematic diagram of the process flow of the transistor manufacturing method, the method includes the following steps:

Step S31, forming a self-assembled layer in the first opening;

Step S32, performing annealing treatment on the self-assembled layer to form strip-shaped first structures and second structures respectively, and the first structures and the second structures are arranged alternately and parallel to each other;

Step S33, removing the first structure to form a self-assembled layer with a plurality of second openings;

Step S34 , using the self-assembled layer with multiple second openings as a mask to etch part of the substrate to form multiple first multi-fin structures arranged at intervals.

The manufacturing method of forming a plurality of first multi-fin structures arranged at intervals in the first opening of the substrate will be described in detail below with reference to FIG. 11 and FIGS. 4 to 7 .

Referring to step S31 and FIG. 4 , a self-assembled layer is formed in the first opening.

Based on the aforementioned SOI substrate, a first opening is formed in the active semiconductor layer 12 of the SOI substrate; a self-assembly material is filled into the first opening to form a self-assembly layer 14 . The block copolymer can be applied in the first opening by a spin coating process.

In DSA technology, under specific process conditions, the copolymers will be rearranged and combined to form a staggered structure. In an embodiment of the present invention, the material of the self-assembly layer 14 is selected from polystyrene-polymethylmethacrylate diblock copolymers (polystyrene-block-poly(methylmethacrylate)copolymers, PS-b-PMMA ), for subsequently forming the first structure and the second structure that are arranged in a staggered manner, and then forming the fin. Under the annealing condition, the PS (polystyrene) material and the PMMA (poly methyl methacrylate) material have a strip structure, and the PS material and the PMMA material are arranged in parallel with each other.

In addition to linear block copolymers, block copolymers with other structures can also be used in DSA, such as star copolymers, branched copolymers, etc.

Referring to step S32 and FIG. 5 , annealing is performed on the self-assembled layer to form a strip-shaped first structure and a second structure, and the first structure and the second structure are arranged alternately and parallel to each other.

The annealing treatment is to bake the self-assembled polymer below 200° C. for about 4-6 minutes, using a conventional baking method. Preferably, the baking temperature is 80-150° C., and the baking time is 5 minutes. The widths of the first structure and the second structure formed after the annealing treatment are approximately the same (approximately 1:1 ratio), so that the subsequently formed first multi-fin structure has approximately the same line/space (line/space) architecture. Wherein, the width of the first structure 15 and the second structure 16 is about 10-20 nm.

In an embodiment of the present invention, the material of the first structure is PMMA, and the material of the second structure is PS.

It should be noted that, in other embodiments of the present invention, the material of the first structure may also be PS, and the material of the second structure may be PMMA.

Referring to step S33 and FIG. 6 , the first structure 15 is removed to form a self-assembled layer (that is, the second structure 16 ) having a plurality of second openings.

Since the PMMA material and PS material arranged at intervals in strips are irradiated by an ultraviolet light source, the PMMA material therein can be removed with acetic acid without affecting the PS material and its arrangement. Therefore, in the embodiment of the present invention, the above method can be used to remove the first structure 15 . The specific steps are: irradiating the annealed self-assembled layer under ultraviolet light with a power of 250W-300W, and then adding acetic acid to remove the first structure 15 to form a self-assembled layer with multiple second openings 17 (ie the second structure 16). Wherein, when the power of the ultraviolet light is 280W, and the volume ratio of CH ₃ COOH and H ₂ O is 3:7, the effect of removing the first structure 15 is better.

Referring to step S34 and FIG. 7 , using the self-assembled layer with the plurality of second openings 17 as a mask, part of the substrate is etched to form a plurality of first multi-fin structures 18 arranged at intervals.

Taking the SOI substrate as an example, etching part of the substrate refers to etching part of the active semiconductor layer 12, and the buried insulating layer 11 is used as an etching stop layer. The etching process may be dry etching. Specifically, the etching gas used for etching part of the active semiconductor layer 12 may include HCl and H ₂ , the flow rate of the HCl is about 150-300 sccm, the flow rate of the H ₂ is about 15-30 slm, and the process parameters are about : The temperature is 20-70°C, and the pressure is 2mTorr-100mTorr.

Since the widths of the first structure 15 and the second structure 16 formed in step S32 are approximately the same, the first multi-fin formed after removing the first structure 15 and etching the substrate with the second structure 16 as a mask The structures 18 are arranged in parallel and at intervals, and have approximately the same line/space structure, that is, the line width of the fins is approximately the same as the spacing between the fins.

Although the above-mentioned first multi-fin structure 18 formed by the DSA technique can obtain a fin pattern with a thinner width (slimer) than the traditional photolithography process, however, because the multi-fin structure usually has the same line/space ( line/space) architecture, in this way, when forming a thinner fin pattern, the spacing between adjacent fins is also very narrow, but in actual products, it is necessary to be able to flexibly adjust the spacing between fins. The purpose of the present invention is to provide a method for manufacturing a field effect transistor, which can adjust the pitch size of the fins according to actual production process requirements.

Referring to step S4 and FIG. 8 , the organic material 19 is filled in the first opening formed with the first multi-fin structure 18 .

Preferably, the filled organic material 19 may be bottom anti-reflective coating (BARC).

Since the multi-fin structure with the same line/space (line/space) architecture is obtained through the aforementioned DSA technology, in order to obtain the fin pitch size required for the actual process, the inventors of the present invention have found through research that it is possible to obtain the multi-fin structure by having the same The photolithography process is continued on the fins of the line/space structure to obtain the desired pitch of the fins.

Since the fin structure is a silicon layer, if the photolithography process is directly used, the light will be reflected from the silicon layer and may damage the adjacent photoresist, which will have an adverse effect on the line width, that is, the dimension control of the fin. Therefore, any technical means known in the art may be used, for example, a spin-coating process may be used to fill the bottom anti-reflective coating in the first opening of the active semiconductor layer 12 forming the first multi-fin structure. Wherein, in order to facilitate subsequent formation of photoresist on the bottom anti-reflection coating, the bottom anti-reflection coating should at least fill the second openings between the multi-fin structures The first opening of the source semiconductor layer is filled and the bottom anti-reflection coating is flush with the active semiconductor layer 12 of the SOI substrate.

The reason why the opening of the active semiconductor layer forming the first multi-fin structure is filled with a liquid organic material can not only reduce the adverse effect of light reflection in the subsequent photolithography process, but also take advantage of the good liquid fluidity of the organic material. By spin-coating the bottom anti-reflective coating in the opening of the active semiconductor layer forming a multi-fin structure, filling the low part of the pattern, so that the cured bottom anti-reflective coating can obtain the flat effect of the surface topography, avoiding subsequent planarization needs.

Referring to step S5 and FIG. 9 , a photoresist layer is formed on the organic material, and the photoresist layer 20 is patterned.

Spin-coat photoresist on the aforementioned surface flush with the active semiconductor layer of the SOI substrate by the bottom anti-reflection coating. According to actual process requirements, for example, according to the pitch size of the fins of the second multi-fin structure to be formed, the pattern of the photoresist layer is set, and the patterned photoresist layer 20 is formed on the bottom anti-reflection coating.

Referring to step S6 and FIG. 10 , using the patterned photoresist layer as a mask, part of the first multi-fin structure is removed to form a desired second multi-fin structure.

An etching process is used for removing part of the multi-fin structure. Since wet etching has a lateral erosion phenomenon, the etching accuracy cannot be controlled, therefore, dry etching is preferred. The widths of the first structure 15 and the second structure 16 formed above are approximately the same, about 10-20 nm, for example, 15 nm. That is, the multi-fin structure 18 has a similar line/space architecture of about 15nm/15nm, ie, the fin size is 15nm, and the fin pitch size is also about 15nm. After removing part of the first multi-fin structure, the formed line/space structure is about 15nm/45nm, that is, the fin size is 15nm, and the fin pitch size is also about 45nm. Therefore, the method for manufacturing a field effect transistor of the present invention , the fin pitch size of the multi-fin structure is adjusted to meet the actual process needs.

It should be noted that, although as shown in FIG. 10 , after part of the first multi-fin structure is removed, the pitch of the fins of the second multi-fin structure is equal, but in actual operation, the fins of the second multi-fin structure can be made The pitch size is not equal, and the adjustment of the pitch size can be obtained by patterning the photoresist. The present invention intends to illustrate that the spacing between multi-fin structures with the same line/space structure can be adjusted, and is not limited to the dimensions shown in the figure.

As an embodiment of the present invention, the etching gas used in the dry etching may include HCl and H ₂ , the flow rate of the HCl is about 150-300 sccm, the flow rate of the H ₂ is about 15-30 slm, and the process parameters Approximately: temperature 20-70°C, pressure 2mTorr-100mTorr.

The present invention pre-forms a multi-fin structure with approximately the same line/space (line/space) structure on the substrate through Directed Self-Assembly (DSA) technology to obtain a smaller fin size, and then removes part of the fin structure to obtain a multi-fin structure with adjustable fin spacing. That is to say, through the method of the present invention, while forming fins with smaller line widths, the spacing between multiple fins can be adjusted according to actual process requirements.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (16)

1. A method for manufacturing a field effect transistor, characterized in that the method comprises: provide the substrate; forming a first opening on the substrate; forming a plurality of first multi-fin structures arranged at intervals in the first opening; Filling the first opening formed with the first multi-fin structure with an organic material; forming a photoresist layer on the organic material, and patterning the photoresist layer; Using the patterned photoresist layer as a mask, part of the first multi-fin structure is removed to form a second multi-fin structure. 2. The method for manufacturing a field effect transistor according to claim 1, wherein said patterning said photoresist layer comprises setting the photoresist layer according to the required fin pitch size of the second multi-fin structure. layer graphics. 3 . The method for fabricating a field effect transistor according to claim 2 , wherein the spacing between the fins of the second multi-fin structure is equal. 4 . 4 . The method for manufacturing a field effect transistor according to claim 2 , wherein the fins of the second multi-fin structure have different pitches. 5. The method for manufacturing a field effect transistor according to claim 1, wherein forming a plurality of first multi-fin structures arranged at intervals in the first opening comprises: forming a self-assembled layer within the first opening; performing annealing treatment on the self-assembled layer to form a strip-shaped first structure and a second structure, and the first structure and the second structure are arranged in parallel with each other; removing the first structure to form a self-assembled layer having a plurality of second openings; Using the self-assembled layer with multiple second openings as a mask, etching part of the substrate to form multiple first multi-fin structures arranged at intervals. 6. The manufacture method of field effect transistor as claimed in claim 5, is characterized in that, described self-assembly layer material comprises polystyrene-polymethyl methacrylate diblock copolymer, and the material of the first structure is PMMA, and the material of the second structure is PS. 7 . The method for manufacturing a field effect transistor according to claim 5 , wherein the annealing temperature is below 200° C., and the annealing time is 4-6 minutes. 8. The method for manufacturing a field effect transistor according to claim 5, wherein the width of the first structure and the second structure is between 10nm and 20nm. 9. The method for manufacturing a field effect transistor according to claim 1, wherein the organic material is a bottom anti-reflection coating. 10 . The method for manufacturing a field effect transistor according to claim 1 , wherein the thickness of the filled organic material at least fills up the first opening of the substrate. 11 . 11 . The method for manufacturing a field effect transistor according to claim 1 , wherein the removed part of the first multi-fin structure adopts a dry etching process. 12. The method for manufacturing a field effect transistor according to claim 11, wherein the etching gas comprises HCl and _H2 , the flow rate of the HCl is 150-300 sccm, and the flow rate of the _H2 is 15-300 sccm. 30slm. 13 . The method for manufacturing a field effect transistor according to claim 11 , wherein the etching process parameters are: a temperature of 20-70° C., and a pressure of 2 mTorr-100 mTorr. 14. The method for manufacturing a field effect transistor according to claim 5, wherein the substrate comprises an SOI substrate, the SOI substrate comprises at least an active semiconductor layer, and the etched part of the substrate is Refers to etching a part of the active semiconductor layer to form a first multi-fin structure. 15. The method for manufacturing a field effect transistor according to claim 14, wherein the active semiconductor layer comprises silicon, SiGe, SiC, Ge or any combination thereof. 16. The method for manufacturing a field effect transistor according to claim 5, wherein the substrate comprises bulk silicon.

Images