CN103187284A - Field effect transistor manufacturing method - Google Patents
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- CN103187284A CN103187284A CN2011104540575A CN201110454057A CN103187284A CN 103187284 A CN103187284 A CN 103187284A CN 2011104540575 A CN2011104540575 A CN 2011104540575A CN 201110454057 A CN201110454057 A CN 201110454057A CN 103187284 A CN103187284 A CN 103187284A
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- 230000005669 field effect Effects 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims description 70
- 239000004065 semiconductor Substances 0.000 claims description 27
- 238000001338 self-assembly Methods 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 239000000126 substance Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 14
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000006117 anti-reflective coating Substances 0.000 claims description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 229920000359 diblock copolymer Polymers 0.000 claims description 3
- 229910003465 moissanite Inorganic materials 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 7
- 239000003292 glue Substances 0.000 abstract 2
- 238000003384 imaging method Methods 0.000 abstract 2
- 239000005416 organic matter Substances 0.000 abstract 2
- 230000000873 masking effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 21
- 238000002408 directed self-assembly Methods 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000004793 Polystyrene Substances 0.000 description 8
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- 229920001400 block copolymer Polymers 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 229920001577 copolymer Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
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- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920002959 polymer blend Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A field effect transistor manufacturing method includes the following steps: a substrate is provided; a first opening is formed in the substrate; a plurality of first multi-fin structures which are arranged at intervals are formed in the first opening; organic matter materials are filled in the first opening which is provided with the first multi-fin structures; a photoetching glue layer is formed on the organic matter materials and subjected to imaging; and a part of the first multi-fin structures are removed to form second multi-fin structures while the photoetching glue layer which is subjected to the imaging is used as a masking film. According to the field effect transistor manufacturing method, through the adjustment of the multi-fin structures provided with the same line / space framework, appropriate pitch dimensions between fins are enabled to be obtained according to technological needs.
Description
Technical field
The present invention relates to field of semiconductor fabrication processes, relate in particular to the manufacture method of many fins field-effect transistor.
Background technology
Along with the sustainable development of semiconductor industry technology, the adjustment of dimensions of semiconductor devices becomes the promotion integrated circuit and makes improved principal element, the structure of conventional MOS field-effect transistor can't satisfy the demand of device performance, therefore, develop the such device architecture of multiple gate field effect transistor (MuGFET) at present and solved this technological challenge.Multiple gate field effect transistor is a kind of MOSFET with a plurality of grids, that is, raceway groove is surrounded by several grids on a plurality of surfaces, thereby can suppress leakage current better, and can strengthen the drive current of conducting state, thereby obtains the device performance of enhancing.
Fin formula field effect transistor (Fin FET) is a kind of common multi-gate structure, and Fig. 1 shows the perspective view of a kind of fin formula field effect transistor of prior art.As shown in Figure 1, Fin FET comprises: Semiconductor substrate 1 is formed with the fin (Fin) 4 of protrusion on the described Semiconductor substrate 1; Oxide layer 2 covers the part of the sidewall of the surface of described Semiconductor substrate 1 and fin 4; Grid structure across on described fin 4, covers top and the sidewall of described fin 4, and grid structure comprises gate dielectric layer (not shown) and the gate electrode 3 that is positioned on the gate dielectric layer.For Fin FET, fin 4 constitutes channel region with the contacted part of grid structure, is conducive to increase drive current, improves device performance.
The size of fin, the size that comprises vertical direction (fin height) and horizontal or horizontal direction (fin width), for drive current performance, short-channel effect and gate-induced drain leakage current (gate-induced drain leakage, GIDL) there is appreciable impact the aspect, yet, control fin size in the Fin FET device and can constantly dwindle the difficulty of this size bigger according to present semiconductor technology.Present directed self assembly (the Directed self-assembly that adopts, DSA) technology forms the field-effect transistor of many fin structures, traditional photoetching process of comparing, can obtain littler fin size, yet the DSA technology can only form the many fins figure with roughly the same circuit/space (line/space) framework usually, and this practical application for semiconductor technology is very limited.
A kind of method of using the directed self assembly of block copolymer is disclosed as U.S. Patent Application Publication No. US2010/0087664 A1.
In view of this, the manufacture method that needs a kind of many fins field-effect transistor, solve because the many fin structures that adopt existing DSA technology to form, its circuit/space (line/space) framework is roughly the same, be that spacing dimension is roughly the same between the live width of fin and the fin, can't satisfy the problem of actual production process requirements.
Summary of the invention
The invention provides a kind of manufacture method of field-effect transistor, can regulate spacing (pitch) size between the fin according to arts demand.
For solving the problems of the technologies described above, the embodiment of the invention provides a kind of manufacture method of field-effect transistor, comprising:
Substrate is provided;
Form first opening at described substrate;
In described first opening, form a plurality of spaced fin structures more than first;
In described first opening that is formed with fin structure more than first, fill the organic substance material;
Form photoresist layer at described organic substance material, graphical described photoresist layer;
Be mask with described patterned photoresist layer, remove part fin structure more than first, form fin structure more than second.
Optionally, described graphical described photoresist layer comprises according to the fin spacing dimension of required fin structure more than second and sets the photoresist layer figure.
Optionally, the fin spacing dimension of described fin structure more than second equates.
Optionally, the fin spacing dimension of described fin structure more than second does not wait.
Optionally, the method for a plurality of spaced fin structures more than first of formation comprises in described first opening:
In described first opening, form the self assembly layer;
Described self assembly layer is carried out annealing in process, form first structure and second structure be strip respectively, and described first structure and second structure is interlaced is arranged in parallel;
Remove described first structure, form the self assembly layer with a plurality of second openings;
Be mask with described self assembly layer with a plurality of second openings, the described substrate of etched portions forms a plurality of spaced fin structures more than first.
Optionally, described self assembly layer material comprises polystyrene-poly methyl methacrylate diblock copolymer, and the material of described first structure is PMMA, and the material of described second structure is PS.
Optionally, described annealing temperature is below 200 ℃, and annealing time is 4～6 minutes.
Optionally, the width of described first structure and second structure is between 10～20nm.
Optionally, described organic substance material is bottom antireflective coating.
Optionally, the thickness of described filling organic substance material to major general's substrate first opening fills up.
Optionally, the fin structure more than first of described removal part adopts dry etch process.
Optionally, described etching gas comprises HCl and H
2, the flow of described HCl is 150～300sccm, described H
2Flow be 15～30slm.
Optionally, described etching technics parameter is: 20～70 ℃ of temperature, pressure are 2mTorr～100mTorr.
Optionally, described substrate comprises the SOI substrate, and described SOI substrate comprises active semiconductor layer at least, and the described substrate of described etched portions refers to that the etched portions active semiconductor layer forms fin structure more than first.
Optionally, described active semiconductor layer comprises silicon, SiGe, SiC, Ge or its combination in any.
Optionally, described substrate comprises body silicon.
Compared with prior art, the embodiment of the invention has the following advantages: by the manufacture method of field-effect transistor provided by the invention, solved because the many fin structures that adopt the DSA technology to form, the problem of the discontented full border of its circuit/space (line/space) framework production technology demand, the present invention is when forming the less fin size of live width, can adjust the spacing dimension between many fins according to the actual process needs again.It is very difficult that prior art forms above-mentioned many fins field-effect transistor structure by the photoetching process exposure, the prior art of therefore comparing, and process implementation method of the present invention is simple.
Description of drawings
Fig. 1 is the perspective view of prior art fin formula field effect transistor;
Fig. 2 is the schematic flow sheet of many fins of one embodiment of the invention field-effect transistor manufacture method;
Fig. 3～Figure 10 is the cross-sectional view of the intermediate structure of many fins of one embodiment of the invention field-effect transistor manufacture method;
Figure 11 is many fins field-effect transistor manufacture method schematic flow sheet according to an embodiment of the invention.
Embodiment
Directed self assembly (Directed self-assembly, DSA) technology is with block co-polymer (block copolymer) or polymeric blends (polymer blend) is deposited on the substrate, usually adopt the rotation coating, and it forms orderly structure with " commander " via annealing process.DSA and the traditional little shadow hardware compatibility of 193nm no longer need the double exposure step.
As described in the background art, as solving the technology that forms the smaller szie pattern, adopt directed self-assembling technique to form the concern that pattern has caused industry.Yet the many fins figure that adopts existing directed self-assembling technique to form, usually has same line/space (line/space) framework, this also just means, when obtaining littler relatively fin live width size, spacing between the fin (pitch) size is also very little, this practical application for semiconductor technology is very limited, is unfavorable for adjusting according to actual needs the spacing dimension between the fin.
The manufacture method that the purpose of this invention is to provide a kind of many fins field-effect transistor can be adjusted the fin spacing dimension of many fins field-effect transistor according to the actual production arts demand.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of many fins field-effect transistor, as shown in Figure 2, Fig. 2 is the schematic flow sheet of many fins of one embodiment of the invention field-effect transistor manufacture method, this method may further comprise the steps at least:
Step S1: substrate is provided;
Step S2: form first opening at described substrate;
Step S2: in described first opening, form a plurality of spaced fin structures more than first;
Step S3: in described first opening that is formed with fin structure more than first, fill the organic substance material;
Step S4: form photoresist layer at described organic substance material, graphical described photoresist layer;
Step S5: be mask with described patterned photoresist layer, remove part fin structure more than first, form fin structure more than second.
Manufacture method below in conjunction with Fig. 2 and many fins of the present invention of Fig. 3～Figure 10 field-effect transistor elaborates.The present invention utilizes schematic diagram to be described in detail; when the embodiment of the invention was described in detail in detail, for ease of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification; and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Refer step S1, S2 and Fig. 3 provide substrate, form first opening 13 at described substrate.
At present mainly adopt two kinds of substrates to form fin formula field effect transistor (Fin FET) device architectures, a kind of employing silicon-on-insulator (SOI) substrate wherein, another uses body silicon (bulk silicon) substrate.
As one embodiment of the invention, substrate described in the step S1 comprises the SOI substrate, and described SOI substrate comprises the lamination of active semiconductor layer 12, buried insulating layer 11 and base substrate 10 at least.
Described SOI substrate can be made of any material that well known to a person skilled in the art, for example can comprise silicon-on-insulator, sige-on-insulator, and other semi-conducting material laminations on the insulator.Described active semiconductor layer 12 comprises silicon, SiGe, SiC or Ge.
As another embodiment of the present invention, described substrate can also be the body silicon substrate.
Form first opening 13 at substrate among the step S2, described first opening 13 is in order to define the position of the many fin structures of follow-up formation self assembly, and described first opening is used for filling self-assembled material at this opening.The formation technology of described first opening 13 is etching technics, for example dry etching.Because described dry etch process is well known to those skilled in the art, does not repeat them here.
Owing to form many fin structures at body silicon, have tangible etch stop layer (buried insulating layer 11) unlike the SOI substrate, the etching depth on body silicon depends on the time of etching fully.Therefore, as the preferred embodiments of the present invention, adopting silicon-on-insulator as substrate, will be that example is described in detail to make many fins field-effect transistor at the SOI substrate below.
Step S3, in described first opening, form a plurality of spaced fin structures more than first, the method that forms fin structure more than first specifically please refer to Figure 11, and Figure 11 is many fins field-effect transistor manufacture method schematic flow sheet according to an embodiment of the invention, and this method may further comprise the steps:
Step S31 forms the self assembly layer in described first opening;
Step S32 carries out annealing in process to described self assembly layer, forms first structure and second structure be strip respectively, and described first structure and second structure is interlaced is arranged in parallel;
Step S33 removes described first structure, forms the self assembly layer with a plurality of second openings;
Step S34 is mask with described self assembly layer with a plurality of second openings, and the described substrate of etched portions forms a plurality of spaced fin structures more than first.
Be described in detail in the manufacture method that forms a plurality of spaced fin structures more than first in first opening of substrate below in conjunction with Figure 11 and Fig. 4～Fig. 7.
Refer step S31 and Fig. 4 form the self assembly layer in described first opening.
Based on aforementioned SOI substrate, in the active semiconductor layer 12 of this SOI substrate, form first opening; In described first opening, fill self-assembled material formation self assembly layer 14.Can block copolymer be put in first opening by spin coating proceeding.
In the DSA technology, copolymer can rearrange combination under specific process conditions, form staggered structure.In an embodiment of the present invention, the material selection of described self assembly layer 14 be polystyrene-poly methyl methacrylate diblock copolymer (polystyrene-block-poly (methyl methacrylate) copolymers, PS-b-PMMA), be used for staggered first structure of follow-up formation and second structure, and then form fin.Under annealing conditions, PS (polystyrene) material and PMMA (poly methyl methacrylate) material is list structure, and described PS material and the PMMA material is interlaced is arranged in parallel.
Except linear block copolymers, the block copolymer with other structures also can be used for DSA, as starlike copolymer, side chain copolymer etc.
Refer step S32 and Fig. 5 carry out annealing in process to described self assembly layer, form first structure and second structure be strip respectively, and described first structure and second structure is interlaced is arranged in parallel.
Described annealing in process is at about 4～6 minutes of baking (bake) below 200 ℃, the baking method that employing is conventional with self-assembling polymers.Preferably, baking temperature is 80-150 ℃, and stoving time is 5 minutes.First structure that forms after the described annealing in process and the width of second structure roughly the same (probably being 1: 1 ratio), and then make the fin structure more than first of follow-up formation have roughly the same circuit/space (line/space) framework.Wherein, the width of described first structure 15 and described second structure 16 is approximately 10～20nm.
In an embodiment of the present invention, the material of described first structure is PMMA, and the material of described second structure is PS.
Need to prove that in other embodiments of the invention, the material of described first structure also can be PS, the material of described second structure is PMMA.
Refer step S33 and Fig. 6 remove described first structure 15, form the self assembly layer (i.e. second structure 16) with a plurality of second openings.
Owing to be the spaced PMMA material of strip and PS material after ultraviolet source irradiation, can remove wherein PMMA material with acetic acid, do not impact and can and not arrange to the PS material.Therefore, in an embodiment of the present invention, can adopt said method to remove described first structure 15.Concrete steps are: the self assembly after the described annealing in process is placed under the ultraviolet light that power is 250W～300W shines, add acetic acid then and remove described first structure 15, form the self assembly layer (i.e. second structure 16) with a plurality of second openings 17.Wherein, when the power of ultraviolet light is 280W, CH
3COOH and H
2The volume ratio of O is 3: 7 o'clock, and the effect of removing described first structure 15 is better.
Refer step S34 and Fig. 7 are mask with described self assembly layer with a plurality of second openings 17, and the described substrate of etched portions forms a plurality of spaced fin structures more than first 18.
Be example with the SOI substrate, the described substrate of etched portions refers to etched portions active semiconductor layer 12, and with buried insulating layer 11 as etching stop layer.Described etching technics can be dry etching.Concrete, the etching gas that etched portions active semiconductor layer 12 adopts can comprise HCl and H
2, the flow of described HCl is approximately 150～300sccm, described H
2Flow be approximately 15～30slm, technological parameter is approximately: 20～70 ℃ of temperature, pressure are 2mTorr～100mTorr.
Because the width of aforementioned first structure 15 that forms in step S32 and second structure 16 is roughly the same, therefore 18 parallel interval of fin structure more than first that form after being the mask etching substrate in removal first structure 15 and with second structure 16 are arranged, has roughly the same circuit/space (line/space) framework, that is, the live width size of fin and the spacing dimension between the fin are roughly the same.
The above-mentioned fin structure more than first 18 that forms through the DSA technology, traditional employing photoetching process can obtain the fin figure of width thinner (slim) though compare, yet, because these many fin structures have identical circuit/space (line/space) framework usually, like this, when formation had thinner fin figure, the spacing between the adjacent fin was also very narrow, and in actual product, need to adjust flexibly the spacing dimension between the fin.The manufacture method that the purpose of this invention is to provide a kind of field-effect transistor can be according to the spacing dimension of actual production arts demand adjustment fin.
Refer step S4 and Fig. 8 in described first opening that is formed with fin structure more than first 18, fill organic substance material 19.
As preferably, the organic substance material 19 of described filling can be bottom antireflective coating (BARC).
Owing to obtained to have many fin structures of identical circuit/space (line/space) framework by aforementioned DSA technology, in order to obtain the required fin spacing dimension of actual process, the present inventor is through discovering, can be by proceeding photoetching process at the fin with same line/space framework, to obtain required fin spacing dimension.
Because fin structure is silicon layer, if directly adopt photoetching process, light will and might damage the photoresist that closes on from the silicon layer reflection so, and this damages for live width is that the size Control of fin can have a negative impact.Therefore can adopt any technological means known in the art, for example, adopt spin coating proceeding in first opening of the active semiconductor layer 12 that forms fin structure more than first, fill bottom antireflective coating.Wherein, form photoresist for ease of follow-up at bottom antireflective coating, bottom antireflective coating is except filling up second opening between many fin structures, at least also first opening of the active semiconductor layer of the many fin structures of described formation to be filled fullly, and bottom antireflective coating be flushed with the active semiconductor layer 12 of SOI substrate.
The organic substance material of filling liquid shape in the opening of the active semiconductor layer that forms fin structure more than first why, except reducing the harmful effect of light reflection in the subsequent optical carving technology, also utilized simultaneously organic substance material better fluid flowability, by spin coating bottom antireflective coating in the opening of the active semiconductor layer that forms many fin structures, the pattern filling lower, make the bottom antireflective coating after solidifying to obtain the smooth effect of surface topography, avoided the needs of subsequent planarization.
Refer step S5 and Fig. 9 form photoresist layer at described organic substance material, graphical described photoresist layer 20.
Aforementioned by spin coating photoresist on bottom antireflective coating and the surface that the active semiconductor layer of SOI substrate flushes.According to the actual process needs, for example, according to the fin spacing dimension of fin structure more than second to be formed, set the photoresist layer figure, form patterned photoresist layer 20 at bottom antireflective coating.
Refer step S6 and Figure 10 are mask with described patterned photoresist layer, remove part fin structure more than first, form required fin structure more than second.
The many fin structures of described removal part adopt etching technics.Because wet etching has the lateral corrasion phenomenon, therefore uncontrollable its etching accuracy, preferably adopts dry etching.Because first structure 15 of aforementioned formation and the width of second structure 16 are roughly the same, are approximately 10-20nm, for example are 15nm.Also namely, many fin structures 18 have similar circuit/space framework and are approximately 15nm/15nm, that is, fin is of a size of 15nm, and the fin spacing dimension also is about 15nm.Through above-mentioned removal part more than first after the fin structure, circuit/space the framework that forms is approximately 15nm/45nm, namely, fin is of a size of 15nm, the fin spacing dimension also is about 45nm, therefore, and the manufacture method of field-effect transistor of the present invention, adjust the fin spacing dimension of many fin structures, satisfied the actual process needs.
Need to prove, though as shown in figure 10, removing part more than first after the fin structure, the fin spacing dimension of fin structure more than second equates, but the fin spacing dimension of fin structure more than second is not waited, and the adjustment of this spacing dimension can graphically obtaining by photoresist.The invention is intended to explanation can adjust the spacing between the many fin structures with same line/space (line/space) framework, is not to be limited to scheme illustrated dimension.
As one embodiment of the invention, the etching gas that described dry etching adopts can comprise HCl and H
2, the flow of described HCl is approximately 150～300sccm, described H
2Flow be approximately 15～30slm, technological parameter is approximately: 20～70 ℃ of temperature, pressure are 2mTorr～100mTorr.
The present invention is by directed self assembly (DSA) technology, be pre-formed the many fin structures with roughly the same circuit/space (line/space) framework at substrate, obtain less fin size, by removing the part fin structure, obtained the adjustable many fin structures of fin spacing then.That is to say, by the present invention's method, when forming the less fin size of live width, can adjust the spacing dimension between many fins according to the actual process needs again.
Though the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (16)
1. the manufacture method of a field-effect transistor is characterized in that, this method comprises:
Substrate is provided;
Form first opening at described substrate;
In described first opening, form a plurality of spaced fin structures more than first;
In described first opening that is formed with fin structure more than first, fill the organic substance material;
Form photoresist layer at described organic substance material, graphical described photoresist layer;
Be mask with described patterned photoresist layer, remove part fin structure more than first, form fin structure more than second.
2. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that, described graphical described photoresist layer comprises according to the fin spacing dimension of required fin structure more than second sets the photoresist layer figure.
3. the manufacture method of field-effect transistor as claimed in claim 2 is characterized in that, the fin spacing dimension of described fin structure more than second equates.
4. the manufacture method of field-effect transistor as claimed in claim 2 is characterized in that, the fin spacing dimension of described fin structure more than second does not wait.
5. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that, forms a plurality of spaced fin structures more than first and comprise in described first opening:
In described first opening, form the self assembly layer;
Described self assembly layer is carried out annealing in process, form first structure and second structure be strip respectively, and described first structure and second structure is interlaced is arranged in parallel;
Remove described first structure, form the self assembly layer with a plurality of second openings;
Be mask with described self assembly layer with a plurality of second openings, the described substrate of etched portions forms a plurality of spaced fin structures more than first.
6. the manufacture method of field-effect transistor as claimed in claim 5, it is characterized in that, described self assembly layer material comprises polystyrene-poly methyl methacrylate diblock copolymer, and the material of described first structure is PMMA, and the material of described second structure is PS.
7. the manufacture method of field-effect transistor as claimed in claim 5 is characterized in that, described annealing temperature is below 200 ℃, and annealing time is 4～6 minutes.
8. the manufacture method of field-effect transistor as claimed in claim 5 is characterized in that, the width of described first structure and second structure is between 10～20nm.
9. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that, described organic substance material is bottom antireflective coating.
10. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that, the thickness of described filling organic substance material to major general's substrate first opening fills up.
11. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that, the described fin structure more than first of removing part adopts dry etch process.
12. the manufacture method of field-effect transistor as claimed in claim 11 is characterized in that, described etching gas comprises HCl and H
2, the flow of described HCl is 150～300sccm, described H
2Flow be 15～30slm.
13. the manufacture method of field-effect transistor as claimed in claim 11 is characterized in that, described etching technics parameter is: 20～70 ℃ of temperature, pressure are 2mTorr～100mTorr.
14. the manufacture method of field-effect transistor as claimed in claim 5, it is characterized in that, described substrate comprises the SOI substrate, and described SOI substrate comprises active semiconductor layer at least, and the described substrate of described etched portions refers to that the etched portions active semiconductor layer forms fin structure more than first.
15. the manufacture method of field-effect transistor as claimed in claim 14 is characterized in that, described active semiconductor layer comprises silicon, SiGe, SiC, Ge or its combination in any.
16. the manufacture method of field-effect transistor as claimed in claim 5 is characterized in that, described substrate comprises body silicon.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110454057.5A CN103187284B (en) | 2011-12-29 | 2011-12-29 | The manufacture method of field-effect transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110454057.5A CN103187284B (en) | 2011-12-29 | 2011-12-29 | The manufacture method of field-effect transistor |
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| Publication Number | Publication Date |
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| CN103187284A true CN103187284A (en) | 2013-07-03 |
| CN103187284B CN103187284B (en) | 2015-10-14 |
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| US9552988B2 (en) | 2015-06-23 | 2017-01-24 | International Business Machines Corporation | Tone inverted directed self-assembly (DSA) fin patterning |
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| US20050056888A1 (en) * | 2003-09-16 | 2005-03-17 | Jae-Man Youn | Double gate field effect transistor and method of manufacturing the same |
| US6872647B1 (en) * | 2003-05-06 | 2005-03-29 | Advanced Micro Devices, Inc. | Method for forming multiple fins in a semiconductor device |
| JP2007207837A (en) * | 2006-01-31 | 2007-08-16 | Toshiba Corp | Semiconductor device, and method of manufacturing same |
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| US20110008956A1 (en) * | 2009-07-10 | 2011-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-assembly pattern for semiconductor integrated circuit |
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| US20040222477A1 (en) * | 2003-05-05 | 2004-11-11 | International Business Machines Corporation | Multi-height finfets |
| US6872647B1 (en) * | 2003-05-06 | 2005-03-29 | Advanced Micro Devices, Inc. | Method for forming multiple fins in a semiconductor device |
| US20050056888A1 (en) * | 2003-09-16 | 2005-03-17 | Jae-Man Youn | Double gate field effect transistor and method of manufacturing the same |
| JP2007207837A (en) * | 2006-01-31 | 2007-08-16 | Toshiba Corp | Semiconductor device, and method of manufacturing same |
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| US9552988B2 (en) | 2015-06-23 | 2017-01-24 | International Business Machines Corporation | Tone inverted directed self-assembly (DSA) fin patterning |
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