CN103681336B - The formation method of semiconductor structure - Google Patents
The formation method of semiconductor structure Download PDFInfo
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- CN103681336B CN103681336B CN201210348128.8A CN201210348128A CN103681336B CN 103681336 B CN103681336 B CN 103681336B CN 201210348128 A CN201210348128 A CN 201210348128A CN 103681336 B CN103681336 B CN 103681336B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000000034 method Methods 0.000 title claims abstract description 85
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- 238000005530 etching Methods 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 26
- 239000013078 crystal Substances 0.000 claims description 19
- 238000001312 dry etching Methods 0.000 claims description 16
- 238000001039 wet etching Methods 0.000 claims description 13
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- 230000001154 acute effect Effects 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 4
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 230000001276 controlling effect Effects 0.000 description 10
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- 238000000151 deposition Methods 0.000 description 6
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
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- 229910021332 silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
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Abstract
A formation method for semiconductor structure, comprising: provide Semiconductor substrate; Form the first hard mask structure at described semiconductor substrate surface, the described first hard mask structure has the bottom surface contacted with described Semiconductor substrate, and wherein, described bottom surface is positioned at the described first projection of hard mask structure on semiconductor substrate surface; Using the described first hard mask structure as mask, etch semiconductor substrates, forms the fin of sidewall slope.The formation method of described semiconductor structure, also comprises: fin portion surface forms grid structure, and described grid structure is across fin end face and sidewall; Form source electrode and drain electrode at fin two ends, described source electrode and drain electrode are positioned at the both sides of grid structure.The formation method of described semiconductor structure, can form the fin formula field effect transistor of fin sidewall slope, and the sloping side wall surfaces of described fin is smooth, improves the performance of fin transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of semiconductor structure.
Background technology
Along with the development of semiconductor process techniques, process node reduces gradually, and rear grid (gate-last) technique is widely applied, and to obtain desirable threshold voltage, improves device performance.But when the characteristic size (CD, CriticalDimension) of device declines further, even if the field effect transistor that after adopting, grid technique makes also cannot meet the demand to device performance, multi-gate device has acquired and has paid close attention to widely.
Fin formula field effect transistor (FinFET) is a kind of common multi-gate device, and Fig. 1 shows a kind of fin of fin formula field effect transistor and the perspective view of grid structure of prior art.As shown in Figure 1, comprising: Semiconductor substrate 10, described Semiconductor substrate 10 is formed with the fin 14 of protrusion; Dielectric layer 11, covers a part for the surface of described Semiconductor substrate 10 and the sidewall of fin 14; Grid structure 12, across described fin 14 covers top and the sidewall of described fin 14, grid structure 12 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on gate dielectric layer.The top of the fin 14 contacted with grid structure 12 and the sidewall constituting channel district of both sides, therefore, FinFET has multiple grid, and this is conducive to increasing drive current, improves device performance.
More structures about fin formula field effect transistor and formation method please refer to the United States Patent (USP) that the patent No. is " US7868380B2 ".
But, often there is the problem such as leakage current, threshold voltage shift, affect the performance of integrated circuit in the transistor that prior art makes.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, the formation method of described semiconductor structure is utilized to form the fin of sidewall slope, described fin sidewall surfaces is smooth, the defect of the follow-up grid structure formed on fin can be reduced, improve the performance of fin formula field effect transistor.
For solving the problem, the present invention proposes a kind of formation method of semiconductor structure, comprising: Semiconductor substrate is provided; Form the first hard mask structure at described semiconductor substrate surface, the described first hard mask structure has the bottom surface contacted with described Semiconductor substrate, and wherein, described bottom surface is positioned at the described first projection of hard mask structure on semiconductor substrate surface; Using the described first hard mask structure as mask, etch semiconductor substrates, forms the fin of sidewall slope.
Optionally, the section shape of the described first hard mask structure is "T"-shaped, inverted trapezoidal or " ten " font.
Optionally, the formation process of the described first hard mask structure is: form hard mask layer at described semiconductor substrate surface; In described hard mask layer, form up-small and down-big opening, described opening exposes the part surface of substrate.
Optionally, the described technique forming up-small and down-big opening in hard mask layer is at least one in photoetching, nano impression, directly self-assembly method, dry etching or wet etching.
Optionally, described hard mask layer has the first hard mask layer being positioned at semiconductor substrate surface and the second hard mask layer being positioned at the first hard mask layer surface; The first opening exposing Semiconductor substrate is formed in described first hard mask layer and the second hard mask layer, forming section first hard mask layer and part second hard mask layer being positioned at described part first hard mask layer surface, wherein, part first hard mask layer is a part for the first mask layer of the first opening both sides, and part second hard mask layer is a part for the second mask layer of the first opening both sides; Select to make the first hard mask layer have the etching technics of high selectivity relative to the second hard mask layer, part first hard mask layer is etched, makes part first hard mask layer along the first opening removal unit partial width, form the described first hard mask structure.
Optionally, described first hard mask layer is not identical with the material of the second hard mask layer.
Optionally, the material of described first hard mask layer is SiO
2, SiN, Si
3n
4or SiON.
Optionally, the material of described second hard mask layer is SiO
2, SiN, Si
3n
4or SiON.
Optionally, the described first hard mask structure comprises part second hard mask layer and the 3rd hard mask layer, and wherein, the 3rd hard mask layer is the part along the first hard mask layer obtained after described first opening etches part first hard mask layer.
Optionally, the width range of described 3rd hard mask layer is 10nm ~ 30nm.
Optionally, the formation process of described 3rd hard mask layer is wet etching or dry etching.
Optionally, by controlling the width of described 3rd hard mask layer, regulate the inclination angle of the sidewall of the fin formed.
Optionally, the technique of described etch semiconductor substrates is dry etching.
Optionally, the technique of described etch semiconductor substrates is plasma etch process, and the bias voltage of described plasma etch process is 100V ~ 300V, and etch period is 50s ~ 100s.
Optionally, by controlling bias voltage and the etch period of described plasma etching, the inclination angle of the sidewall of the fin that adjustment is formed.
Optionally, the Semiconductor substrate of the described employing substrate that to be surperficial crystal face be (100).
Optionally, the sidewall crystal face of the fin of the sidewall slope of described formation is (551), and sidewall slope angle is 82 °, and described angle of inclination is acute angle formed by fin sidewall and substrate surface.
Optionally, the sidewall slope angle of the fin of described formation is 77 ° ~ 87 °, and described angle of inclination is acute angle formed by fin sidewall and substrate surface.
Optionally, also comprise: adopt wet-etching technology to remove the first hard mask structure at fin top; In described fin side grooves, form insulating barrier, described surface of insulating layer is lower than the end face of fin; Form grid structure at insulating barrier and fin portion surface, described grid structure is across fin end face and sidewall; Form source electrode and drain electrode at fin two ends, described source electrode and drain electrode are positioned at the both sides of grid structure.
Compared with prior art, the present invention has the following advantages:
Technical scheme of the present invention, the first hard mask structure is formed at semiconductor substrate surface, described first hard mask structure has the bottom surface contacted with described Semiconductor substrate, and wherein, the bottom surface of the described first hard mask structure is positioned at the projection of described cross section on described semiconductor substrate surface.Utilize the described first hard mask structure as mask, adopt the method for dry etching to etch Semiconductor substrate, form the fin of sidewall slope.Concrete, the section shape of the described first hard mask structure is "T"-shaped, inverted trapezoidal or " ten " font.Carrying out in etching process to Semiconductor substrate, the bottom width of the first hard mask structure determines the width at the final fin top formed.The width of the part that the described first hard mask structure is wider; such as the width of the transverse part of the transverse part at "T"-shaped top, the top of inverted trapezoidal or " cross " is all greater than the width of bottom surface; the structure of described wider portion bottom can be protected in the process that Semiconductor substrate is etched, the bottom width of the first hard mask structure is not suffered a loss.
Further, in technical scheme of the present invention, deposit the first hard mask layer and the second hard mask layer from the bottom to top successively at semiconductor substrate surface, form hard mask structure.After the described first hard mask structure etching, form the first opening of sidewalls vertical.Along described first opening, the first hard mask layer is further etched again, form the first hard mask structure.In the present embodiment, the method for wet etching is adopted to etch the first hard mask layer.Because the first hard mask layer and the second hard mask layer adopt the material same etching technics to different etching ratio, while the first hard mask layer is etched, do not affect part second hard mask layer, forming section shape is the first "T"-shaped hard mask structure.In the process etched Semiconductor substrate, the first hard mask structure part second hard mask layer at the middle and upper levels has protective effect to the 3rd of lower floor the hard mask mask layer.Due in dry etching process, plasma has higher energy, makes the first hard mask structure have loss.In prior art, general individual layer mask, and described individual layer mask can be subject to serious damage in plasma etch process, thus the final size of the fin of impact formation, especially in undersized situation, the final size impact of fin is particularly serious; And in technical scheme of the present invention, three hard mask layer of part second hard mask layer to lower floor on upper strata is protected, prevent it from sustaining damage in etching process and affecting the size of the fin of formation.Because the fin top width size finally formed is determined by the width of lower floor's hard mask layer, thus avoid in etching process, the impact of the impaired fin size for being formed of mask layer.
Further, adopt the method for dry etching to etch described Semiconductor substrate, the vertical bombarding semiconductor substrate of the plasma adopted, plasma diffusion makes part plasma depart from vertical direction, to both sides etch semiconductor substrates.Along with the degree of depth of etching groove increases, form the fin with sloped sidewall gradually.Concrete, technical scheme of the present invention adjusts the slope of the fin sidewall of formation by controlling bias plasma.Regulate the energy of plasma can regulate the speed of etch semiconductor substrates.And plasma can be regulated the speed of Semiconductor substrate bevel etched by controlling etch rate, thus the slope of adjustment fin sidewall.Energy of plasma is larger, and the speed of etching is faster, is scattered the energy also corresponding raising of the plasma of offset from perpendicular, thus adds the etch rate of the Semiconductor substrate to groove both sides, strengthens the slope of the final fin sidewall formed.Technical scheme of the present invention, can also by the slope regulating the width of the 3rd hard mask layer to regulate fin sidewall.When the width of the 3rd hard mask layer reduces, after there is scattering between plasma, the isoionic deviation angle of offset from perpendicular also can correspondingly increase, thus causes the horizontal component to the Semiconductor substrate of groove both sides etches to increase, thus causes the slope of fin sidewall to increase.Employing surface is the substrate of (100) crystal face, the fin sidewall that crystal face is (551) can be formed, the sidewall slope angle of described (551) crystal face is 82 °, by controlling the parameter of plasma etching, also the fin that sidewall inclination angle is 77 ° ~ 87 ° can be formed, described fin sidewall is close to (551) crystal face, the atomic arrangement of the sidewall surfaces of described fin more trends towards regularity than the atomic arrangement of other crystal faces, so the sidewall formed is comparatively smooth, defect is less, the follow-up fin formula field effect transistor performance formed on this fin is also improved.And adopt technical scheme of the present invention to form the sloped sidewall of Different Slope, described sloped sidewall makes the upper opening between adjacent fin increase, the deposition quality of later stage grid structure can be improved, make the fin formula field effect transistor performance of formation more stable; On the other hand, the fin shape that the present invention is formed is conducive to the dispersion of stress, so stress strengthens after grid structure on subsequent deposition, still stably remain on substrate surface and do not collapse.Using the described first hard mask structure as mask, only need etch step just can form the fin of sidewall slope, processing step simply, and can reduce the damage that multiple etching causes fin portion surface.
Accompanying drawing explanation
Fig. 1 is the perspective view of the fin field effect pipe of prior art;
Fig. 2 to Fig. 7 is the generalized section that embodiments of the invention form semiconductor structure.
Embodiment
The problems such as described in the background art, current fin formula field effect transistor exists leakage current, and threshold voltage is unstable, affect the performance of transistor and integrated circuit.
Find through research, in fin formula field effect transistor, the interface quality between grid structure and fin is very large for the performance impact of fin formula field effect transistor.Research finds, Si (551) surface is compared with Si (110) surface, and more easily make atomic arrangement neat, blemish is less, and current driving ability is high.Described Si (551) crystal face is the face tilted, and the fin of sidewall slope is more conducive to the deposition of grid structure, improves interface quality.And prior art forms the comparatively complicated etching needing to carry out repeatedly to fin of the most technical process of fin of sloped sidewall, easily damage is caused to fin sidewall.
For solving the problem, embodiments of the invention propose a kind of formation method of semiconductor structure, using first of T-shaped the hard mask structure as mask, carry out dry etching to Semiconductor substrate, form the fin with sloped sidewall, and form fin formula field effect transistor on this basis.The formation method of described semiconductor structure, processing step is simple, need only once etch the fin just defining sidewall slope, decrease the damage to fin portion surface.
Below in conjunction with accompanying drawing, by specific embodiment, carry out clear, complete description to technical scheme of the present invention, obviously, described embodiment is only a part for embodiment of the present invention, instead of they are whole.According to described embodiment, those of ordinary skill in the art's obtainable other execution modes all under without the need to the prerequisite of creative work, all belong to protection scope of the present invention.
Concrete, please refer to Fig. 2 to Fig. 7, Fig. 2 to Fig. 7 is the generalized section that the present embodiment forms semiconductor structure.
Please refer to Fig. 2, provide Semiconductor substrate 100, described substrate surface has mask structure 200.
The material of described Semiconductor substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, can be body material also can be that composite construction is as silicon-on-insulator.In the present embodiment, Semiconductor substrate 100 is body silicon.Described Semiconductor substrate 100 provides platform for subsequent technique.
In the present embodiment, described hard mask structure 200 has the first hard mask layer 210 and the second hard mask layer 220, and described first hard mask layer 210 is positioned at substrate surface, and described second hard mask layer 220 is positioned at the first hard mask layer 210 surface.Utilize chemical vapor deposition method, deposit described first hard mask layer 210 and the second hard mask layer 220 successively at substrate surface.The material of described first hard mask layer comprises SiO
2, SiN, Si
3n
4or one or more materials in SiON; The material of described second hard mask layer comprises SiO
2, SiN, Si
3n
4or one or more materials in SiON; And described first hard mask layer and the second hard mask layer have different selective etching ratios.
In the present embodiment, the material of the first hard mask layer 210 is silicon nitride, and the material of the second hard mask layer 220 is silica.In the present embodiment, the thickness of the first hard mask layer 210 is 500nm ~ 1000nm, and the thickness of the second hard mask layer 220 is 500 ~ 1000nm.
Please refer to Fig. 3, etch described hard mask structure 200 (as shown in Figure 2), in described hard mask structure, form the first opening, expose substrate portions surface.
Concrete, utilize spin-coating method to form photoresist layer, by graphical after development exposure on described hard mask structure 200 (as shown in Figure 2) surface.Utilize graphical photoresist layer as mask, etch described hard mask structure 200 to Semiconductor substrate 100 surface, in described hard mask structure 200, form opening, the upper and lower width of described first opening is consistent, exposes the part surface of Semiconductor substrate.Opening both sides have part first hard mask layer 210a and part second hard mask layer 220a, and described part second hard mask layer 220a is positioned at part first hard mask layer 210a upper strata.The position of the first opening that described upper and lower width is consistent defines the grooved position between the fin of formation.The technique of the hard mask structure 200 of described etching comprises one or more techniques in photoetching, nano impression, directly self assembly (DSA), dry etching or wet etching.
Please refer to Fig. 4, independent etching described part first hard mask layer 210a (as shown in Figure 3), form the 3rd hard mask layer 210b, its final width is made to be less than part second hard mask layer 220a, form the second up-small and down-big opening and the first hard mask structure 230, the described first hard mask structure is "T"-shaped.
The technique etched described part first hard mask layer 210a is wet etching or dry etching.In the present embodiment, adopt the technique of wet etching to etch described part first hard mask layer 210a, form the 3rd hard mask layer 210b, make the width of the 3rd hard mask layer 210b be less than part second hard mask layer 220a.The part second hard mask layer 220a on described 3rd hard mask layer 210b and upper strata forms the first hard mask structure 230, and the described first hard mask structure 230 is in "T"-shaped, have the second opening between described first hard mask structure 230, described second opening is up-small and down-big inverse-T-shaped.
In embodiments of the invention, because described part first hard mask layer 210a is different with the material that part second hard mask layer 220a adopts, so select etching solution bi-material to high etching selection ratio, described etching solution can only etch part first hard mask layer 210a.In the present embodiment, the material of part first hard mask layer 210a is silicon nitride, and the material of part second hard mask layer 220a is silica, and the etching solution of employing is the phosphoric acid solution of boiling.Due to concentration be 85% phosphoric acid solution 180 DEG C time to the etch rate of silicon dioxide slowly, so can be used for doing the selective etch of silicon nitride and silicon dioxide.It is generally 10nm/min to the etch rate of silicon nitride, to the etch rate of silicon dioxide then far below 10nm/min.According to the width of the fin end face needed in side circuit, control the width of the 3rd hard mask layer 210b formed, the width of described 3rd hard mask layer 210b equals or slightly larger than the width of the final fin end face formed.In the present embodiment, the width of described 3rd hard mask layer 210b is 10nm ~ 30nm.
In an embodiment of the present invention, other two kinds not identical materials can be selected to form described part first hard mask layer 210a and part second hard mask layer 220a, and according to described two kinds of not identical materials, select to have the etching solution of high selectivity, only etch described part first hard mask layer 210a and non-etched portions second hard mask layer 220a.
In other embodiments of the invention, the technique of dry etching can also be adopted.But, compared with dry etching, adopt the Etch selectivity of wet-etching technology to different materials higher, be more conducive to the first hard mask structure forming T-shaped.
In other embodiments of the invention, also at least one technique in photoetching, nano impression, directly self-assembly method, dry etching or wet etching can be adopted to form the first hard mask structure, between described first hard mask structure, there is up-small and down-big opening, and the bottom surface of the described first hard mask structure is positioned at the described first projection of hard mask structure on semiconductor substrate surface.The section shape of the described first hard mask structure can also be inverse-T-shaped, " ten " font.
Please refer to Fig. 5, using the first hard mask structure 230 as mask, etch semiconductor substrates 100, forms the fin 110 of sidewall slope.
Concrete, the described first hard mask structure 230 comprises the part second hard mask layer 220a of the 3rd hard mask layer 210b and top thereof.
Dry etch process is adopted to etch described Semiconductor substrate 100.In the present embodiment, the method for using plasma etching, plasma, with certain energy normal bombardment substrate surface, is not etched by the region that the first hard mask structure 230 covers substrate surface.After plasma enters the opening between the first hard mask structure 230, due to the scattering process between plasma, part plasma can be made to depart from vertical direction and have horizontal component, most of plasma still carries out etching to Semiconductor substrate in the vertical direction and forms groove simultaneously.In the present embodiment, the bias voltage of plasma etching is 100V ~ 300V, and etch period is 50 seconds ~ 100 seconds.
The plasma of part offset from perpendicular, using the 3rd hard mask layer 210b as mask, the Semiconductor substrate of etching groove both sides.Along with gash depth is larger, the time be more etched close to the Semiconductor substrate of the groove both sides of substrate surface is longer, and the material of Semiconductor substrate is etched more, and the width of groove is then larger, causes the shape that groove is big up and small down.Finally, the sidewall of sidewall slope is defined in the both sides of groove.In the present embodiment, employing surface is the Semiconductor substrate of (100) crystal face, by controlling the bias voltage of plasma etching and the width and other processes parameter of the 3rd hard mask layer, make the fin sidewall crystal face formed be Si (551), formed by sidewall and substrate surface, acute angle is 82 °.Be significantly improved compared with other crystal faces at the surface smoothness of Si of the present invention (551) crystal face, thus using Si (551) as the sidewall of fin, effectively can reduce the defect of fin portion surface.In other embodiments of the invention, can form the sidewall of the fin 110 of similar Si (551) crystal face, formed by described sidewall and substrate surface, acute angle is 77 ° ~ 87 °.Except acute angle formed by sidewall and substrate surface is except the crystal face of 82 °, the crystal face of described fin sidewall is not (551) face, but close to (551) face, evenness just can be slightly poorer than it, but do not have the change of matter.
Further, formed when grid structure in fin portion surface, also can improve deposition quality and the interface quality each other of gate dielectric layer and gate electrode, reduce leakage current, the performance of raising fin formula field effect transistor.
In other embodiments of the invention, the energy of plasma can be regulated by controlling bias plasma, thus regulate the speed of etch semiconductor substrates.And plasma can be regulated the speed of Semiconductor substrate bevel etched by controlling etch rate, thus the slope of adjustment fin 110 sidewall.Energy of plasma is larger, and the speed of etching is faster, is scattered the energy also corresponding raising of the plasma of offset from perpendicular, thus adds the etch rate of the Semiconductor substrate to groove both sides, strengthens the slope of final fin 110 sidewall formed.
In other embodiments of the invention, can also by the slope regulating the width of the 3rd hard mask layer 210b to regulate fin 110 sidewall of formation.Reduce the width of the 3rd hard mask layer 210b, the width of the corresponding increase of meeting hard mask structure lower middle portion opening.There is scattering between plasma after, the isoionic deviation angle of offset from perpendicular also can correspondingly increase, thus cause the horizontal component to the Semiconductor substrate of groove both sides etches to increase, and the width of the end face of the fin 110 formed is the width also corresponding reduction of the 3rd hard mask layer 210b, thus the slope of fin 110 sidewall is caused to increase.
In other embodiments of the present invention, also can adopt the substrate of other crystal faces, form the fin of sidewall slope.Can be realized the adjustment to fin sidewall slope by the bottom width controlling the bias voltage of plasma etching and the mask structure of formation, processing step flexibly and easily realize.
Due in dry etching process, plasma has higher energy, and hard mask structure can be sustained damage.If adopt the hard mask structure of individual layer as mask, the shape that after sustaining damage, change in size is formed after directly affecting substrate etching.The the first double-deck hard mask structure 230 is adopted in the present embodiment; the part second hard mask layer 220a on upper strata is utilized to protect the 3rd hard mask layer 210b of lower floor; because the fin top width size finally formed is determined by the width of the 3rd hard mask layer 210b of lower floor; thus avoid in etching process, the impact of the impaired fin size for being formed of mask layer.
In other embodiments of the present invention, also can form the first hard mask structure that section shape is inverted trapezoidal or " ten " font.Described section shape is that the part that the width major part of the first hard mask structure of inverted trapezoidal or " ten " font is less to the width below it plays a protective role equally, and the bottom surface of the make first hard mask structure is formed at etch semiconductor substrates in the process of fin does not suffer a loss.
Please refer to Fig. 6, remove the first hard mask structure 230 (as shown in Figure 5) of semiconductor substrate surface.
It is wet etching that the first hard mask structure 230 removing described semiconductor substrate surface comprises the technique removing described 3rd hard mask layer 210b (as shown in Figure 5) and part second hard mask layer 220a (as shown in Figure 5).After removing the described first hard mask structure 230, substrate surface only has fin 110.
In the present embodiment, fin formula field effect transistor can also be formed on the fin basis with sloped sidewall of described formation.
Please refer to Fig. 7, in described fin 110 side grooves, form insulating barrier 120, described insulating barrier 120 surface is lower than the end face of fin; Form grid structure at insulating barrier 120 and fin 110 surface, described grid structure is across fin 110 end face and sidewall; Form source electrode and drain electrode (not shown) at fin two ends, described source electrode and drain electrode are positioned at the both sides of grid structure.
Concrete, the material of described insulating barrier 120 is silica or silicon oxynitride, and the formation process of described insulating barrier 120 is that shallow trench is filled.After etching forms the fin 110 of sidewall slope, only remove the part second hard mask layer 220a on upper strata, then deposition of insulative material in groove.First the grooved inner surface in fin 110 both sides grows one deck liner oxidation layer with hot oxygen method, fills full insulating material more afterwards with CVD in groove.Forming described liner oxidation layer is the lattice damage that the etching technics forming the first fin to eliminate previous step causes trenched side-wall i.e. the first fin sidewall, reduces defect.Remove the insulating material at fin top with cmp (CMP) technology, and using the 3rd hard mask layer 210b as grinding stop layer, form smooth surface.Return using described 3rd hard mask layer 210b as mask again and carve described insulating material, form insulating barrier 120.Remove described 3rd hard mask layer 210b afterwards again.
Described grid structure comprises gate dielectric layer 130 and gate electrode layer 140.The material of described gate dielectric layer 130 comprises silica, silicon oxynitride or hafnium.Described gate electrode layer material is polysilicon, metal silicide or metal.Described grid structure be positioned at insulating barrier 120 surface and across described fin 110 end face and sidewall.With described grid structure for mask, in the fin 110 of described grid structure both sides, doping forms source/drain (not shown).
In embodiments of the invention, first of double-deck T-shaped the hard mask structure is adopted to carry out etching the fin forming sidewall slope to substrate as mask, described fin sidewall is close to (551) crystal face, there is atomic arrangement neat, the advantage of surfacing, is conducive to the performance improving the device that the later stage is formed.And the fin of sidewall slope is conducive to, forming in fin formula field effect transistor process the deposition of carrying out carrying out insulating material when shallow trench is filled between adjacent fin, due to sidewall slope, making the generation that can reduce defect in deposition process; When formation grid, also contribute to the interface quality improving contact-making surface, improve the performance of transistor.
In embodiments of the invention, can be realized the adjustment to fin sidewall slope by the bottom width controlling the bias voltage of plasma etching and the mask structure of formation, processing step flexibly and easily realize.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (19)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate is provided;
The first hard mask structure is formed at described semiconductor substrate surface, described first hard mask structure has the bottom surface contacted with described Semiconductor substrate, wherein, described bottom surface is positioned at the described first projection of hard mask structure on semiconductor substrate surface, and described bottom width is less than the Breadth Maximum of the described first hard mask structure;
Using the described first hard mask structure as mask, etch semiconductor substrates, forms the fin of sidewall slope.
2. the formation method of semiconductor structure according to claim 1, is characterized in that, the section shape of the described first hard mask structure is "T"-shaped, inverted trapezoidal or " ten " font.
3. the formation method of semiconductor structure according to claim 2, is characterized in that, the formation process of the described first hard mask structure is: form hard mask layer at described semiconductor substrate surface; In hard mask layer, form up-small and down-big opening, described opening exposes the part surface of substrate.
4. the formation method of semiconductor structure according to claim 3, is characterized in that, the described technique forming up-small and down-big opening in hard mask layer is at least one in photoetching, nano impression, directly self-assembly method, dry etching or wet etching.
5. the formation method of semiconductor structure according to claim 3, is characterized in that, described hard mask layer has the first hard mask layer being positioned at semiconductor substrate surface and the second hard mask layer being positioned at the first hard mask layer surface; The first opening exposing Semiconductor substrate is formed in described first hard mask layer and the second hard mask layer, forming section first hard mask layer and part second hard mask layer being positioned at described part first hard mask layer surface, wherein, part first hard mask layer is a part for the first mask layer of the first opening both sides, and part second hard mask layer is a part for the second mask layer of the first opening both sides; Select to make the first hard mask layer have the etching technics of high selectivity relative to the second hard mask layer, part first hard mask layer is etched, makes part first hard mask layer along the first opening removal unit partial width, form the described first hard mask structure.
6. the formation method of semiconductor structure according to claim 5, is characterized in that, described first hard mask layer is not identical with the material of the second hard mask layer.
7. the formation method of semiconductor structure according to claim 6, is characterized in that, the material of described first hard mask layer is SiO
2, SiN, Si
3n
4or SiON.
8. the formation method of semiconductor structure according to claim 6, is characterized in that, the material of described second hard mask layer is SiO
2, SiN, Si
3n
4or SiON.
9. the formation method of semiconductor structure according to claim 5, it is characterized in that, described first hard mask structure comprises part second hard mask layer and the 3rd hard mask layer, wherein, the 3rd hard mask layer is the part along the first hard mask layer obtained after described first opening etches part first hard mask layer.
10. the formation method of semiconductor structure according to claim 9, is characterized in that, the width range of described 3rd hard mask layer is 10nm ~ 30nm.
The formation method of 11. semiconductor structures according to claim 9, is characterized in that, the formation process of described 3rd hard mask layer is wet etching or dry etching.
The formation method of 12. semiconductor structures according to claim 10, is characterized in that, by controlling the width of described 3rd hard mask layer, regulates the inclination angle of the sidewall of the fin formed.
The formation method of 13. semiconductor structures according to claim 1, is characterized in that, the technique of described etch semiconductor substrates is dry etching.
The formation method of 14. semiconductor structures according to claim 1, is characterized in that, the technique of described etch semiconductor substrates is plasma etch process, and the bias voltage of described plasma etch process is 100V ~ 300V, and etch period is 50s ~ 100s.
The formation method of 15. semiconductor structures according to claim 14, is characterized in that, by controlling bias voltage and the etch period of described plasma etching, and the inclination angle of the sidewall of the fin that adjustment is formed.
The formation method of 16. semiconductor structures according to claim 1, is characterized in that, the Semiconductor substrate of the employing substrate that to be surperficial crystal face be (100).
The formation method of 17. semiconductor structures according to claim 16, it is characterized in that, the sidewall crystal face of the fin of the sidewall slope of described formation is (551), and sidewall slope angle is 82 °, and described angle of inclination is acute angle formed by fin sidewall and substrate surface.
The formation method of 18. semiconductor structures according to claim 1, is characterized in that, the sidewall slope angle of the fin of described formation is 77 ° ~ 87 °, and described angle of inclination is acute angle formed by fin sidewall and substrate surface.
The formation method of 19. semiconductor structures according to claim 1, is characterized in that, also comprise: adopt wet-etching technology to remove the first hard mask structure at fin top; In described fin side grooves, form insulating barrier, described surface of insulating layer is lower than the end face of fin; Form grid structure at insulating barrier and fin portion surface, described grid structure is across fin end face and sidewall; Form source electrode and drain electrode at fin two ends, described source electrode and drain electrode are positioned at the both sides of grid structure.
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| TW201234589A (en) * | 2011-02-09 | 2012-08-16 | United Microelectronics Corp | Fin field-effect transistor structure and manufacturing process thereof |
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