CN103681336A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN103681336A CN103681336A CN201210348128.8A CN201210348128A CN103681336A CN 103681336 A CN103681336 A CN 103681336A CN 201210348128 A CN201210348128 A CN 201210348128A CN 103681336 A CN103681336 A CN 103681336A
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- 229910052581 Si3N4 Inorganic materials 0.000 description 4
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- 238000012545 processing Methods 0.000 description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a method for forming a semiconductor structure. The method comprises the following steps: providing a semiconductor substrate; forming a first hard mask structure on the surface of the semiconductor substrate, wherein the first hard mask structure has a bottom surface in contact with the semiconductor substrate, and the bottom surface is positioned within the projection of the first hard mask structure on the surface of the semiconductor substrate; taking the first hard mask structure as mask, etching the semiconductor substrate to form a fin part whose side walls are inclined. The method for forming a semiconductor structure also comprises the following steps: forming a gate structure on the surface of the fin part, the gate structure going across the top surface and the side wall of the fin part; forming a source and a drain at two ends of the fin part, wherein the source and the drain is positioned on two sides of the gate structure. The method for forming a semiconductor structure can form a fin-type field-effect transistor in which the side walls of the fin part are inclined and the inclined side walls of the fin part have a smooth surface, as a result, the performance of the fin-type field-effect transistor is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of semiconductor structure.
Background technology
Along with the development of semiconductor process techniques, process node reduces gradually, and rear grid (gate-last) technique is widely applied, and to obtain desirable threshold voltage, improves device performance.But when the characteristic size (CD, Critical Dimension) of device further declines, even if the field effect transistor that after adopting, grid technique is made also cannot meet the demand to device performance, multiple-grid device has acquired widely and has paid close attention to.
Fin formula field effect transistor (Fin FET) is a kind of common multiple-grid device, and Fig. 1 shows a kind of fin of fin formula field effect transistor and the perspective view of grid structure of prior art.As shown in Figure 1, comprising: Semiconductor substrate 10, is formed with the fin 14 of protrusion in described Semiconductor substrate 10; Dielectric layer 11, covers the part of the surface of described Semiconductor substrate 10 and the sidewall of fin 14; Grid structure 12, across on described fin 14 and cover top and the sidewall of described fin 14, grid structure 12 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on gate dielectric layer.The sidewall constituting channel district of the top of the fin 14 contacting with grid structure 12 and both sides, therefore, Fin FET has a plurality of grid, and this is conducive to increase drive current, improves device performance.
More structures about fin formula field effect transistor and formation method please refer to the United States Patent (USP) that the patent No. is " US7868380B2 ".
But, often there is the problems such as leakage current, threshold voltage shift in the transistor that prior art is made, affects the performance of integrated circuit.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, utilize the fin of the formation method formation sidewall slope of described semiconductor structure, described fin sidewall surfaces is smooth, can reduce the defect of the follow-up grid structure forming on fin, improve the performance of fin formula field effect transistor.
For addressing the above problem, the present invention proposes a kind of formation method of semiconductor structure, comprising: Semiconductor substrate is provided; At described semiconductor substrate surface, form the first hard mask structure, the described first hard mask structure has the bottom surface contacting with described Semiconductor substrate, and wherein, described bottom surface is positioned at the described first projection of hard mask structure on semiconductor substrate surface; Using the described first hard mask structure as mask, etching semiconductor substrate, the fin of formation sidewall slope.
Optionally, the section shape of the described first hard mask structure is "T"-shaped, inverted trapezoidal or " ten " font.
Optionally, the formation technique of the described first hard mask structure is: at described semiconductor substrate surface, form hard mask layer; In described hard mask layer, form up-small and down-big opening, described opening exposes the part surface of substrate.
Optionally, the described technique that forms up-small and down-big opening in hard mask layer is photoetching, nano impression, direct at least one in self-assembly method, dry etching or wet etching.
Optionally, described hard mask layer has the second hard mask layer that is positioned at the first hard mask layer of semiconductor substrate surface and is positioned at the first hard mask layer surface; In described the first hard mask layer and the second hard mask layer, form the first opening that exposes Semiconductor substrate, forming section the first hard mask layer and part the second hard mask layer that is positioned at described part the first hard mask layer surface, wherein, part the first hard mask layer is a part for the first mask layer of the first opening both sides, and part the second hard mask layer is a part for the second mask layer of the first opening both sides; Selection makes the first hard mask layer with respect to the second hard mask layer, have the etching technics of high selectivity, and part the first hard mask layer is carried out to etching, makes part the first hard mask layer remove partial width along the first opening, forms the described first hard mask structure.
Optionally, the material of described the first hard mask layer and the second hard mask layer is not identical.
Optionally, the material of described the first hard mask layer is SiO
2, SiN, Si
3n
4or SiON.
Optionally, the material of described the second hard mask layer is SiO
2, SiN, Si
3n
4or SiON.
Optionally, the described first hard mask structure comprises part the second hard mask layer and the 3rd hard mask layer, and wherein, the 3rd hard mask layer is for carrying out a part for the first hard mask layer of obtaining after etching to part the first hard mask layer along described the first opening.
Optionally, the width range of described the 3rd hard mask layer is 10nm ~ 30nm.
Optionally, the formation technique of described the 3rd hard mask layer is wet etching or dry etching.
Optionally, by controlling the width of described the 3rd hard mask layer, regulate the inclination angle of the sidewall of the fin forming.
Optionally, the technique of described etching semiconductor substrate is dry etching.
Optionally, the technique of described etching semiconductor substrate is plasma etch process, and the bias voltage of described plasma etch process is 100V ~ 300V, and etch period is 50s ~ 100s.
Optionally, by controlling bias voltage and the etch period of described plasma etching, adjust the inclination angle of the sidewall of the fin forming.
Optionally, the Semiconductor substrate of described employing is the substrate that surperficial crystal face is (100).
Optionally, the sidewall crystal face of the fin of the sidewall slope of described formation is (551), and sidewall slope angle is 82 °, and described angle of inclination is the acute angle angle that fin sidewall becomes with substrate surface.
Optionally, the sidewall slope angle of the fin of described formation is 77 ° ~ 87 °, and described angle of inclination is the acute angle angle that fin sidewall becomes with substrate surface.
Optionally, also comprise: adopt wet-etching technology to remove the first hard mask structure at fin top; In described fin side grooves, form insulating barrier, described surface of insulating layer is lower than the end face of fin; At insulating barrier and fin surface, form grid structure, described grid structure is across fin end face and sidewall; At fin two ends, form source electrode and drain electrode, described source electrode and drain electrode are positioned at the both sides of grid structure.
Compared with prior art, the present invention has the following advantages:
Technical scheme of the present invention, at semiconductor substrate surface, form the first hard mask structure, the described first hard mask structure has the bottom surface contacting with described Semiconductor substrate, and wherein, the bottom surface of the described first hard mask structure is positioned at the projection of described cross section on described semiconductor substrate surface.Utilize the described first hard mask structure as mask, adopt the method for dry etching to carry out etching to Semiconductor substrate, form the fin of sidewall slope.Concrete, the section shape of the described first hard mask structure is "T"-shaped, inverted trapezoidal or " ten " font.Semiconductor substrate is being carried out in etching process, and the bottom width of the first hard mask structure determines the width at the final fin top forming.The width of the part that the described first hard mask structure is wider; for example the transverse part at "T"-shaped top is, the width of the transverse part of the top of inverted trapezoidal or " cross " is all greater than the width of bottom surface; in the process of Semiconductor substrate being carried out to etching, can protect the structure of described wider portion bottom, the bottom width of the first hard mask structure is not suffered a loss.
Further, in technical scheme of the present invention, at semiconductor substrate surface, deposit successively from the bottom to top the first hard mask layer and the second hard mask layer, form hard mask structure.After the described first hard mask structure etching, form the first vertical opening of sidewall.Along described the first opening, the first hard mask layer is carried out to further etching again, form the first hard mask structure.In the present embodiment, adopt the method for wet etching to carry out etching to the first hard mask layer.Because the first hard mask layer and the second hard mask layer adopt the material same etching technics to different etching ratios, when the first hard mask layer is carried out to etching, on the not impact of part the second hard mask layer, forming section shape is the first "T"-shaped hard mask structure.Semiconductor substrate is being carried out in the process of etching, the first hard mask structure part the second hard mask layer at the middle and upper levels has protective effect to the 3rd of lower floor the hard mask mask layer.In dry etching process, plasma has higher energy, makes the first hard mask structure have loss.In prior art, general using individual layer mask, and described individual layer mask can be subject to serious damage in plasma etch process, thus the final size of the fin that impact forms, especially, in undersized situation, the impact of the final size of fin is particularly serious; And in technical scheme of the present invention, part second hard mask layer on upper strata is protected the 3rd hard mask layer of lower floor, prevent that it from sustaining damage and affecting the size of the fin of formation in etching process.Because the width of the final fin top width size forming by lower floor's hard mask layer determines, thereby avoided in etching process the impact of the impaired fin size for forming of mask layer.
And, adopt Semiconductor substrate described in the method etching of dry etching, the vertical bombarding semiconductor substrate of plasma adopting, plasma scattering makes part plasma depart from vertical direction, to both sides etching semiconductor substrate.Degree of depth increase along with etching groove, forms the fin with sloped sidewall gradually.Concrete, technical scheme of the present invention is adjusted the slope of the fin sidewall of formation by controlling bias plasma.The energy of adjusting plasma can regulate the speed of etching semiconductor substrate.And can regulate the speed of plasma to Semiconductor substrate bevel etched by controlling etch rate, thereby adjust the slope of fin sidewall.Energy of plasma is larger, and the speed of etching is faster, is scattered the also corresponding raising of energy of the plasma of offset from perpendicular, thereby has increased the etch rate to the Semiconductor substrate of groove both sides, strengthens the slope of the final fin sidewall forming.Technical scheme of the present invention, can also be by regulating the width of the 3rd hard mask layer to regulate the slope of fin sidewall.When the width of the 3rd hard mask layer reduces, after there is scattering between plasma, the isoionic deviation angle of offset from perpendicular also can correspondingly increase, thereby causes the horizontal component of the Semiconductor substrate of groove both sides being carried out to etching to increase, thereby causes the slope of fin sidewall to increase.Adopting surface is the substrate of (100) crystal face, can form the fin sidewall that crystal face is (551), the sidewall slope angle of described (551) crystal face is 82 °, by controlling the parameter of plasma etching, also can form sidewall inclination angle and be the fin of 77 ° ~ 87 °, described fin sidewall approaches (551) crystal face, the atomic arrangement of the sidewall surfaces of described fin more trends towards regularity than the atomic arrangement of other crystal faces, so the sidewall forming is comparatively smooth, defect is less, and the follow-up fin formula field effect transistor performance forming on this fin is also improved.And adopt technical scheme of the present invention to form the sloped sidewall of Different Slope, described sloped sidewall increases the upper opening between adjacent fin, can improve the deposition quality of later stage grid structure, make the fin formula field effect transistor performance of formation more stable; On the other hand, the fin shape that the present invention forms is conducive to the dispersion of stress, so the in the situation that stress strengthening after grid structure on subsequent deposition, still stably remain on substrate surface and do not collapse.Using the described first hard mask structure as mask, only need an etch step just can form the fin of sidewall slope, processing step is simple, and can reduce the damage that multiple etching causes fin surface.
Accompanying drawing explanation
Fig. 1 is the perspective view of the fin field effect pipe of prior art;
Fig. 2 to Fig. 7 is the generalized section that embodiments of the invention form semiconductor structure.
Embodiment
As described in the background art, at present there is leakage current in fin formula field effect transistor, and the problems such as threshold voltage shakiness affect the performance of transistor and integrated circuit.
Through research, find, in fin formula field effect transistor, the interface quality between grid structure and fin is very large for the performance impact of fin formula field effect transistor.Research is found, Si(551) surface and Si(110) surface compares, and more easily makes atomic arrangement neat, and blemish is less, and current driving ability is high.Described Si(551) face of crystal face for tilting, and the fin of sidewall slope is more conducive to the deposition of grid structure, improves interface quality.And the most technical process of fin of prior art formation sloped sidewall is comparatively complicated, need to carry out etching repeatedly to fin, easily fin sidewall be caused to damage.
For addressing the above problem, embodiments of the invention have proposed a kind of formation method of semiconductor structure, using the first hard mask structure of T shape as mask, and Semiconductor substrate is carried out to dry etching, formation has the fin of sloped sidewall, and forms on this basis fin formula field effect transistor.The formation method of described semiconductor structure, processing step is simple, need only one time etching just formed the fin of sidewall slope, reduced the damage to fin surface.
Below in conjunction with accompanying drawing, by specific embodiment, technical scheme of the present invention is carried out to clear, complete description, obviously, described embodiment is only a part for embodiment of the present invention, rather than they are whole.According to described embodiment, those of ordinary skill in the art is obtainable all other execution modes under the prerequisite without creative work, all belong to protection scope of the present invention.
Concrete, please refer to Fig. 2 to Fig. 7, Fig. 2 to Fig. 7 is the generalized section that the present embodiment forms semiconductor structure.
Please refer to Fig. 2, Semiconductor substrate 100 is provided, described substrate surface has mask structure 200.
The material of described Semiconductor substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, can be that body material can be also that composite construction is as silicon-on-insulator.In the present embodiment, Semiconductor substrate 100 is body silicon.Described Semiconductor substrate 100 provides platform for subsequent technique.
In the present embodiment, described hard mask structure 200 has the first hard mask layer 210 and the second hard mask layer 220, and described the first hard mask layer 210 is positioned at substrate surface, and described the second hard mask layer 220 is positioned at the first hard mask layer 210 surfaces.Utilize chemical vapor deposition method, at substrate surface, deposit successively described the first hard mask layer 210 and the second hard mask layer 220.The material of described the first hard mask layer comprises SiO
2, SiN, Si
3n
4or one or more materials in SiON; The material of described the second hard mask layer comprises SiO
2, SiN, Si
3n
4or one or more materials in SiON; And described the first hard mask layer and the second hard mask layer have different selective etching ratios.
In the present embodiment, the material of the first hard mask layer 210 is silicon nitride, and the material of the second hard mask layer 220 is silica.In the present embodiment, the thickness of the first hard mask layer 210 is 500nm ~ 1000nm, and the thickness of the second hard mask layer 220 is 500 ~ 1000nm.
Please refer to Fig. 3, hard mask structure 200(is as shown in Figure 2 described in etching), in described hard mask structure, form the first opening, expose substrate part surface.
Concrete, utilize spin-coating method at described hard mask structure 200(as shown in Figure 2) surface formation photoresist layer, graphical after exposing by development.Utilize graphical photoresist layer as mask, hard mask structure 200 is to Semiconductor substrate 100 surfaces described in etching, and at the interior formation opening of described hard mask structure 200, the upper and lower width of described the first opening is consistent, exposes the part surface of Semiconductor substrate.Opening both sides have part the first hard mask layer 210a and part the second hard mask layer 220a, and described part the second hard mask layer 220a is positioned at part the first hard mask layer 210a upper strata.The position of the first opening that described upper and lower width is consistent defines the groove position between the fin of formation.The technique of the hard mask structure 200 of described etching comprises one or more techniques in photoetching, nano impression, directly self assembly (DSA), dry etching or wet etching.
Please refer to Fig. 4, described in independent etching, part the first hard mask layer 210a(as shown in Figure 3), form the 3rd hard mask layer 210b, make its final width be less than part the second hard mask layer 220a, form the second up-small and down-big opening and the first hard mask structure 230, the described first hard mask structure is "T"-shaped.
The technique that described part the first hard mask layer 210a is carried out to etching is wet etching or dry etching.In the present embodiment, adopt the technique of wet etching to carry out etching to described part the first hard mask layer 210a, form the 3rd hard mask layer 210b, make the width of the 3rd hard mask layer 210b be less than part the second hard mask layer 220a.The part second hard mask layer 220a on described the 3rd hard mask layer 210b and upper strata forms the first hard mask structure 230, and the described first hard mask structure 230 is "T"-shaped, between the described first hard mask structure 230, have the second opening, it is up-small and down-big inverse-T-shaped that described the second opening is.
In embodiments of the invention, because described part the first hard mask layer 210a is different with the material that part the second hard mask layer 220a adopts, so select bi-material to have the etching solution of high etching selection ratio, described etching solution can only carry out etching to part the first hard mask layer 210a.In the present embodiment, the material of part the first hard mask layer 210a is silicon nitride, and the material of part the second hard mask layer 220a is silica, and the etching solution of employing is the phosphoric acid solution of boiling.Because the concentration phosphoric acid solution that is 85% is very slow to the etch rate of silicon dioxide 180 ℃ time, so can be used for doing the selective etch of silicon nitride and silicon dioxide.It is generally 10nm/min to the etch rate of silicon nitride, to the etch rate of silicon dioxide far below 10nm/min.According to the width of the fin end face needing in side circuit, control the width of the 3rd hard mask layer 210b of formation, the width of described the 3rd hard mask layer 210b equals or is slightly larger than the width of the fin end face of final formation.In the present embodiment, the width of described the 3rd hard mask layer 210b is 10nm ~ 30nm.
In an embodiment of the present invention, can select other two kinds of not identical materials to form described part the first hard mask layer 210a and part the second hard mask layer 220a, and according to described two kinds of not identical materials, selection has the etching solution of high selectivity, part the first hard mask layer 210a described in an etching and non-etched portions the second hard mask layer 220a.
In other embodiments of the invention, also can adopt the technique of dry etching.Yet, compare with dry etching, adopt wet-etching technology higher to the Etch selectivity of different materials, be more conducive to form the first hard mask structure of T shape.
In other embodiments of the invention, also can adopt at least one technique in photoetching, nano impression, direct self-assembly method, dry etching or wet etching to form first hard mask structure, between the described first hard mask structure, there is up-small and down-big opening, and the bottom surface of the described first hard mask structure is positioned at the described first projection of hard mask structure on semiconductor substrate surface.The section shape of the described first hard mask structure can also be inverse-T-shaped, " ten " font.
Please refer to Fig. 5, using the first hard mask structure 230 as mask, etching semiconductor substrate 100, the fin 110 of formation sidewall slope.
Concrete, the described first hard mask structure 230 comprises the part second hard mask layer 220a of the 3rd hard mask layer 210b and top thereof.
Adopt dry etch process to carry out etching to described Semiconductor substrate 100.In the present embodiment, the method for using plasma etching, plasma vertically bombards substrate surface with certain energy, and etching is carried out in the region that substrate surface is not covered by the first hard mask structure 230.After plasma enters the opening between the first hard mask structure 230, due to the scattering process between plasma, can make part plasma depart from vertical direction and have horizontal component, most of plasma still carries out etching to Semiconductor substrate in the vertical direction and forms groove simultaneously.In the present embodiment, the bias voltage of plasma etching is 100V ~ 300V, and etch period is 50 seconds ~ 100 seconds.
The plasma of part offset from perpendicular, usings the 3rd hard mask layer 210b as mask, the Semiconductor substrate of etching groove both sides.Along with gash depth is larger, more approach the time that the Semiconductor substrate of the groove both sides of substrate surface is etched longer, the material of Semiconductor substrate is etched manyly, and the width of groove is larger, causes the big up and small down shape of groove.Finally, in the both sides of groove, formed the sidewall of sidewall slope.In the present embodiment, adopting surface is the Semiconductor substrate of (100) crystal face, by controlling the bias voltage of plasma etching and the width and other processes parameter of the 3rd hard mask layer, making the fin sidewall crystal face forming is Si(551), the acute angle angle that sidewall becomes with substrate surface is 82 °.At Si(551 of the present invention) surface smoothness of crystal face compares and is significantly improved with other crystal faces, thereby using Si(551) as the sidewall of fin, can effectively reduce the defect on fin surface.In other embodiments of the invention, can form similar Si(551) sidewall of the fin 110 of crystal face, the acute angle angle that described sidewall becomes with substrate surface is 77 ° ~ 87 °.The acute angle angle becoming with substrate surface except sidewall is that the crystal face of 82 °, the crystal face of described fin sidewall is not (511) face, but approaches (511) face, and evenness just can be slightly poorer than it, but do not have the change of matter.
Further, when fin surface forms grid structure, also can improve the deposition quality of gate dielectric layer and gate electrode and interface quality each other, reduce leakage current, improve the performance of fin formula field effect transistor.
In other embodiments of the invention, can regulate by controlling bias plasma the energy of plasma, thereby regulate the speed of etching semiconductor substrate.And can regulate the speed of plasma to Semiconductor substrate bevel etched by controlling etch rate, thereby adjust the slope of fin 110 sidewalls.Energy of plasma is larger, and the speed of etching is faster, is scattered the also corresponding raising of energy of the plasma of offset from perpendicular, thereby has increased the etch rate to the Semiconductor substrate of groove both sides, strengthens the slope of final fin 110 sidewalls that form.
In other embodiments of the invention, can also be by regulating the width of the 3rd hard mask layer 210b to regulate the slope of fin 110 sidewalls of formation.Reduce the width of the 3rd hard mask layer 210b, the width of the hard mask structure lower middle portion of the corresponding increase of meeting opening.After there is scattering between plasma, the isoionic deviation angle of offset from perpendicular also can correspondingly increase, thereby cause the horizontal component of the Semiconductor substrate of groove both sides being carried out to etching to increase, and the width of the end face of the fin 110 forming is also corresponding the reducing of width of the 3rd hard mask layer 210b, thereby cause the slope of fin 110 sidewalls to increase.
In other embodiment of the present invention, also can adopt the substrate of other crystal faces, form the fin of sidewall slope.Can realize the adjustment to fin sidewall slope degree by controlling the bottom width of the bias voltage of plasma etching and the mask structure of formation, processing step is realized flexibly and easily.
In dry etching process, plasma has higher energy, and hard mask structure can be sustained damage.If adopt the hard mask structure of individual layer as mask, after sustaining damage, change in size can directly affect the shape forming after substrate etching.In the present embodiment, adopt the first double-deck hard mask structure 230; utilize the 3rd hard mask layer 210b of the part second hard mask layer 220a protection lower floor on upper strata; because the width of the final fin top width size forming by the 3rd hard mask layer 210b of lower floor determines; thereby avoided in etching process the impact of the impaired fin size for forming of mask layer.
In other embodiment of the present invention, also can form section shape is the first hard mask structure of inverted trapezoidal or " ten " font.Described section shape is that the width major part of the first hard mask structure of inverted trapezoidal or " ten " font plays a protective role equally to the less part of width of its below, does not suffer a loss in the bottom surface of the first hard mask structure making in the process of etching semiconductor substrate formation fin.
Please refer to Fig. 6, remove the first hard mask structure 230(of semiconductor substrate surface as shown in Figure 5).
The first hard mask structure 230 of removing described semiconductor substrate surface comprises removes described the 3rd hard mask layer 210b(as shown in Figure 5) and part the second hard mask layer 220a(as shown in Figure 5) technique be wet etching.After removing the described first hard mask structure 230, substrate surface only has fin 110.
In the present embodiment, can also on the fin basis with sloped sidewall of described formation, form fin formula field effect transistor.
Please refer to Fig. 7, in described fin 110 side grooves, form insulating barrier 120, described insulating barrier 120 surfaces are lower than the end face of fin; At insulating barrier 120 and fin 110 surfaces, form grid structure, described grid structure is across fin 110 end faces and sidewall; At fin two ends, form source electrode and drain electrode (not shown), described source electrode and drain electrode are positioned at the both sides of grid structure.
Concrete, the material of described insulating barrier 120 is silica or silicon oxynitride, the formation technique of described insulating barrier 120 is that shallow trench is filled.After etching forms the fin 110 of sidewall slope, only remove the part second hard mask layer 220a on upper strata, then deposition of insulative material in groove.First the grooved inner surface in fin 110 both sides grows one deck substrate oxide layer with hot oxygen method, fills afterwards full insulating material with CVD method in groove again.Form described substrate oxide layer and be in order to eliminate etching technics that previous step forms the first fin to the trenched side-wall lattice damage that the first fin sidewall causes, reduce defect.With cmp (CMP) technology, remove the insulating material at fin top, and using the 3rd hard mask layer 210b as grinding stop layer, form smooth surface.Described the 3rd hard mask layer 210b of usining again returns and carves described insulating material as mask, forms insulating barrier 120.Remove again afterwards described the 3rd hard mask layer 210b.
Described grid structure comprises gate dielectric layer 130 and gate electrode layer 140.The material of described gate dielectric layer 130 comprises silica, silicon oxynitride or hafnium.Described gate electrode layer material is polysilicon, metal silicide or metal.Described grid structure is positioned at insulating barrier 120 surface and across described fin 110 end faces and sidewall.Take described grid structure as mask, and the interior doping of fin 110 in described grid structure both sides forms source/drain electrode (not shown).
In embodiments of the invention, adopt the first hard mask structure of double-deck T shape, as mask, substrate is carried out to the fin that etching forms sidewall slope, described fin sidewall approaches (551) crystal face, has atomic arrangement neat, the advantage of surfacing, is conducive to improve the performance of the device that the later stage forms.And the fin of sidewall slope is conducive to carry out in forming fin formula field effect transistor process when shallow trench is filled between adjacent fin, carry out the deposition of insulating material, due to sidewall slope, makes can reduce in deposition process the generation of defect; When forming grid, also contribute to improve the interface quality of contact-making surface, improve transistorized performance.
In embodiments of the invention, can realize the adjustment to fin sidewall slope degree by controlling the bottom width of the bias voltage of plasma etching and the mask structure of formation, processing step is realized flexibly and easily.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (19)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate is provided;
At described semiconductor substrate surface, form the first hard mask structure, the described first hard mask structure has the bottom surface contacting with described Semiconductor substrate, and wherein, described bottom surface is positioned at the described first projection of hard mask structure on semiconductor substrate surface;
Using the described first hard mask structure as mask, etching semiconductor substrate, the fin of formation sidewall slope.
2. the formation method of semiconductor structure according to claim 1, is characterized in that, the section shape of the described first hard mask structure is "T"-shaped, inverted trapezoidal or " ten " font.
3. the formation method of semiconductor structure according to claim 2, is characterized in that, the formation technique of the described first hard mask structure is: at described semiconductor substrate surface, form hard mask layer; In described hard mask layer, form up-small and down-big opening, described opening exposes the part surface of substrate.
4. the formation method of semiconductor structure according to claim 3, is characterized in that, the described technique that forms up-small and down-big opening in hard mask layer is at least one in photoetching, nano impression, direct self-assembly method, dry etching or wet etching.
5. the formation method of semiconductor structure according to claim 3, is characterized in that, described hard mask layer has the second hard mask layer that is positioned at the first hard mask layer of semiconductor substrate surface and is positioned at the first hard mask layer surface; In described the first hard mask layer and the second hard mask layer, form the first opening that exposes Semiconductor substrate, forming section the first hard mask layer and part the second hard mask layer that is positioned at described part the first hard mask layer surface, wherein, part the first hard mask layer is a part for the first mask layer of the first opening both sides, and part the second hard mask layer is a part for the second mask layer of the first opening both sides; Selection makes the first hard mask layer with respect to the second hard mask layer, have the etching technics of high selectivity, and part the first hard mask layer is carried out to etching, makes part the first hard mask layer remove partial width along the first opening, forms the described first hard mask structure.
6. the formation method of semiconductor structure according to claim 5, is characterized in that, the material of described the first hard mask layer and the second hard mask layer is not identical.
7. the formation method of semiconductor structure according to claim 6, is characterized in that, the material of described the first hard mask layer is SiO
2, SiN, Si
3n
4or SiON.
8. the formation method of semiconductor structure according to claim 6, is characterized in that, the material of described the second hard mask layer is SiO
2, SiN, Si
3n
4or SiON.
9. the formation method of semiconductor structure according to claim 5, it is characterized in that, the described first hard mask structure comprises part the second hard mask layer and the 3rd hard mask layer, wherein, the 3rd hard mask layer is for carrying out a part for the first hard mask layer of obtaining after etching to part the first hard mask layer along described the first opening.
10. the formation method of semiconductor structure according to claim 9, is characterized in that, the width range of described the 3rd hard mask layer is 10nm ~ 30nm.
The formation method of 11. semiconductor structures according to claim 9, is characterized in that, the formation technique of described the 3rd hard mask layer is wet etching or dry etching.
The formation method of 12. semiconductor structures according to claim 10, is characterized in that, by controlling the width of described the 3rd hard mask layer, regulates the inclination angle of the sidewall of the fin forming.
The formation method of 13. semiconductor structures according to claim 1, is characterized in that, the technique of described etching semiconductor substrate is dry etching.
The formation method of 14. semiconductor structures according to claim 1, is characterized in that, the technique of described etching semiconductor substrate is plasma etch process, and the bias voltage of described plasma etch process is 100V ~ 300V, and etch period is 50s ~ 100s.
The formation method of 15. semiconductor structures according to claim 14, is characterized in that, by controlling bias voltage and the etch period of described plasma etching, adjusts the inclination angle of the sidewall of the fin forming.
The formation method of 16. semiconductor structures according to claim 1, is characterized in that, the Semiconductor substrate of described employing is the substrate that surperficial crystal face is (100).
The formation method of 17. semiconductor structures according to claim 16, it is characterized in that, the sidewall crystal face of the fin of the sidewall slope of described formation is (551), and sidewall slope angle is 82 °, and described angle of inclination is the acute angle angle that fin sidewall becomes with substrate surface.
The formation method of 18. semiconductor structures according to claim 1, is characterized in that, the sidewall slope angle of the fin of described formation is 77 ° ~ 87 °, and described angle of inclination is the acute angle angle that fin sidewall becomes with substrate surface.
The formation method of 19. semiconductor structures according to claim 1, is characterized in that, also comprises: adopt wet-etching technology to remove the first hard mask structure at fin top; In described fin side grooves, form insulating barrier, described surface of insulating layer is lower than the end face of fin; At insulating barrier and fin surface, form grid structure, described grid structure is across fin end face and sidewall; At fin two ends, form source electrode and drain electrode, described source electrode and drain electrode are positioned at the both sides of grid structure.
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| CN107464745A (en) * | 2016-06-06 | 2017-12-12 | 北大方正集团有限公司 | A kind of preparation method of mask structure and mask structure |
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| US20070167024A1 (en) * | 2006-01-17 | 2007-07-19 | International Business Machines Corporation | Corner clipping for field effect devices |
| CN101303975A (en) * | 2007-05-07 | 2008-11-12 | 台湾积体电路制造股份有限公司 | Fin filled effect transistor and method of forming the same |
| TW201234589A (en) * | 2011-02-09 | 2012-08-16 | United Microelectronics Corp | Fin field-effect transistor structure and manufacturing process thereof |
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| US20070167024A1 (en) * | 2006-01-17 | 2007-07-19 | International Business Machines Corporation | Corner clipping for field effect devices |
| CN101303975A (en) * | 2007-05-07 | 2008-11-12 | 台湾积体电路制造股份有限公司 | Fin filled effect transistor and method of forming the same |
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