CN103187273B - MOS transistor and preparation method thereof - Google Patents
MOS transistor and preparation method thereof Download PDFInfo
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- CN103187273B CN103187273B CN201110459388.8A CN201110459388A CN103187273B CN 103187273 B CN103187273 B CN 103187273B CN 201110459388 A CN201110459388 A CN 201110459388A CN 103187273 B CN103187273 B CN 103187273B
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Abstract
A kind of MOS transistor and preparation method thereof, wherein, the manufacture method of MOS transistor comprises: form grid; Grid is utilized to carry out vertical ion injection for mask; Form side wall; Carry out source and drain ion implantation and form source-drain area; Described vertical ion injects the ion implanted region formed and is positioned at bottom source-drain area and bottom channel region, in step-like distribution, wherein, is positioned at ion implanted region bottom described channel region higher than the ion implanted region be positioned at bottom described source-drain area.The present invention is after grid is formed, the side wall of grid is formed introduces a step vertical ion injection before, this step ion implantation take grid as mask, Semiconductor substrate is carried out to the ion implantation of specific range and given dose, change the substrate doping below raceway groove, but change smaller to the substrate doping below source-drain area.Like this, improve the output resistance of transistor, thus improve the gain of transistor.The impact of such method on mutual conductance and threshold voltage is smaller, and simple.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to and a kind ofly can improve gain but can not the MOS transistor that mutual conductance be affected and preparation method thereof.
Background technology
The gain of metal-oxide-semiconductor is the ratio of the input voltage of output current and this unit.The output AC resistance R of MOSFET
odirectly have influence on the voltage gain K of device
v(K
v=g
mr
o).
In metal-oxide-semiconductor, gate transconductance g
mreflect gate source voltage V
gSto drain current I
dcontrol ability, it is the important parameter characterizing metal-oxide-semiconductor amplifying power.It reflects the low level signal amplification performance of device, be the bigger the better.At drain-source voltage V
dSunder condition for a certain fixed numbers, micro-variable of drain current is called mutual conductance with the ratio of the micro-variable of gate source voltage causing this to change.On the output characteristic curve of MOSFET, gate transconductance g
mfor slope of a curve, reflect the drain current I of MOSFET
dwith gate source voltage V
gSchange and situation about changing.
Gate transconductance g
mwith gain factor β=W μ C of MOSFET
ox/ L is proportional, and namely high transconductance requires large grid breadth length ratio (W/L), high carrier mobility μ and large gate oxide capacitance C
ox(namely large gate insulating film dielectric constant).
The output resistance of MOSFET is the inverse of source-leakage conductance (or drain conductance), can be tried to achieve by the voltage-current characteristic of device.The output voltage-current characteristic of MOSFET belongs to the characteristic of current saturation type, then at the output AC resistance R of linear zone
ojust equal to export D.C. resistance, and resistance value is very little, is inversely proportional to gate source voltage: R simultaneously
o∝ 1/ (V
gS-V
t).And the output AC resistance R in saturation region
owill much larger than output D.C. resistance, ideally R
o=∞, but in fact R
owith channel-length modulation and DIBL effect closely related: R
o∝ 1/L ∝ V
a(L is the long index of modulation of ditch, V
aearly voltage (your sharp voltage).
For long channel device and short channel device, the method that tradition improves the gain of metal-oxide-semiconductor is by thinning gate insulation layer, traditional threshold voltage adjustments ion implantation or electrostatic effect ion implantation.But, for thick gate insulating film is thinning, the parameters such as mutual conductance are significantly increased.
Summary of the invention
The object of the invention is the output resistance being increased MOS transistor by the mode of ion implantation, thus increase the gain of MOS transistor.
For achieving the above object, the present invention proposes a kind of manufacture method of MOS transistor, comprising:
Form grid;
Grid is utilized to carry out vertical ion injection for mask;
Side wall is formed in the both sides of grid;
Carry out source and drain ion implantation and form source-drain area;
Described vertical ion injects the ion implanted region formed and is positioned at bottom source-drain area and bottom channel region, in step-like distribution, wherein, is positioned at ion implanted region bottom described channel region higher than the ion implanted region be positioned at bottom described source-drain area.
Optionally, the energy that described vertical ion injects is 80 ~ 220KeV, and dosage is 1.0E12 ~ 1.0E13atom/cm
2.
Optionally, the ion that described vertical ion injects is:
Pair pmos transistor, injecting ion is the one of As, P;
Pair nmos transistor, injecting ion is B, BF
2, one in In.
Optionally, described after grid is formed, vertical ion also comprises lightly doped drain ion implantation and bag-shaped ion implantation before injecting.
The present invention also comprises a kind of MOS transistor, comprising:
Grid;
Be positioned at the channel region below grid;
Be positioned at the source-drain area of raceway groove both sides;
Be positioned at the ion implanted region bottom channel region and source-drain area, the part that described ion implanted region is positioned at bottom described channel region is step-like higher than it is positioned at the part bottom source-drain area.
Optionally, described MOS transistor is PMOS transistor, and the injection ion of described ion implanted region is the one of As, P.
Optionally, described MOS transistor is nmos pass transistor, and the injection ion of described ion implanted region is B, BF
2, one in In.
The present invention is after grid is formed, the side wall of grid is formed introduces a step vertical ion injection before, this step ion implantation take grid as mask, Semiconductor substrate is carried out to the ion implantation of specific range and given dose, change the substrate doping below raceway groove, but change smaller to the substrate doping doping content below source-drain area.Like this, improve the output resistance of transistor, thus improve the gain of transistor.The impact of such method on mutual conductance and threshold voltage is smaller, and simple.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawing indicates identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on purport of the present invention is shown.
Fig. 1 is schematic diagram MOS transistor being carried out to vertical ion injection.
Fig. 2 for vertical ion shown in Fig. 1 inject after the schematic diagram of ion distribution situation in the transistor.
Fig. 3 is that pair pmos transistor carries out different vertical ion and injects the threshold voltage V caused
twith mutual conductance g
msituation of change.
Embodiment
The present invention is after grid is formed, the side wall of grid is formed introduces a step vertical ion injection before, this step ion implantation take grid as mask, Semiconductor substrate is carried out to the ion implantation of specific range and given dose, change the substrate doping below raceway groove, but change smaller to the substrate doping below source-drain area.Like this, improve the output resistance of transistor, thus improve the gain of transistor.The impact of such method on mutual conductance and threshold voltage is smaller, and simple.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public embodiment.
It should be noted that, provide the object of these accompanying drawings to be contribute to understanding embodiments of the invention, and should not be construed as and limit improperly of the present invention.For the purpose of clearer, size shown in figure not drawn on scale, may do to amplify, to reduce or other change.
As shown in Figure 1, the transistor shown in figure is formed on the substrate 100 vertical ion injection mode of the present invention, and it has formed grid G, but does not also form the side wall of grid, and is reserved with source electrode D region and drain electrode S region.Method of the present invention is that transistor after the gate formation carries out vertical (angle is zero) ion implantation to transistor, because there is the stop of grid G on channel region, so inject just more shallow in channel region, and above source-drain area, there is no mask blocks, thus ion implantation obtains very dark.The ion distribution that ion implantation mode of the present invention is formed as dotted line in Fig. 14 illustrate in step-like distribution, specifically as shown in Figure 2, at the zero point that Fig. 2 is is X-coordinate with the center of grid G, substrate 100 surface location is the zero point of Y-coordinate, at Y=0.08um place, the impurities concentration distribution in X face.Curve 1,2,3 wherein in figure is the result display that three secondary ions inject.Visible in figure, the distribution of formation that three secondary ions inject is all similar: below source-drain area, and the ion distribution of injection is from the distant place of source and drain, and the channel region of side under the gate, the ion distribution of injection just in time side under the channel.The doping of raceway groove can be improved like this, modulating action is played to channel doping (i.e. output resistance), but the raising of channel dopant concentration (i.e. output resistance) does not have influence on the change of the impurity concentration of the substrate under source-drain area, namely do not have influence on junction capacitance and the electric leakage of the substrate under drain region.
It is the one of As, P that pair pmos transistor of the present invention injects ion, and it is B, BF that pair nmos transistor injects ion
2or the one in In, energy range is 80 ~ 220KeV, and implantation dosage is 1.0E12 ~ 1.0E13atom/cm
2(1 × 10
12atom/cm
2~ 1 × 10
13atom/cm
2).
For PMOS transistor, below table 1 for after vertical ion of the present invention that pair pmos transistor carries out different parameters injects, the threshold voltage V that transistor is corresponding
twith mutual conductance g
mvalue.The dosage that following table intermediate ion injects is 2 × 10
12atom/cm
2, implant angle is zero degree (being namely vertical injection with substrate surface), and the ion of injection is As or P.
Table 1
Fig. 3 is threshold voltage V after the different ions drawn according to the value in table 1 is injected according to different-energy
twith mutual conductance g
msituation of change.Wherein, abscissa represents energy, and the ordinate on the left side represents threshold voltage V
t, the ordinate on the right represents mutual conductance g
m, by the expression of Fig. 3, different ions injection parameter significantly can be found out to threshold voltage V
twith mutual conductance g
mimpact.Wherein visible:
For injection As, Implantation Energy greatly about 50 ~ 70KeV time, threshold voltage V
twith mutual conductance g
mchange basically identical; And after Implantation Energy is greater than about about 70KeV, threshold voltage V
twith mutual conductance g
mchange difference start to strengthen, but generally speaking, all to diminish.
For injection P, Implantation Energy greatly about 90 ~ 120KeV time, threshold voltage V
twith mutual conductance g
mchange basically identical; And when other Implantation Energy, threshold voltage V
twith mutual conductance g
mchange difference larger.
And the threshold voltage V that injection P causes
twith mutual conductance g
mchange be greater than and inject As, so for PMOS, preferably injecting ionic type is As.
Describe embodiments of the present invention in detail with the manufacturing process of a concrete PMOS transistor below, and with the difference of other ion implantation step, its processing step comprises:
Step S1, provides Semiconductor substrate;
Step S2, forms shallow groove isolation structure;
Step S3, trap injects;
Step S4, forms grid;
Step S5, low leakage doping/bag-shaped ion implantation;
Step S6, vertical ion injects;
Step S7, side wall is formed;
Step S8, source and drain is injected.
Be embodied as:
Perform step S1, Semiconductor substrate is provided;
Described Semiconductor substrate is preferably body silicon base, also can be germanium silicon substrate, iii-v element compound substrate (as GaAs, indium phosphide, gallium nitride etc.), silicon carbide substrates or its laminated construction, or silicon on insulated substrate, or diamond substrate, or well known to a person skilled in the art other Semiconductor substrate.
Perform step S2, form fleet plough groove isolation structure;
Semiconductor substrate surface is formed with pad oxide, polish stop layer successively, polish stop layer forms photoresist layer.With patterned photoresist layer for mask, etch polish stop layer, pad oxide and semiconductor base successively and form shallow trench, remove photoresist layer afterwards.Utilize chemical vapor deposition method to fill up silica in shallow trench, and carry out cmp to polish stop layer, then place to go polish stop layer forms fleet plough groove isolation structure.
Perform step S3, trap injects: well region ion implantation, channel ion inject, threshold voltage adjustments ion implantation;
Concrete, the ion implantation of this step can divide three steps to carry out, and is respectively: well region ion implantation (WellIMP) district is the bottom being formed at well structure, for the formation of well region; Channel ion injection region forms the partial below with source/drain region to be formed in well structure, for preventing the electric leakage between source/drain region; Threshold voltage ion implanted region is the top layer being formed at well structure, for adjusting threshold voltage.
Also comprise annealing process after ion implantation, described annealing process is: in the inert gas environment such as nitrogen or argon gas, and annealing temperature is 900 DEG C ~ 1070 DEG C, and annealing time is 5s ~ 60s.By the short annealing of this step, while energy activator impurity and elimination ion implantation produce defect, and transient enhanced diffusion (TED) effect and self thermal diffusion can be utilized simultaneously, knot is changed to gradual, can reach and reduce channel surface electric field, suppress the object of hot carrier in jection (HCI) effect.
Perform step S4, form gate insulation layer successively on a semiconductor substrate, form grid;
Carry out oxidation at semiconductor substrate surface and form gate insulation layer, the material of gate insulation layer is silica, and thickness is about
generation type for carry out thermal oxidation in thermal oxidation furnace.
And then polysilicon deposition is carried out on gate insulation layer.The thickness of depositing polysilicon is about
generation type is decomposed for utilizing silane, and the polysilicon deposition of formation is in gate electrode insulation surface.
Spin coating photoresist, photoetching, to form gate patterns on a photoresist, to form the photoresist of gate patterns as mask etching polysilicon layer and gate insulation layer, forms grid.The process of grid being carried out to B ion implantation is also comprised, to adulterate to the grid of polysilicon after having formed grid.
Perform step S5, lightly doped drain/bag-shaped ion implantation;
Along with the width of grid constantly reduces, raceway groove (silicon area between the source and drain) length under grid structure also constantly reduces.The minimizing of the channel length in transistor adds the possibility of electric charge break-through between source and drain, and draws undesirable channel leakage stream.So-called lightly doped drain injects, and referred to before the source-drain area forming metal-oxide-semiconductor, light dope is first done in the drain region of metal-oxide-semiconductor, and then does source-drain area injection.The distance broadened between source-drain area suitable like this, it also reduces the impact of the minimizing of channel length.
During bag-shaped ion implantation with gate dielectric layer and grid for mask, unactivated bag-shaped ion implanted region is formed in Semiconductor substrate, its degree of depth is slightly deeper than the degree of depth of light dope ion implantation, and the ion of described bag-shaped ion implantation is contrary with the ionic conduction type of light dope ion implantation.The object of bag-shaped injection suppresses to cause potential barrier by leakage to reduce the short-channel effect that (DLBL) cause.
Perform step S6, vertical ion injects;
This step is exactly the ion implantation that the present invention increases, in this step, grid has been formed, set the energy of ion implantation to control the range of ion implantation, ensure to be injected under source-drain area at source-drain area ion, and in channel region, the ion be injected into just in time is in below raceway groove.Concrete, for the present embodiment, selecting to inject ion is As, and energy range is 90 ~ 120KeV, and implantation dosage is 1.0E12 ~ 1.0E13 (1 × 10
12atom/cm
2~ 1 × 10
13atom/cm
2), implant angle is zero degree (namely vertical with semiconductor substrate surface).
Perform step S7, side wall is formed;
Side wall is used for around polysilicon gate, prevents the source and drain of larger dose from injecting and too consequently Punchthrough may occur close to raceway groove.The generation type of side wall is that deposit one deck about
silicon dioxide, this layer of silicon dioxide is used for forming side wall in the surrounding of polysilicon gate, then utilizes dry etch process to anti-carve most of silicon dioxide, only on the side wall of polysilicon gate, leaves layer of silicon dioxide.
Perform step S8, source and drain ion implantation;
Using photoresist and grid as mask, ion implantation is carried out to Semiconductor substrate, forms self aligned source-drain area.In order to complete down doping techniques, with the doping of the median dose junction depth slightly exceeding LDD, but the well depth formed than well region doping is shallow.The side wall that previous step is formed can protect raceway groove, stops entering of foreign atom in injection process.The energy injection degree of depth that enters silicon can be greater than the junction depth of LDD in this step, the side wall that silicon dioxide is formed prevents arsenic impurities to invade narrow channel region.
Also comprise annealing process after source and drain ion implantation, described annealing process is: in the inert gas environment such as nitrogen or argon gas, and annealing temperature is 900 DEG C ~ 1070 DEG C, and annealing time is 5s ~ 60s.By the short annealing of this step, while energy activator impurity and elimination ion implantation produce defect, and transient enhanced diffusion (TED) effect and self thermal diffusion can be utilized simultaneously, knot is changed to gradual, can reach and reduce channel surface electric field, suppress the object of hot carrier in jection (HCI) effect.
Through comprising the PMOS transistor that above-mentioned technique is formed, there is larger output resistance, namely can have larger gain.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Any those of ordinary skill in the art, are not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (5)
1. a manufacture method for MOS transistor, is characterized in that, comprising:
Form grid;
Grid is utilized to carry out vertical ion injection for mask;
Side wall is formed in the both sides of grid;
Carry out source and drain ion implantation and form source-drain area;
Control the range of ion implantation, ensure that the position of ion implantation is as follows: described vertical ion injects the ion implanted region formed and is positioned at below source-drain area and below channel region, in step-like distribution, wherein, described ion implanted region is positioned at the bottom of the part below described channel region lower than source-drain area, and described ion implanted region is positioned at part below described channel region and is positioned at part below described source-drain area higher than it;
The ion that described vertical ion injects is: pair pmos transistor, and injecting ion is the one of As, P; Pair nmos transistor, injecting ion is B, BF
2, one in In.
2. manufacture method as claimed in claim 1, is characterized in that, the energy that described vertical ion injects is 80 ~ 220KeV, and dosage is 1.0E12 ~ 1.0E13atom/cm
2.
3. manufacture method as claimed in claim 1, is characterized in that, after described grid is formed, vertical ion also comprises lightly doped drain ion implantation and bag-shaped ion implantation before injecting.
4. a MOS transistor, is characterized in that, comprising:
Grid;
Be positioned at the channel region below grid;
Be positioned at the source-drain area of raceway groove both sides;
Be positioned at below channel region with source-drain area below ion implanted region, in step-like distribution, described ion implanted region is positioned at the bottom of the part below described channel region lower than source-drain area, and described ion implanted region is positioned at part below described channel region and is positioned at part below source-drain area higher than it;
Described MOS transistor is PMOS transistor, and the injection ion of described ion implanted region is the one of As, P.
5. a MOS transistor, is characterized in that, comprising:
Grid;
Be positioned at the channel region below grid;
Be positioned at the source-drain area of raceway groove both sides;
Be positioned at below channel region with source-drain area below ion implanted region, in step-like distribution, described ion implanted region is positioned at the bottom of the part below described channel region lower than source-drain area, and described ion implanted region is positioned at part below described channel region and is positioned at part below source-drain area higher than it;
Described MOS transistor is nmos pass transistor, and the injection ion of described ion implanted region is B, BF
2, one in In.
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|---|---|---|---|
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|---|---|---|---|
| CN201110459388.8A CN103187273B (en) | 2011-12-31 | 2011-12-31 | MOS transistor and preparation method thereof |
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| CN103187273B true CN103187273B (en) | 2016-04-20 |
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| US5543654A (en) * | 1992-01-28 | 1996-08-06 | Thunderbird Technologies, Inc. | Contoured-tub fermi-threshold field effect transistor and method of forming same |
| US5888873A (en) * | 1996-11-06 | 1999-03-30 | Advanced Micro Devices, Inc. | Method of manufacturing short channel MOS devices |
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| US6534402B1 (en) * | 2001-11-01 | 2003-03-18 | Winbond Electronics Corp. | Method of fabricating self-aligned silicide |
| CN101752254B (en) * | 2008-12-22 | 2012-12-19 | 中芯国际集成电路制造(上海)有限公司 | Ion implantation zone forming method, MOS transistor and manufacture method thereof |
| CN101783299B (en) * | 2009-01-20 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | MOS (Metal Oxide Semiconductor) formation method and threshold voltage adjustment method thereof |
| CN101840861A (en) * | 2009-03-16 | 2010-09-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN101894758A (en) * | 2009-05-19 | 2010-11-24 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for increasing gains of MOS pipe |
| US8299545B2 (en) * | 2010-01-28 | 2012-10-30 | International Business Machines Corporation | Method and structure to improve body effect and junction capacitance |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5543654A (en) * | 1992-01-28 | 1996-08-06 | Thunderbird Technologies, Inc. | Contoured-tub fermi-threshold field effect transistor and method of forming same |
| US5888873A (en) * | 1996-11-06 | 1999-03-30 | Advanced Micro Devices, Inc. | Method of manufacturing short channel MOS devices |
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