CN103187224B - A kind of slide holder for plasma processing apparatus - Google Patents
A kind of slide holder for plasma processing apparatus Download PDFInfo
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- CN103187224B CN103187224B CN201110456419.4A CN201110456419A CN103187224B CN 103187224 B CN103187224 B CN 103187224B CN 201110456419 A CN201110456419 A CN 201110456419A CN 103187224 B CN103187224 B CN 103187224B
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Abstract
The invention provides slide holder and comprise the plasma processor platform of this slide holder, wherein, described substrate is positioned at above described slide holder, described slide holder comprises: the first electrode, it is connected with the radio-frequency power supply with first frequency, for generation of plasma, be wherein provided with one or more vacuum cavity; Electrostatic chuck, it is positioned at above described first electrode, for clamping substrate.The present invention can improve substrate process uniformity.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of slide holder for plasma processing apparatus.
Background technology
The edge effect of semiconductor arts piece is a problem of puzzlement semiconductor industry.The edge effect of so-called semiconductor arts piece refers in plasma treatment procedure, because plasma is by electric field controls, and the field intensity of the two poles of the earth edge can by the impact of rim condition up and down, some electric field line total bends, and cause Electric field edge part field intensity uneven, and then cause the plasma density of this part uneven.In that case, also there is a circle around the semiconductor arts piece produced and process uneven region.This non-uniform phenomenon is more obvious when rf electric field frequency is higher, and the inhomogeneities degree being greater than this plasma concentration when 60MHZ is even greater than 100Mhz at rf frequency is difficult to regulate and control with the gathering ring of other device as being positioned at electrostatic chuck edge again.
Because semiconductor arts piece is circular, therefore more outer ring area is larger, and the not good rate of finished products that will cause of the homogeneity of each process procedure of marginal portion significantly declines.Generally adopting today of 300mm processing procedure, the loss that semiconductor arts piece edge effect brings is more huge.
Therefore, need in the industry to improve edge effect simply and effectively, improve process uniformity.
Summary of the invention
For the problems referred to above in background technology, the present invention proposes the slide holder for plasma processing apparatus that can improve homogeneity.
First aspect present invention provides a kind of slide holder for carrying substrates being applied to plasma processing apparatus, and wherein, described substrate is positioned at above described slide holder, it is characterized in that, described slide holder comprises:
First electrode, it is connected with the radio-frequency power supply with first frequency, for generation of plasma, is wherein provided with one or more vacuum cavity;
Electrostatic chuck, it is positioned at above described first electrode, for clamping substrate.
Alternatively, described one or more vacuum cavity is arranged in described first electrode below corresponding to described substrate center region.
Alternatively, described one or more vacuum cavity is arranged at respectively corresponding to described substrate center region and fringe region, and in described first electrode of zone line between described middle section and described fringe region.
Wherein, described identical with the volume in described one or more vacuum cavities corresponding to described substrate zone line corresponding to one or more vacuum cavity in described substrate center region.
Further, the described one or more cavity corresponding to substrate center region is connected with the described one or more cavities corresponding to substrate zone line, and one-tenth is integrated.
Wherein, the described volume corresponding to one or more vacuum cavities in described substrate center region is greater than the described volume corresponding to one or more vacuum cavities of described substrate zone line.
Further, the described one or more cavity corresponding to substrate center region is connected with the described one or more cavities corresponding to substrate zone line, and one-tenth is integrated.
Further, described first electrode at least comprises the first area corresponding to substrate center region, corresponding to the 3rd region in substrate edge region, and the second area between described first area and described 3rd region,
Wherein, described plasma processing apparatus also comprises:
Drive unit, its for drive alternatively described first area, second area and the 3rd region one of them to carry out in vertical direction flexible.
Further, described drive unit drives described first area and second area to carry out stretching in vertical direction alternatively.
Further, the volume being positioned at the vacuum cavity of described first area of flexible generation that described first area is carried out in vertical direction is greater than the volume being positioned at the vacuum cavity of described second area that described second area carries out the flexible generation in vertical direction.
Further, the volume being positioned at the vacuum cavity of described first area of flexible generation that described first area is carried out in vertical direction equals the volume being positioned at the vacuum cavity of described second area that described second area carries out the flexible generation in vertical direction.
Further, described drive unit comprises electric machine, hydraulic means, pneumatic shuttle.
Further, described first frequency is more than 13M hertz.
Further, described substrate is semiconductor chip,
Wherein, described electrostatic chuck at least comprises:
First dielectric layer;
Second dielectric layer, it is positioned at above described first dielectric layer, and is embedded with the electrode for generation of electrostatic attraction.
Further, described substrate is glass substrate, and wherein, described electrostatic chuck at least comprises one first dielectric layer.
Second aspect present invention provides a kind of plasma processing apparatus, it is characterized in that, comprises the slide holder described in first aspect present invention.
Further, described first frequency is more than 13M hertz.
Further, described substrate is semiconductor chip,
Wherein, described electrostatic chuck at least comprises:
First dielectric layer;
Second dielectric layer, it is positioned at above described first dielectric layer, and is embedded with the electrode for generation of electrostatic attraction.
Further, described substrate is glass substrate, and wherein, described electrostatic chuck at least comprises one first dielectric layer.
Slide holder provided by the invention and the plasma processing apparatus comprising this slide holder can improve edge effect simply and effectively, improve process uniformity.
Accompanying drawing explanation
Fig. 1 is the slide holder structural representation of the vacuum treatment installation of the first specific embodiment of the present invention;
Fig. 2 is that the present invention carries out the schematic diagram of Region dividing to substrate;
Fig. 3 is the slide holder structural representation of the vacuum treatment installation of the second specific embodiment of the present invention;
Fig. 4 is the slide holder structural representation of the vacuum treatment installation of the 3rd specific embodiment of the present invention;
Fig. 5 is the slide holder structural representation of the vacuum treatment installation of the 4th specific embodiment of the present invention;
Fig. 6 is the slide holder structural representation of the vacuum treatment installation of the 5th specific embodiment of the present invention;
Fig. 7 is the slide holder structural representation of the vacuum treatment installation of the 6th specific embodiment of the present invention;
Fig. 8 is the structural representation of SOG;
Fig. 9 is that SOG is heated the structural representation of rear surface projection;
Figure 10 is invention effect schematic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described.
The present invention is by being divided into multiple region by the bottom electrode at vacuum treatment installation, and produce one or more cavity at the diverse location corresponding to substrate, change the dielectric constant of equivalent capacity between described bottom electrode and substrate lower surface, thus change the size of described equivalent capacity further, to realize being optimized the process uniformity of substrate.
Fig. 1 is the slide holder structural representation of the vacuum treatment installation of the present invention's specific embodiment.Hereafter by describe specific embodiment in, described vacuum treatment installation is etching machine bench especially.As shown in Figure 1, the invention provides a kind of slide holder 1 for carrying substrates W being applied to plasma processing apparatus, wherein, described substrate typically is a silicon chip, and described silicon chip W is positioned at above described slide holder 1, and described slide holder 1 comprises:
First electrode 13, described first electrode 13 is connected with the radio-frequency power supply 15 with first frequency f.It should be noted that, also comprise a second electrode (not shown) parallel with described first electrode 13 in etching machine bench chamber upper part, both combine the plasma for generation of processing procedure, to carry out etching processing to described substrate W.Wherein, described first electrode 13 is provided with one or more vacuum cavity.Hereafter explain to the vacuum cavity wherein arranged in detail.
Wherein, described first electrode 13 is by electrical conductor material processing procedure, especially, can be made up of metallic aluminium.
Electrostatic chuck, it is positioned at above described first electrode 13, for clamping substrate W.Also there is an electrostatic chuck chassis 16 (ESC base plate) below electrostatic chuck.
Fig. 2 is that the present invention carries out the schematic diagram of Region dividing to substrate.As shown in Figure 2, it illustrates the vertical view of the substrate of a horizontal positioned, described substrate is discoidal, with the center of circle of discoidal substrate for starting point, the circular portion being positioned at middle section is set as the middle section C ' of substrate, be positioned at the zone line M ' that the peripheral circular annular region of described middle section C ' is set as substrate, be positioned at the fringe region E ' that the peripheral circle ring area of described zone line M ' is set as substrate.By reference to the accompanying drawings 1, in the first dielectric layer 14 in electrostatic chuck, region corresponding to the middle section C ' of described substrate W is middle section C1, region corresponding to the zone line M ' of described substrate W is zone line M1, and the region corresponding to the fringe region E ' of substrate W is fringe region E1.
In the present embodiment, in order to more concisely technological invention mechanism of the present invention is described easily, need to carry out Region dividing to substrate.It should be noted that, the Region dividing carried out substrate is in the present embodiment not in esse, but the present invention and the virtual grate that substrate is carried out for convenience of description, can not in order to limit the present invention.
Be to be understood that, because the division of above-mentioned zone is not in the present embodiment in esse, so, according to technique needs, can adjust arbitrarily the division of above-mentioned zone, such as, the Region dividing corresponding to substrate region that etching rate can be reduced to a certain degree is fringe region, and not must divide according to digital scope.
Original thinking of the present invention changes semiconductor arts piece fringe field density by changing parasitic capacitance between cavity and top electrode, and semiconductor arts piece edge effect improves.That is the electric field redistribution by regulating the parasitic capacitance between edge plasma and cavity can make semiconductor arts piece edge.In general, affect this parasitic capacitance value because have three, i.e. the relative area of top electrode edge and cavity, the distance between top electrode edge and cavity, and edge plasma and cavity form the effective dielectric constant in space.Plasma treatment chamber is once make, clearly, its top electrode edge and the relative area of cavity and the distance between them are fixing, and the Relationship Comparison of parasitic capacitance and Electric Field Distribution is complicated, different radio-frequency (RF) energy inputs also can affect this relation, and consider technologic feasibility, it is very difficult for precalculating and producing the vacuum reaction chamber with suitable size parasitic capacitance.
Therefore, what uniquely likely change is exactly the effective dielectric constant of plasma and cavity space.The present invention is based on such consideration, the effective dielectric constant in this space is regulated and obtains a suitable parasitic capacitance, make electric field redistribution, and then make semiconductor arts piece plasma treatment effect homogeneous.
As shown in Figure 1, in a preferred embodiment of the invention, described one or more vacuum cavity is arranged in described first electrode 13 below corresponding to described substrate W middle section, that is, as illustrated first empty H11.The first electrode 13 and substrate W is regarded as three equivalent capacity Cc, Cm, Ce respectively according to middle section C1, zone line M1 and fringe region E1, wherein namely the first dielectric layer 14 of electrostatic chuck act as this equivalent capacity medium wherein with the cavity that may be positioned at above the first electrode 13, therefore, according to capacitance equation:
C=ε S/4 π kd, wherein, ε is dielectric constant, and d is distance.
Thus, due in the present embodiment, owing to empty H11 being arranged in the middle section C1 of the first electrode 13 easily produced below the higher middle section of etch rate, make the dielectric in middle section C1 compared with the zone line M1 of its periphery and the dielectric of fringe region E1 few, namely, the dielectric constant of the equivalent capacity Cc of middle section C1 reduces, and then described equivalent capacity Cc is reduced, thus make the radio frequency source 15 be connected on the first electrode 13 can arrive the minimizing of substrate center region C1 further, the plasma quantity making the substrate center area unit time produce thus reduces, thus the interaction liveness between the plasma of generation and substrate is reduced, the etch rate in the described substrate center region of final reduction, to realize being optimized the process uniformity of substrate.
Wherein, described one or more vacuum cavity also can be arranged at respectively corresponding to described substrate center region and fringe region, and in described first electrode of zone line between described middle section and described fringe region.
Alternatively, the one or more vacuum cavities be arranged at described in corresponding to described substrate center region are identical with the described volume be arranged at corresponding to one or more vacuum cavities of described substrate zone line.With reference to Fig. 3, in the present embodiment, the volume of H21 equals the volume of H22, then can reduce the etch rate of substrate W middle section C ' and zone line M ' thus, the etch rate of substrate W fringe region E is in a disguised form compensated, improves the edge effect of substrate W.
Wherein, the described one or more empty H21 corresponding to substrate center region is connected with the described one or more empty H22 corresponding to substrate zone line, and one-tenth is integrated.
Alternatively, the volume in the one or more vacuum cavities corresponding to described substrate zone line is arranged at described in the volume be arranged at described in corresponding to one or more vacuum cavities in described substrate center region is greater than.As shown in Figure 4, in the present embodiment, the volume of H31 is greater than the volume of H32, then progressively can adjust according to middle section C ', middle M ' and fringe region E ' respectively the etch rate of silicon chip W thus.Particularly, because the volume of the vacuum cavity H31 being arranged in middle section C is maximum, then the etch rate corresponding to the middle section C ' of silicon chip W is lowered at most.Secondly, because the volume of the vacuum cavity H32 being positioned at zone line M1 is less than described vacuum cavity H31, the etch rate then corresponding to the zone line M ' of silicon chip W have also been obtained reduction, but it must reduce the etch rate of amplitude lower than the middle section C ' corresponding to silicon chip W.Again, the fringe region E due to the fringe region E ' corresponding to silicon chip W in the present embodiment does not arrange any vacuum cavity, and its etch rate does not carry out any adjustment.Therefore, above-mentioned control makes the etch rate corresponding to silicon chip W middle section C ' minimum, the a little higher than described etch rate corresponding to silicon chip W middle section C ' of etch rate corresponding to the zone line M ' of silicon chip W, and the etch rate corresponding to the fringe region E ' of silicon chip W is the highest.Edge effect compensates thus, optimizes process uniformity further.
The described one or more empty H31 corresponding to substrate center region is connected with the described one or more empty H32 corresponding to substrate zone line, and one-tenth is integrated.
It should be noted that, it will be appreciated by those skilled in the art that, the present invention also comprises some change case to above-described embodiment, such as, the region that region, zone line, fringe region can be entreated in the substrate corresponding all arranges one or more cavity, as long as the etch rate realizing middle section is minimum, zone line secondly, the most higher position of fringe region can compensate etched edge effect, thus realizes goal of the invention.
See accompanying drawing 5 ~ Fig. 7, according to a change case of above-described embodiment, described first electrode at least comprises the first area corresponding to substrate center region, corresponding to the 3rd region in substrate edge region, and the second area between described first area and described 3rd region.Wherein, described plasma processing apparatus also comprises: drive unit 18, it is flexible that it carries out in vertical direction for one of them driving described first area C2, second area M2 and the 3rd region E2 alternatively, thus produce one or more cavity in above-mentioned zone in described first electrode 13.The present invention needs different configuration modes to above-mentioned one or more vacuum cavity according to different technique, will specifically tell about hereinafter.
Further, in the present invention's specific embodiment, described drive unit 18 drives described first area C and second area M to carry out stretching in vertical direction alternatively.
As shown in Figure 5, described drive unit 18 can be selected to drive first area C ' to carry out stretching in vertical direction by choice device 17, thus produces the first empty H41 in corresponding to described first electrode 13 below silicon chip W middle section.Due in the present embodiment, cavity H41 is arranged in the first area C of the first electrode 13 easily produced below the higher middle section of etch rate, make the dielectric in the C of first area compared with the second area M2 of its periphery and the dielectric of the 3rd region E2 few, namely, the dielectric constant of the equivalent capacity Cc of first area C reduces, and then described equivalent capacity Cc is reduced, thus the radio-frequency (RF) energy making the radio frequency source 15 be connected on the first electrode 13 can arrive substrate first area C2 reduces, the plasma quantity making the substrate center area unit time produce thus reduces, the etch rate in the described substrate center region of final reduction, to improve the edge effect of silicon chip W, thus the interaction liveness between the plasma of generation and substrate is reduced, realize being optimized the process uniformity of silicon chip.
Alternatively, the volume being positioned at the vacuum cavity of described first area C2 of flexible generation that described first area C2 carries out in vertical direction equals the volume being positioned at the vacuum cavity of described second area M2 that described second area M2 carries out the flexible generation in vertical direction.With reference to Fig. 6, in the present embodiment, the volume of H51 equals the volume of H52, then can reduce the etch rate of silicon chip W middle section C ' and zone line M ' thus, the etch rate of silicon chip W fringe region E2 is in a disguised form compensated, improves the edge effect of silicon chip W.
The one or more empty H51 of the described wafer center region C ' of corresponding to is connected with the described one or more empty H52 corresponding to silicon chip zone line M ', and one-tenth is integrated.
Alternatively, the volume being positioned at the vacuum cavity of described first area C2 of flexible generation that described first area C2 carries out in vertical direction is greater than the volume being positioned at the vacuum cavity of described second area M2 that described second area M2 carries out the flexible generation in vertical direction.As shown in Figure 7, in the present embodiment, the volume of H61 is greater than the volume of H62, then progressively can adjust according to middle section, centre and fringe region respectively the etch rate of silicon chip W thus.Particularly, because the volume of the vacuum cavity H61 being arranged in first area C2 is maximum, then the etch rate corresponding to the middle section C ' of silicon chip W is lowered at most.Secondly, because the volume of the vacuum cavity H32 being positioned at second area M2 is less than described vacuum cavity H61, the etch rate then corresponding to the zone line M ' of silicon chip W have also been obtained reduction, but it must reduce the etch rate of amplitude lower than the middle section C ' corresponding to silicon chip W.Again, the 3rd region E2 due to the fringe region E ' corresponding to silicon chip W in the present embodiment does not arrange any vacuum cavity, and its etch rate does not carry out any adjustment.Therefore, above-mentioned control makes the etch rate corresponding to silicon chip W middle section C ' minimum, the a little higher than described etch rate corresponding to silicon chip W middle section C ' of etch rate corresponding to the zone line M ' of silicon chip W, and the etch rate corresponding to the fringe region E ' of silicon chip W is the highest.Edge effect compensates thus, optimizes process uniformity further.
Wherein, the one or more empty H61 of the described wafer center region C ' of corresponding to is connected with the described one or more empty H62 corresponding to silicon chip zone line M ', and one-tenth is integrated.
Embodiment shown in Fig. 7 is a change case of Fig. 5, its difference is, the volume being positioned at the vacuum cavity H61 of described first area C of the flexible generation that described first area C carries out in vertical direction is greater than the volume being positioned at the vacuum cavity H62 of described second area M that described second area M carries out the flexible generation in vertical direction.
Wherein, described drive unit comprises electric machine, hydraulic means, pneumatic shuttle.Exemplarily, as shown in Fig. 5 ~ Fig. 7, described drive unit further comprises lifting device 19a and 19b, wherein, described lifting device 19a carries out stretching and the vacuum cavity being positioned at described first area produced in vertical direction for described first area, described lifting device 19a carries out stretching and the vacuum cavity being positioned at described second area produced in vertical direction for described second area.Electric machine, hydraulic means, pneumatic shuttle is comprised for driving the drive unit of described lifting device 19a and 19b.
In embodiment mentioned above, described substrate is all semiconductor chip, because semiconductor chip needs to clamp with electrostatic attraction.So shown in accompanying drawing 1,3,6 ~ 8, described electrostatic chuck at least comprises: the first dielectric layer 14; Second dielectric layer 11, it is positioned at above described first dielectric layer 14, and is embedded with the electrode 12 for generation of electrostatic attraction.
According to a change case, described substrate is glass substrate (glass wafer).Be to be understood that, a kind of underlying structure conventional in semiconductor manufacturing is included in structure (semiconductor on insulation insulator substrates with semi-conducting material, SOI), this structure is being usually used in manufacturing high performance thin-film transistor, the display of solar cell and Active Matrix Display and so on and other devices after Subsequent semiconductor PROCESS FOR TREATMENT or micro Process.A kind of concrete structure of soi structure is SOG (silicon on glass) structure, and namely isolate supports material structure, is also referred to as glass substrate, is known as the basis of " 21st century silicon integrated circuit technology " in the world.It can break through many restrictions of body silicon materials, has broad application prospects in many-sides such as space industry, optoelectronic areas and micro mechanical systems.
For SOG structure, glass substrate is described below, Fig. 8 shows the structural representation of SOG, as shown in Figure 1, SOG structure mainly comprises three-decker from top to bottom: glass substrate layer 20, adhesion substance layer etc., its for serve as described glass substrate layer 20 and silicon layer 22 in conjunction with material layer.Further, the method obtaining SOG structure comprises and utilizes pressure, temperature (typically being 150 degrees Celsius) and voltage to be applied to silicon layer 22 and glass substrate 20 with promotion joint therebetween.
It can thus be appreciated that, prior art is mainly through applying uniform temperature (such as, higher than normal temperature) promote the joint of semi-conducting material and insulator substrates thus make soi structure, but normal temperature state can be cooled to after soi structure is made, because the thermal coefficient of expansion of wherein each kind of material is different, semiconductor material layer (silicon layer 22 as Fig. 1) can be distorted or displacement at in-plane, make the soi structure out-of-flatness on the whole obtained, Fig. 9 shows soi structure surface and occurs irregular situation.As shown in Figure 2, due to the difference of the thermal coefficient of expansion of normal temperature lower ply of glass 20 ' and silicon layer 22 ', cause the glassy layer 20 ' of described silicon layer 22 ' surface and bottom to present on the whole gently protruding, described in be raised in general 0.5mm ~ 1mm of horizontal plane or more.Therefore, carrying out processing procedure to glass substrate does not normally need electrostatic attraction to be fixed on slide holder, but adopts specific device to apply a power from top to glass substrate and fix.
Therefore, in the embodiment of glass substrate, electrostatic chuck (not shown) only comprises one first dielectric layer 14, and without the need to comprising the second dielectric layer 11 and electrode 12 disposed therein again.
Further, described first frequency f is more than 13M hertz, preferably more than 60Mhz, and it is to 100Mhz.
Present invention also offers a kind of plasma processing apparatus, it is characterized in that, comprise aforesaid slide holder.
Wherein, described first frequency is more than 13M hertz.
With reference to Figure 10, it for initial point, with the diameter of silicon chip for transverse axis, is that Y-axis determines a reference axis with etch rate with the center of circle of silicon chip.Wherein, S1 is the etch rate curve of silicon chip that the slide holder of application prior art obtains, visible, and its middle section etch rate around the center of circle is higher, and region etch speed decreases therebetween, minimum at the etch rate of its fringe region.S2 and S3 is corresponding to the etch rate curve applying the silicon chip that slide holder provided by the invention obtains.Wherein, S2 only corresponds to wafer center region and implements the present invention, and the etch rate of its middle section is significantly reduced as seen.S3 implements the present invention to wafer center region and zone line, and the etch rate of its middle section and zone line is obtained for reduction.Describe superiority of the present invention thus, the present invention effectively can improve edge effect fast with low power, realizes processing procedure homogenization.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (18)
1. be applied to the slide holder for carrying substrates of plasma processing apparatus, wherein, described substrate is positioned at above described slide holder, it is characterized in that, described slide holder comprises:
First electrode, it is connected with the radio-frequency power supply with first frequency, for generation of plasma, is wherein provided with one or more vacuum cavity;
Electrostatic chuck, it is positioned at above described first electrode, for clamping substrate;
Described first electrode at least comprises the first area corresponding to substrate center region, corresponding to the 3rd region in substrate edge region, and the second area between described first area and described 3rd region;
Wherein, described plasma processing apparatus also comprises:
Drive unit, its for drive alternatively described first area, second area and the 3rd region one of them to carry out in vertical direction flexible.
2. slide holder according to claim 1, is characterized in that, described one or more vacuum cavity is arranged in described first electrode below corresponding to described substrate center region.
3. slide holder according to claim 1, it is characterized in that, described one or more vacuum cavity is arranged at respectively corresponding to described substrate center region and fringe region, and in described first electrode of zone line between described middle section and described fringe region.
4. slide holder according to claim 3, is characterized in that, described identical with the volume in described one or more vacuum cavities corresponding to described substrate zone line corresponding to one or more vacuum cavity in described substrate center region.
5. slide holder according to claim 4, is characterized in that, the described one or more cavity corresponding to substrate center region is connected with the described one or more cavities corresponding to substrate zone line, and one-tenth is integrated.
6. slide holder according to claim 3, is characterized in that, the described volume corresponding to one or more vacuum cavities in described substrate center region is greater than the described volume corresponding to one or more vacuum cavities of described substrate zone line.
7. slide holder according to claim 6, is characterized in that, the described one or more cavity corresponding to substrate center region is connected with the described one or more cavities corresponding to substrate zone line, and one-tenth is integrated.
8. slide holder according to claim 1, is characterized in that, described drive unit drives described first area and second area to carry out stretching in vertical direction alternatively.
9. slide holder according to claim 8, it is characterized in that, the volume being positioned at the vacuum cavity of described first area of the flexible generation that described first area is carried out in vertical direction is greater than the volume being positioned at the vacuum cavity of described second area that described second area carries out the flexible generation in vertical direction.
10. slide holder according to claim 8, it is characterized in that, the volume being positioned at the vacuum cavity of described first area of the flexible generation that described first area is carried out in vertical direction equals the volume being positioned at the vacuum cavity of described second area that described second area carries out the flexible generation in vertical direction.
11. slide holders according to claim 1, is characterized in that, described drive unit comprises electric machine, hydraulic means, pneumatic shuttle.
12. slide holders according to any one of claim 1 to 11, it is characterized in that, described first frequency is more than 13M hertz.
13. slide holders according to claim 12, is characterized in that, described substrate is semiconductor chip, and wherein, described electrostatic chuck at least comprises:
First dielectric layer;
Second dielectric layer, it is positioned at above described first dielectric layer, and is embedded with the electrode for generation of electrostatic attraction.
14. slide holders according to claim 12, is characterized in that, described substrate is glass substrate, and wherein, described electrostatic chuck at least comprises one first dielectric layer.
15. 1 kinds of plasma processing apparatus, is characterized in that, comprise the slide holder described in any one of claim 1 to 11.
16. plasma processing apparatus according to claim 15, is characterized in that, described first frequency is more than 13M hertz.
17. plasma processing apparatus according to claim 15, is characterized in that, described substrate is semiconductor chip,
Wherein, described electrostatic chuck at least comprises:
First dielectric layer;
Second dielectric layer, it is positioned at above described first dielectric layer, and is embedded with the electrode for generation of electrostatic attraction.
18. plasma processing apparatus according to claim 15, is characterized in that, described substrate is glass substrate, and wherein, described electrostatic chuck at least comprises one first dielectric layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110456419.4A CN103187224B (en) | 2011-12-30 | 2011-12-30 | A kind of slide holder for plasma processing apparatus |
| TW101143731A TW201332054A (en) | 2011-12-30 | 2012-11-22 | Substrate sustaining platform for plasma processing apparatus |
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| CN201110456419.4A CN103187224B (en) | 2011-12-30 | 2011-12-30 | A kind of slide holder for plasma processing apparatus |
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| CN103187224B true CN103187224B (en) | 2015-09-09 |
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| CN101278368A (en) * | 2005-09-30 | 2008-10-01 | 朗姆研究公司 | Electrostatic chuck assembly with dielectric material and/or cavity having varying thickness, profile and/or shape, method of use and apparatus incorporating same |
| CN102110573A (en) * | 2009-12-28 | 2011-06-29 | 东京毅力科创株式会社 | Plasma processing apparatus |
| CN201751976U (en) * | 2010-03-12 | 2011-02-23 | 中微半导体设备(上海)有限公司 | Processing device with plasma |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI484590B (en) | 2015-05-11 |
| CN103187224A (en) | 2013-07-03 |
| TW201332054A (en) | 2013-08-01 |
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Address after: 201201 No. 188 Taihua Road, Jinqiao Export Processing Zone, Pudong New Area, Shanghai Patentee after: Medium and Micro Semiconductor Equipment (Shanghai) Co., Ltd. Address before: 201201 No. 188 Taihua Road, Jinqiao Export Processing Zone, Pudong New Area, Shanghai Patentee before: Advanced Micro-Fabrication Equipment (Shanghai) Inc. |
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