CN103186691A - Independent double-grid FinFET channel potential distribution analysis model - Google Patents

Abstract

The invention provides an independent double-grid FinFET (Fin Field-Effect Transistor) channel potential distribution analysis model which comprises a source electrode, wherein the source electrode is arranged on one side of a powered channel; the side of the powered channel, which is deviated from the powered channel, is provided with a drain electrode; the top surface of the powered channel is provided with an upper grid electrode; and the bottom surface of the powered channel is provided with a lower grid electrode. The independent double-grid FinFET channel potential distribution analysis model is characterized in that the device structure adopts the following potential distribution model analysis formula. The independent double-grid FinFET channel potential distribution analysis model disclosed by the invention does not use more approximate conditions and solves a two-dimensional poisson equation by using a progression method so as to establish a channel potential analysis model; the analysis model adopts more reasonable boundary condition; complex geometrical structure parameters and experimental parameters are not introduced into the analysis model; and the analysis model is suitable for different conditions such as substrate reversed bias voltages, drain voltages and the like, well accords with a numerical simulation result and has the advantages of simple form, high computing accuracy and high computing speed.

Description

A kind of separate double gate FinFET is resolved the groove potential distributed model

Technical field

The invention belongs to technical field of semiconductors, relate in particular to a kind of separate double gate FinFET (FinField-Effect Transistor fin formula field-effect transistor) and resolve the groove potential distributed model.

Background technology

For the integrated level that improves integrated circuit and the performance of chip, along with the development of integrated circuit MOS device technology, the device critical size is more and more littler.For single grid planar technology of main flow, the grid length of device can not unconfinedly be dwindled, along with a series of second-order effect general designation short-channel effect appears in device dimensions shrink.Electric properties of devices often becomes very poor under the short channel situation.In order to overcome short-channel effect to the influence of small size MOS device performance and reliability, some novel device architectures have occurred, mos field effect transistor (mos field effect transistor Metal-Oxide-Semiconductor Field Effect Transistor is called for short MOSFET) as multi-gate structure.FinFET is a kind of of multiple-grid MOSFET, is considered to get a good chance of becoming the main flow device under the littler 10nm-20nm yardstick.For novel FinFET structure, its grid surrounds the area of conducting channel much larger than the MOSFET of conventional planar technology, even the control raceway groove that grid also can be fabulous under short channel situation conduction, suppress short-channel effect, reduce the device quiescent dissipation, obtain good subthreshold value amplitude of oscillation characteristic and very high carrier mobility.

Research object of the present invention is a kind of in the FinFET structure: the separate double gate FinFET.In order to make accurately mimic channel characteristic of circuit emulator that circuit designer uses, the accurately and efficiently analytic model of setting up the separate double gate FinFET is very important.For short-channel effect, people generally use numerical computation method and analytic method to study.Be not easy the input circuit simulator program but numerical method is more accurate usually, and analytic method can address this problem.And analytic method mainly contains the method for electric charge apportion model and deberthing loose measure journey.The electric charge apportion model only can correctly be foretold short channel effect within the specific limits, because it is supposed but not experiment based on how much the electric charge distribution of source drain-gate.So leak to press, substrate bias is bigger, raceway groove deviation more in short-term is bigger.For analytic model, groove potential model in the past is under the approximate hypothesis of gradual channel, draws under the condition of vertical rate of change of having ignored the raceway groove electric field.For the device of 10nm magnitude, gradual channel is approximate can not to be suitable for, and must draw the groove potential distributed model on the basis of finding the solution two-dimentional Poisson equation.Can use a series of supposition or approximate condition when finding the solution two-dimentional Poisson equation usually, this can make it reduce in raceway groove validity very in short-term.

Summary of the invention

The objective of the invention is to set up the groove potential analytic model by using series method to find the solution two-dimentional Poisson equation to the separate double gate FinFET, can use a series of supposition or approximate condition when finding the solution two-dimentional Poisson equation in order to solve in the prior art, the problem that it is reduced in raceway groove validity very in short-term.

Provide a kind of separate double gate FinFET to resolve the groove potential distributed model to achieve these goals, comprise: the source electrode that energising raceway groove one side is provided with, the side that described energising raceway groove deviates from described source electrode is provided with drain electrode, the end face that is positioned at described energising raceway groove is provided with grid, the bottom surface of described energising raceway groove is provided with down grid, wherein, the Potential Distributing model analytic expression of this device architecture is:

$\mathrm{\ψ}(x,y)=V_{\mathrm{SS}}+\frac{V_D}{L}Z+\underset{n=1}{\overset{\∞}{\mathrm{\Σ}}}{A}_n\left(y\right)\sin \frac{\mathrm{n\πx}}{L}$

V wherein _SSBe built-in electromotive force, V _DBe that drain voltage, L are that the described source electrode in described energising raceway groove both sides is to length, T between the described drain electrode _SiBe the thickness of silicon, V _GSBe gate voltage, V _FBBe flat-band voltage, V _GFFThe last grid voltage that represents described energising raceway groove end face deducts the value of flat-band voltage, as V _GFF=V _{On the GS}-V _FB, V _GFBThe following grid voltage that represents described energising raceway groove bottom surface deducts the value of flat-band voltage, as V _GFB=V _{Under the GS}-V _FB, ε _SiBe specific inductive capacity, the C of silicon _OxBe gate oxide unit-area capacitance,

For the ratio of following grid and last grid institute making alive, Be the ratio of following grid with the electric capacity of last grid.Semiconductor surface place electromotive force minimum point, i.e. virtual negative electrode place, z=z ₀In the formula:

$r_n=\frac{\mathrm{n\π}}{L},$ n=1，2，3…，

$A_n\left(y\right)=C_n{e}^{r_{n}y}+D_n{e}^{-r_{n}y}-\frac{f_n}{r_{n^2}}$

$C_n=\frac{C_{\mathrm{ox}1}[({\mathrm{\ϵ}}_{\mathrm{si}}{r}_n-r_2{C}_{\mathrm{ox}1})(f_n-G_n{r}_n^2)+r_2(C_{\mathrm{ox}1}+{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n)(f_n-H_n{r}_n^2)e^{r_n{\mathrm{\τ}}_{\mathrm{si}}}\text{]}}{r_n^2[C_{\mathrm{ox}1}{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n(1+r_2)(1+e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})-(r_2{C}_{\mathrm{ox}1}^2+{\mathrm{\ϵ}}_{\mathrm{si}}^2{r}_n^2)(1-e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})]}$

$D_n=C_{\mathrm{ox}1}{e}^{r_n{\mathrm{\τ}}_{\mathrm{si}}}\frac{[({\mathrm{\ϵ}}_{\mathrm{si}}{r}_n+r_2{C}_{\mathrm{ox}1})(f_n-G_n{r}_n^2)e^{r_n{\mathrm{\τ}}_{\mathrm{si}}}-r_2(C_{\mathrm{ox}1}-{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n)(f_n-H_n{r}_n^2)]}{r_n^2[C_{\mathrm{ox}1}{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n(1+r_2)(1+e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})-(r_2{C}_{\mathrm{ox}1}^2+{\mathrm{\ϵ}}_{\mathrm{si}}^2{r}_n^2)(1-e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})]}$

$G_n=\frac{2}{\mathrm{n\π}}[(V_{\mathrm{SS}}-V_{\mathrm{GFF}})(1-{(-1)}^n)-{(-1)}^n{V}_D]$

$H_n=\frac{2}{\mathrm{n\π}}[(V_{\mathrm{SS}}-r_1{V}_{\mathrm{GFF}})(1-{(-1)}^n)-{(-1)}^n{V}_D].$

Above-mentioned separate double gate FinFET is resolved the groove potential distributed model, wherein, and described source ground.

Above-mentioned separate double gate FinFET is resolved the groove potential distributed model, and wherein, the boundary condition of described energising raceway groove is: and ψ (x=0, y)=V _Ss, ψ (x=L, y)=V _Ss+ V _D,

$\mathrm{\ψ}(x,y=0)={V_{\mathrm{GFF}}+\frac{{\mathrm{\ϵ}}_{\mathrm{si}}}{C_{\mathrm{ox}1}}\frac{\mathrm{\δ\Ψ}}{\mathrm{\δy}}|}_{y=0},$ $\mathrm{\ψ}(x,y=t_{\mathrm{si}})={V_{\mathrm{GFB}}+\frac{{\mathrm{\ϵ}}_{\mathrm{si}}}{C_{\mathrm{ox}2}}\frac{\mathrm{\δ\Ψ}}{\mathrm{\δy}}|}_{y={\mathrm{\τ}}_{\mathrm{si}}}.$

Above-mentioned separate double gate FinFET is resolved the groove potential distributed model, and wherein, the Poisson equation of this separate double gate FinFET Potential Distributing under the rectangular coordinate form is:

Separate double gate FinFET provided by the invention resolves the groove potential distributed model, adopted the following effect that has of as above scheme:

1, studies the separate double gate FinFET with resolving, and obtained the analytical expression of device channel Potential Distributing

2, by analyzing with device simulation software emulation result, the groove potential distributed model that parses is consistent with simulation result, and the proof model is effectively correct.

3, simultaneously result of the present invention has great role to VLSI (very large scale integrated circuit) designs, and this novel separate double gate FinFET has long, the big area of grid of short grid, thicker oxide layer and little tunnelling current.

4, the groove potential model that the present invention relates to can be embedded in technology and the device simulation software and use.

Description of drawings

Fig. 1 is common FinFET structural representation;

Fig. 2 is separate double gate FinFET structural representation of the present invention;

Fig. 3 is separate double gate FinFET sectional view of the present invention;

Fig. 4 A is that separate double gate FinFET of the present invention is at the synoptic diagram of different geometrical size lower surface gesture with the raceway groove change in location;

Fig. 4 B for separate double gate FinFET of the present invention under difference grid bias lower surface gesture with the synoptic diagram of raceway groove change in location.

Embodiment

For technological means that the present invention is realized, create feature, reach purpose and effect is easy to understand, following to concrete diagram, further set forth the present invention.

Shown in Fig. 2,3,4A and 4B, a kind of separate double gate FinFET is resolved the groove potential distributed model, comprise: the source electrode that energising raceway groove one side is provided with, the side that the energising raceway groove deviates from source electrode is provided with drain electrode, the end face that is positioned at the energising raceway groove is provided with grid, the bottom surface of energising raceway groove is provided with down grid, and wherein, the Potential Distributing model analytic expression of this device architecture is:

$\mathrm{\ψ}(x,y)=V_{\mathrm{SS}}+\frac{V_D}{L}Z+\underset{n=1}{\overset{\∞}{\mathrm{\Σ}}}{A}_n\left(y\right)\sin \frac{\mathrm{n\πx}}{L}$

V wherein _SSBe built-in electromotive force, V _DBe that drain voltage, L are extremely length, the T between the drain electrode of raceway groove both sides source electrode that switch on _SiBe the thickness of silicon, V _GSBe gate voltage, V _FBBe flat-band voltage, V _GFFThe last grid voltage of representative energising raceway groove end face deducts the value of flat-band voltage, as V _GFF=V _{On the GS}-V _FB, V _GFBThe following grid voltage of representative energising raceway groove bottom surface deducts the value of flat-band voltage, as V _GFB=V _{Under the GS}-V _FB, ε _SiBe specific inductive capacity, the C of silicon _OxBe gate oxide unit-area capacitance, For the ratio of following grid and last grid institute making alive, Be the ratio of following grid with the electric capacity of last grid.Semiconductor surface place electromotive force minimum point, i.e. virtual negative electrode place, z=z ₀, in the formula:

$r_n=\frac{\mathrm{n\π}}{L},$ n=1，2，3…，

$A_n\left(y\right)=C_n{e}^{r_{n}y}+D_n{e}^{-r_{n}y}-\frac{f_n}{r_{n^2}}$

$C_n=\frac{C_{\mathrm{ox}1}[({\mathrm{\ϵ}}_{\mathrm{si}}{r}_n-r_2{C}_{\mathrm{ox}1})(f_n-G_n{r}_n^2)+r_2(C_{\mathrm{ox}1}+{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n)(f_n-H_n{r}_n^2)e^{r_n{\mathrm{\τ}}_{\mathrm{si}}}\text{]}}{r_n^2[C_{\mathrm{ox}1}{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n(1+r_2)(1+e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})-(r_2{C}_{\mathrm{ox}1}^2+{\mathrm{\ϵ}}_{\mathrm{si}}^2{r}_n^2)(1-e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})]}$

$D_n=C_{\mathrm{ox}1}{e}^{r_n{\mathrm{\τ}}_{\mathrm{si}}}\frac{[({\mathrm{\ϵ}}_{\mathrm{si}}{r}_n+r_2{C}_{\mathrm{ox}1})(f_n-G_n{r}_n^2)e^{r_n{\mathrm{\τ}}_{\mathrm{si}}}-r_2(C_{\mathrm{ox}1}-{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n)(f_n-H_n{r}_n^2)]}{r_n^2[C_{\mathrm{ox}1}{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n(1+r_2)(1+e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})-(r_2{C}_{\mathrm{ox}1}^2+{\mathrm{\ϵ}}_{\mathrm{si}}^2{r}_n^2)(1-e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})]}$

$G_n=\frac{2}{\mathrm{n\π}}[(V_{\mathrm{SS}}-V_{\mathrm{GFF}})(1-{(-1)}^n)-{(-1)}^n{V}_D]$

$H_n=\frac{2}{\mathrm{n\π}}[(V_{\mathrm{SS}}-r_1{V}_{\mathrm{GFF}})(1-{(-1)}^n)-{(-1)}^n{V}_D].$

In specific embodiments of the invention, source ground.

In specific embodiments of the invention, the boundary condition of energising raceway groove is: and ψ (x=0, y)=V _Ss, ψ (x=L, y)=V _Ss+ V _D, $\mathrm{\ψ}(x,y=0)={V_{\mathrm{GFF}}+\frac{{\mathrm{\ϵ}}_{\mathrm{si}}}{C_{\mathrm{ox}1}}\frac{\mathrm{\δ\Ψ}}{\mathrm{\δy}}|}_{y=0},$ $\mathrm{\ψ}(x,y=t_{\mathrm{si}})={V_{\mathrm{GFB}}+\frac{{\mathrm{\ϵ}}_{\mathrm{si}}}{C_{\mathrm{ox}2}}\frac{\mathrm{\δ\Ψ}}{\mathrm{\δy}}|}_{y={\mathrm{\τ}}_{\mathrm{si}}}$

In specific embodiments of the invention, the Poisson equation of this separate double gate FinFET Potential Distributing under the rectangular coordinate form is: $\frac{d^2\mathrm{\Ψ}}{{\mathrm{dx}}^2}+\frac{d^2\mathrm{\Ψ}}{{\mathrm{dy}}^2}=\frac{{\mathrm{qN}}_A}{{\mathrm{\ϵ}}_{\mathrm{si}}}.$

Below by specific embodiment model provided by the invention is described in detail, in order to better understand model provided by the invention, but the content of embodiment does not limit protection scope of the present invention.

For the separate double gate FinFET, its sectional view as shown in Figure 3, ignore charge carrier to Potential Distributing contribution exhaust entirely or weak transoid hypothesis under, obtain the Poisson equation under the rectangular coordinate form of separate double gate FinFET Potential Distributing: $\frac{d^2\mathrm{\Ψ}}{{\mathrm{dx}}^2}+\frac{d^2\mathrm{\Ψ}}{{\mathrm{dy}}^2}=\frac{{\mathrm{qN}}_A}{{\mathrm{\ϵ}}_{\mathrm{si}}}---\left(1\right)$

According to its boundary condition: ψ (x=0, y)=V _Ss(2)

ψ(x=L,y)=V _ss+V _D （3）

$\mathrm{\ψ}(x,y=0)={V_{\mathrm{GFF}}+\frac{{\mathrm{\ϵ}}_{\mathrm{si}}}{C_{\mathrm{ox}1}}\frac{\mathrm{\δ\Ψ}}{\mathrm{\δy}}|}_{y=0}---\left(4\right)$

$\mathrm{\ψ}(x,y=t_{\mathrm{si}})={V_{\mathrm{GFB}}+\frac{{\mathrm{\ϵ}}_{\mathrm{si}}}{C_{\mathrm{ox}2}}\frac{\mathrm{\δ\Ψ}}{\mathrm{\δy}}|}_{y={\mathrm{\τ}}_{\mathrm{si}}}---\left(5\right)$

Further, equation (4), (5) are the boundary conditions that obtains by Gauss theorem.

V wherein _SSBe built-in electromotive force, V _DBe that drain voltage, L are extremely length, the T between the drain electrode of raceway groove both sides source electrode that switch on _SiBe the thickness of silicon, V _GSBe gate voltage, V _FBBe flat-band voltage, V _GFFThe last grid voltage of representative energising raceway groove end face deducts the value of flat-band voltage, as V _GFF=V _{On the GS}-V _FB, V _GFBThe following grid voltage of representative energising raceway groove bottom surface deducts the value of flat-band voltage, as V _GFB=V _{Under the GS}-V _FB, ε _SiBe specific inductive capacity, the C of silicon _OxBe gate oxide unit-area capacitance,

For the ratio of following grid and last grid institute making alive,

Be the ratio of following grid with the electric capacity of last grid.Semiconductor surface place electromotive force minimum point, i.e. virtual negative electrode place, z=z ₀, in the formula:

$r_n=\frac{\mathrm{n\π}}{L},$ n=1，2，3…，

$A_n\left(y\right)=C_n{e}^{r_{n}y}+D_n{e}^{-r_{n}y}-\frac{f_n}{r_{n^2}}$

$C_n=\frac{C_{\mathrm{ox}1}[({\mathrm{\ϵ}}_{\mathrm{si}}{r}_n-r_2{C}_{\mathrm{ox}1})(f_n-G_n{r}_n^2)+r_2(C_{\mathrm{ox}1}+{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n)(f_n-H_n{r}_n^2)e^{r_n{\mathrm{\τ}}_{\mathrm{si}}}\text{]}}{r_n^2[C_{\mathrm{ox}1}{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n(1+r_2)(1+e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})-(r_2{C}_{\mathrm{ox}1}^2+{\mathrm{\ϵ}}_{\mathrm{si}}^2{r}_n^2)(1-e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})]}$

$D_n=C_{\mathrm{ox}1}{e}^{r_n{\mathrm{\τ}}_{\mathrm{si}}}\frac{[({\mathrm{\ϵ}}_{\mathrm{si}}{r}_n+r_2{C}_{\mathrm{ox}1})(f_n-G_n{r}_n^2)e^{r_n{\mathrm{\τ}}_{\mathrm{si}}}-r_2(C_{\mathrm{ox}1}-{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n)(f_n-H_n{r}_n^2)]}{r_n^2[C_{\mathrm{ox}1}{\mathrm{\ϵ}}_{\mathrm{si}}{r}_n(1+r_2)(1+e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})-(r_2{C}_{\mathrm{ox}1}^2+{\mathrm{\ϵ}}_{\mathrm{si}}^2{r}_n^2)(1-e^{{2r}_n{\mathrm{\τ}}_{\mathrm{si}}})]}$

$G_n=\frac{2}{\mathrm{n\π}}[(V_{\mathrm{SS}}-V_{\mathrm{GFF}})(1-{(-1)}^n)-{(-1)}^n{V}_D]$

$H_n=\frac{2}{\mathrm{n\π}}[(V_{\mathrm{SS}}-r_1{V}_{\mathrm{GFF}})(1-{(-1)}^n)-{(-1)}^n{V}_D].$

Shown in Fig. 4 A, the track of square represents simulation result, lines track representative model result, different components structure under identical bias,

t _ox1＝t _ox2＝1.5nm,V _DS=0.1V，N _A＝10 ¹⁶cm ^-3，V _GSF＝V _GSB＝0.2V。

Shown in Fig. 4 B, the track of square represents simulation result, lines track representative model result, identity unit structure under different bias voltages,

L=25mm,t _si=10nm L=25mm,t _si=10nm

，t _ox1＝t _ox2＝1.5nm,V _DS=0.1V，N _A＝10 ¹⁶cm ^-3，V _GSF＝0.2V。

In sum, a kind of separate double gate FinFET of the present invention is resolved the groove potential distributed model, do not use too much approximate condition, use series method to find the solution two-dimentional Poisson equation and set up the groove potential analytic model, this analytic model has adopted comparatively appropriate boundary condition, do not introduce complicated geometrical structure parameter and empirical parameter, be applicable to conditions such as different substrate reversed bias voltages, drain voltage, and meet ground better with The results of numerical simulation, there is form succinct, the computational accuracy height, the advantage that computing velocity is fast.

More than specific embodiments of the invention are described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and substituting also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of doing under the spirit and scope of the present invention, all should contain within the scope of the invention.

Claims (4)

1. a separate double gate FinFET is resolved the groove potential distributed model, comprise: the source electrode that energising raceway groove one side is provided with, the side that described energising raceway groove deviates from described source electrode is provided with drain electrode, the end face that is positioned at described energising raceway groove is provided with grid, the bottom surface of described energising raceway groove is provided with down grid, it is characterized in that the Potential Distributing model analytic expression of this device architecture is:

$\mathrm{\ψ}(x,y)=V_{\mathrm{SS}}+\frac{V_D}{L}Z+\underset{n=1}{\overset{\∞}{\mathrm{\Σ}}}{A}_n\left(y\right)\sin \frac{\mathrm{n\πx}}{L}$

V wherein _SSBe built-in electromotive force, V _DBe that drain voltage, L are that the described source electrode in described energising raceway groove both sides is to length, T between the described drain electrode _SiBe the thickness of silicon, V _GSBe gate voltage, V _FBBe flat-band voltage, V _GFFThe last grid voltage that represents described energising raceway groove end face deducts the value of flat-band voltage, as V _GFF=V _{On the GS}-V _FB, V _GFBThe following grid voltage that represents described energising raceway groove bottom surface deducts the value of flat-band voltage, as V _GFB=V _{Under the GS}-V _FB, ε _SiBe specific inductive capacity, the C of silicon _OxBe gate oxide unit-area capacitance,

For the ratio of following grid and last grid institute making alive,

Be the ratio of grid and the electric capacity of last grid down, semiconductor surface place electromotive force minimum point, i.e. virtual negative electrode place, z=z ₀, in the formula:

$r_n=\frac{\mathrm{n\π}}{L},$ n=1，2，3…，

$A_n\left(y\right)=C_n{e}^{r_{n}y}+D_n{e}^{-r_{n}y}-\frac{f_n}{r_n^2}$

$G_n=\frac{2}{\mathrm{n\π}}[(V_{\mathrm{SS}}-V_{\mathrm{GFF}})(1-{(-1)}^n)-{(-1)}^n{V}_D]$

$H_n=\frac{2}{\mathrm{n\π}}[(V_{\mathrm{SS}}-r_1{V}_{\mathrm{GFF}})(1-{(-1)}^n)-{(-1)}^n{V}_D].$

2. separate double gate FinFET according to claim 1 is resolved the groove potential distributed model, it is characterized in that described source ground.

3. separate double gate FinFET according to claim 1 is resolved the groove potential distributed model, it is characterized in that the boundary condition of described energising raceway groove is: $\mathrm{\ψ}(x=0,y)=V_{\mathrm{SS}},\mathrm{\ψ}(x=L,y)=V_{\mathrm{SS}}+V_D,$

4. separate double gate FinFET according to claim 1 is resolved the groove potential distributed model, it is characterized in that the Poisson equation of this separate double gate FinFET Potential Distributing under the rectangular coordinate form is:

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