CN103178853A - Compressive-sensing-based sparse signal under-sampling method and implementation device - Google Patents

Abstract

The invention relates to a compressive-sensing-based sparse signal under-sampling method and an implementation device, which are used for lowering a sampling rate of frequency-domain sparse signals on the premise of guaranteeing the restoration effect of the signals. The method comprises the following steps of: generating a trigger signal and an m sequence by an FPGA (Field Programmable Gate Array), carrying out frequency mixing on the m sequence and the measured sparse signal after the m sequence is modulated, and carrying out filtering by a low pass filter; sampling the filtered signal and storing sampled data by a data sampling module after the data sampling module detects the triggering signal; and calculating a transfer function of a system and the m sequence corresponding to the sampled data when the signal is reconstructed, and then restoring the original signal by an OMP (Orthogonal Matching Pursuit) signal reconstructing algorithm. The compressive-sensing-based sparse signal under-sampling method and the implement device are suitable for the under-sampling of frequency-domain sparse analogue signals.

Description

Owe the method for sampling and implement device based on the sparse signal of compressed sensing

Technical field

The present invention relates to a kind of sparse signal and owe the method for sampling and implement device.

Background technology

Traditional intelligence sample process must be followed nyquist sampling theorem, and namely sampling rate is greater than 2 times of original signal highest frequency at least, could recover without distortion primary signal like this from the discrete data that sampling obtains.Yet along with the development of information technology, process framework take nyquist sampling theorem as the signal on basis sampling rate and the processing speed of front-end A/D C proposed higher requirement, bring immense pressure also for the links such as transmission, storage of backend information.Solving the common scheme of these pressure is Signal Compression, but, this method compressed afterwards of first sampling does not reduce the pressure of front-end A/D C, and Signal Compression means that a large amount of redundant informations is arranged in sampling process, has wasted the resources such as a large amount of sensing elements, time and memory space.

By people such as Candes and Donoho, compressive sensing theory (Compressive Sensing, CS) was proposed in 2004.This theory can be carried out Signal Compression and sampling merging, namely in signal acquisition, just data is suitably compressed, and just can significantly reduce signal sampling rate when signal has sparse property.

Have at signal under the prerequisite of sparse property, can (every delegation of Φ can be regarded as a transducer here with the incoherent observing matrix Φ of orthogonal basis matrix Ψ: M * N (M N) with one, it and multiplication, obtained the partial information of signal), signal x is carried out compression observation:

y＝Φx (1)

Just can obtain M Systems with Linear Observation value (projection) y ∈ ^MComprised the enough information of reconstruction signal x in these a small amount of linear projections.

Then obtain the reconstruction signal of original signal from measured value y by special algorithm

The frequency-domain sparse signal has the characteristic of spectrum sparse, is namely sparse on frequency domain, and orthogonal basis matrix Ψ just can get Fourier transform matrix like this.If x (t) is an analog signal, it is carried out Fourier transform, namely its Fourier transform base vector with N * 1 dimension Linear combination represent.X (t) can expand into:

$x\left(t\right)=\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{\mathrm{\α}}_n{\mathrm{\ψ}}_n\left(t\right)---\left(2\right)$

Wherein: Ψ _n(t)=e ^{J2 π t (n-1)/N}

Fourier Transform Coefficients:

α _n＝<x(t)，Ψ _n(t)>＝Ψ _n ^T(t)x(t)

These coefficients form coefficient vector α=(α ₁, α ₂..., α _n) ^T, the frequency spectrum of Here it is signal, each element is a spectrum component of signal.If by after descending, element value is decayed rapidly with the element in coefficient vector α, the coefficient number that perhaps coefficient vector α intermediate value is larger is K, and K is little more a lot of than N, show that this signal is sparse at frequency domain, claim that x (t) is the frequency-domain sparse signal, its degree of rarefication is K.

For the frequency-domain sparse signal sampling, utilize compressive sensing theory to break through and be the restriction of Qwest's sampling law, realize owing sampling.Compressive sensing theory represents, the sampling rate of frequency-domain sparse signal no longer depends on highest frequency or the bandwidth of signal, but depends on the degree of rarefication K of signal.If the signal degree of rarefication is K, when signal is discrete signal, can be obtained the scope of minimum sampling number M by formula (3), wherein N is the length of original signal, c is a very little constant.When signal is the continuous analog signal, N be original signal be Qwest's frequency, can be obtained the scope of Least sampling rate M by formula (3).

M≥cklog(N/K) (3)

Summary of the invention

The present invention is for the situation decline lower frequency region sparse signal sample rate in assurance signal recovery effects, thereby provides a kind of sparse signal based on compressed sensing to owe the method for sampling and implement device.

Sparse signal based on compressed sensing is owed the method for sampling, and it is realized by following steps:

Step 1, employing are embedded in m sequencer generation m sequence in FPGA; And adopt FPGA synchronously to produce triggering signal;

Step 2, the m sequence that step 1 is produced adopt signal conditioning circuit to carry out signal condition, the m sequence after obtaining to nurse one's health;

After step 3, conditioning that step 2 is obtained, the m sequence adopts multiplier to carry out mixing with tested sparse signal, the acquisition mixed frequency signal;

Step 4, employing low pass filter carry out low-pass filtering to the mixed frequency signal that step 3 obtains, signal after the acquisition low-pass filtering;

Produce triggering signal in step 5, employing step 1 and trigger sample circuit, and after adopting sample circuit to the low-pass filtering of step 4 acquisition, signal is sampled, the acquisition sampled result;

Step 6, employing host computer carry out signal reconstruction to the sampled result that step 5 obtains, and obtain the reconstruction result of original tested sparse signal.

The concrete grammar that the sampled result that employing host computer described in step 6 obtains step 5 is carried out signal reconstruction is:

Steps A, according to formula:

H(s)＝H ₁(s)G(s)

Acquisition is mixed to the transfer function H (s) between sampling;

In formula: H ₁(s) be the transfer function of low pass filter, described low pass filter is second order Butterworth simulation low-pass filter;

G (s) is for being mixed to the continued product of operational amplification circuit transfer functions at different levels between sampling;

H ₁(s) be according to formula:

$H_1\left(s\right)=\frac{w_c^2}{{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA00002948651100031.png,HDA00002948651100051.png"\; state="\{\{state\}\}">s</figure-callout>}}^2+\frac{w_c}{Q}s+{\mathrm{<figure-callout\; id="2"\; label="w\; c"\; filenames="HDA00002948651100031.png,HDA00002948651100051.png"\; state="\{\{state\}\}">w</figure-callout>}}_c^{}}$

Obtain;

In formula: w _cBe the cut-off frequency of low pass filter, Q is quality factor; S is-symbol variable;

G (s) is according to formula:

G(s)＝G ₁(s)G ₂(s)…G _n(s)

Obtain;

In formula: G ₁(s) be first operational amplification circuit transfer function; G ₂(s) be the transfer function of second operational amplification circuit; G _n(s) be the transfer function of n operational amplification circuit; N is positive integer;

Step B, employing Bilinear transformation method are carried out the discretization processing to the transfer function H (s) that is mixed between sampling that steps A obtains, obtain digital filter transfer function H (z), and try to achieve the impulse response h (n) of digital filter transfer function H (z);

Step C, the impulse response h (n) of the digital filter transfer function H in step B (z) is overturn, obtain upset h as a result _r(n);

Step D, with the m sequence p in step 1 _c(n) and the upset that obtains of step C h as a result _r(n) do convolution algorithm, obtain observing matrix Φ;

Step e, according to formula:

Θ＝ΦΨ

Obtain perception matrix Θ;

In formula: Ψ is the orthogonal basis matrix, and described Ψ is according to formula:

Ψ＝dftmtx(N)

Obtain; Described dftmtx be MATLAB software from tape function;

Step F, the perception matrix Θ that obtains according to step e realize signal reconstruction by orthogonal matching pursuit algorithm.

Owe the implement device of the method for sampling based on the sparse signal of compressed sensing, it comprises FPGA15, modulate circuit 16, multiplier 11, low pass filter 12, sample circuit 13 and host computer 14;

Described FPGA15 is embedded with the m sequencer, and described m sequencer is for generation of the m sequence;

The m sequence output of described FPGA15 is connected with the signal input part of signal conditioning circuit 16; The signal output part of described signal conditioning circuit 16 is connected with a signal input part of multiplier 11; No. two signal input parts of described multiplier 11 are used for receiving tested sparse signal; The signal output part of described multiplier 11 is connected with the signal input part of low pass filter 12; The signal output part of described low pass filter 12 is connected with the signal input part of sample circuit 13; The signal output part of described sample circuit 13 is connected with the signal input part of host computer 14.

Method of the present invention is utilized the sparse characteristic of frequency-domain sparse signal spectrum, under the prerequisite that guarantees the signal recovery effects, decrease the sample rate of frequency-domain sparse signal, and when the maximum of the contained frequency component of signal is larger, this effect is more obvious, and can make actual sample rate is Qwest's frequency much smaller than signal.The requirement that can reduce the speed of AD device of the present invention, and sampled data output is little, saves memory space, is conducive to the transmission of data.

Description of drawings

Fig. 1 is system configuration schematic diagram of the present invention; Fig. 2 is m sequencer and the control logic schematic diagram that embeds in FPGA; Fig. 3 is the connection diagram of subtraction circuit in embodiment five; Fig. 4 is the circuit connection diagram of AD633 analog multiplier in embodiment five; Fig. 5 is MAX275 internal structure and second order Butterworth simulation low-pass filter circuit connection diagram in embodiment five; Fig. 6 is the data point line waveform schematic diagram of original tested sparse signal; Fig. 7 is the spectrum diagram that contains the original tested sparse signal of 3kHz, two frequencies of 4kHz; Fig. 8 is the line waveform schematic diagram of data point in signal after reconstruct; Fig. 9 contains the experimental result picture of the original tested sparse signal of 3kHz, two frequencies of 4kHz with the data reconstruction of RANDOM SOLUTION adjusting system.

Embodiment

Embodiment one, owe the method for sampling based on the sparse signal of compressed sensing, it is realized by following steps:

Step 1, employing are embedded in m sequencer generation m sequence in FPGA; And adopt FPGA synchronously to produce triggering signal;

Step 2, the m sequence that step 1 is produced adopt signal conditioning circuit to carry out signal condition, the m sequence after obtaining to nurse one's health;

After step 3, conditioning that step 2 is obtained, the m sequence adopts multiplier to carry out mixing with tested sparse signal, the acquisition mixed frequency signal;

Step 4, employing low pass filter carry out low-pass filtering to the mixed frequency signal that step 3 obtains, signal after the acquisition low-pass filtering;

Produce triggering signal in step 5, employing step 1 and trigger sample circuit, and after adopting sample circuit to the low-pass filtering of step 4 acquisition, signal is sampled, the acquisition sampled result;

Step 6, employing host computer carry out signal reconstruction to the sampled result that step 5 obtains, and obtain the reconstruction result of original tested sparse signal.

Embodiment two, owe the implement device of the method for sampling based on the sparse signal of compressed sensing, it comprises FPGA15, modulate circuit 16, multiplier 11, low pass filter 12, sample circuit 13 and host computer 14;

Described FPGA15 is embedded with the m sequencer, and described m sequencer is for generation of the m sequence;

The m sequence output of described FPGA15 is connected with the signal input part of signal conditioning circuit 16; The signal output part of described signal conditioning circuit 16 is connected with a signal input part of multiplier 11; No. two signal input parts of described multiplier 11 are used for receiving tested sparse signal; The signal output part of described multiplier 11 is connected with the signal input part of low pass filter 12; The signal output part of described low pass filter 12 is connected with the signal input part of sample circuit 13; The signal output part of described sample circuit 13 is connected with the signal input part of host computer 14.

The difference that the described sparse signal based on compressed sensing of embodiment three, this embodiment and embodiment two is owed the implement device of the method for sampling is, the model of FPGA15 is EP2C8Q208.

The difference that the described sparse signal based on compressed sensing of embodiment four, this embodiment and embodiment two is owed the implement device of the method for sampling is, it is that the chip of AD633 is realized that multiplier 11 adopts models.

The difference that the described sparse signal based on compressed sensing of embodiment five, this embodiment and embodiment two is owed the implement device of the method for sampling is, the second order Butterworth simulation low-pass filter that the chip that low pass filter 12 is MAX275 for the employing model is built.

Operation principle: preparation:

Preparation before system's operation is the m sequential value that obtains under a certain group of initial value.Operating procedure is as follows:

1, set one group of initial value for the m sequencer, and remain unchanged, each like this when regenerating the m sequence all by same rule, guarantees the sequence of each generation all.

2, the data input pin of uniform sampling module is connected to the m sequence output of FPGA, sampling module is set to trigger sampling configuration, and trigger control end is connected to the triggering signal output of FPGA.It is identical with the jump frequency (being the clock frequency of m sequencer) of m sequence that the sample rate of data acquisition module is set to, and for example, the clock of m sequence is 10kHz, and sample rate also is made as 10kHz.

3, make the control trigger module produce triggering signal, make the m block produce the m sequence, triggering signal is detected by data acquisition module simultaneously, begins the m sequence is sampled.Obtain complete m sequential value under this group initial value after the sampling certain hour, be saved in a file it standby.

Actual moving process:

1, set one group of initial value identical during with preparation for the m sequencer, and remain unchanged.

2, measured signal is connected to the input of system, i.e. another input of multiplier.

3, the data input pin of uniform sampling module is connected to the output of filter.Sampling module is set to trigger sampling configuration, and trigger control end still is connected to the triggering signal output of FPGA.That sample rate arranges as long as than the value of being calculated by formula (3) greatly.For example, the degree of rarefication of measured signal is 2, and the signal highest frequency component is 4kHz, and calculating sample rate needs greater than 6.6c.Wherein c is a constant, and is relevant with the error size of real system itself, accuracy, operational environment etc., needs experiment to determine.Generally, the larger reconstruct better effects if of sample rate.

4, control trigger module and produce triggering signal, make the m block produce the m sequence, triggering signal is detected by data acquisition module simultaneously, begins filtered signal is sampled.Sampled data is transferred in host computer stores.

5, data collecting module collected to data be measured signal and m sequence through the multiplier mixing, the result after low pass filter filtering and conditioning.Because sampling rate is known, can learn that by calculating this section participates in the length of the m sequence of systemic effect in the sampling time, take out corresponding length from the m sequential file of keeping one section gets final product.For example, sampling rate is 2kHz, the sampled data of intercepting 0～0.1s, 200 data points that namely begin.If the jump frequency of m sequence is 10kHz, the data volume that 0～0.1s is corresponding is 1000, and 1000 data that intercepting begins most from the m sequential file of keeping before get final product.Call the signal reconstruction algorithm of finishing in host computer, utilize sampled data and the m sequential value of intercepting that signal is reconstructed, obtain frequency position and the corresponding amplitude of original signal.If necessary, reconstruct data are out become analog signal through D/A.

Each module of system describes in detail:

The FPGA module controls for generation of pseudo random sequence the generation that triggers sampled signal simultaneously.

What the present invention adopted when concrete the application is this pseudo random sequence of m sequence, utilizes the CycloneII of altera corp

This FPGA of series EP2C8Q208 produces.The m sequence is the abbreviation of longest linear feedback shift register sequence, is the sequence that produces by with the shift register of linear feedback, and has the longest cycle, has easy generation, regular many good characteristics such as strong, is a kind of important pseudo random sequence.

Also realized triggering the control logic of sampled signal in FPGA, be used for synchronous the generation and trigger sampled signal, controlled the Back end data acquisition module end output signal is sampled.

Fig. 2 is 10 grades of m sequencer and the triggering signal control logic schematic diagram of realizing in FPGA.

The initial amplitude range of m sequence is 0～3.3V, in order to produce negative amplitude, adjust with subtracter, subtraction circuit as shown in Figure 3, make its from 0 original～3.3V become-1.6～+ 1.7V, also greatly reduced simultaneously the m sequence at first with larger burr, improved quality.

Multiplier: the m sequence realizes mixing through multiplying each other in analog multiplier with the frequency-domain sparse signal after conditioning.Signal shows as the convolution of frequency spectrum in time domain multiplication at frequency domain.Because the spectral range of m sequence is very wide, just the frequency-domain sparse signal is modulated by convolution, realized spread spectrum, the frequency spectrum of original signal is applied to whole frequency axis, on frequency spectrum, all information of original signal are contained in each position, and, due to the participation of m sequence, be equivalent to original signal has been carried out signal scrambling, on frequency spectrum, the information at every bit place has all had unique sign.

What the present invention adopted when concrete the application is AD633 analog multiplier chip, and circuit as shown in Figure 5.There is 1/10 decay AD633 inside to the signal after multiplying each other, the too little meeting of signal amplitude is made troubles to the analyzing and processing of back, in order to make up this decay, the output signal of multiplier is amplified.Discharge circuit can use the fixed gain amplifier design, and is all identical will guarantee the signal component gain of different frequency.

Low pass filter: the key of this part is that the characteristic of practical filter is conformed to the theoretical transfer function of calculating.

Adopt active low-pass filter during specific implementation of the present invention, active filter can adopt amplifier to build, and also can design with integrated filter chip.Adopt integrated filter chip can obtain generally that index is better, the more accurate filter of parameter, and peripheral circuit is simple, design is convenient, has selected MAX275 active filter chip to build second order Butterworth simulation low-pass filter in this system, as shown in Figure 5.

Sample circuit: be used for that filtered signal is carried out low speed and sample and store.

The key of this part is to guarantee to sample to synchronize through the moment that system arrives sampling module with the m sequence zero hour, and namely the initial time of sampling is suitable.Sampling trigger signal is produced by FPGA, inputs to sampling module, and after only receiving the triggering sampled signal, sampling module just begins to carry out data acquisition and storage.

Host computer 14: signal reconstruction needs first observation process to be carried out modeling, tries to achieve the transfer function of modules, thereby tries to achieve corresponding observing matrix Φ, then tries to achieve perception matrix Θ.The data that recycling Θ and low speed uniform sampling obtain are recovered original signal by the signal reconstruction algorithm.

Concrete steps are:

1, derive by calculating or the mode of actual samples obtain one section in the sampling time data and participate in the m sequence P of systemic effect _c(n); Because sampling rate is known, can learn that by calculating this section participates in the length of the m sequence of systemic effect in the sampling time, from the m sequential file of keeping one section of the corresponding length of taking-up.For example, sampling rate is 2kHz, the sampled data of intercepting 0～0.1s, 200 data points that namely begin.If the jump frequency of m sequence is 10kHz, the data volume that 0～0.1s is corresponding is 1000, and 1000 data that intercepting begins most from the m sequential file of keeping before get final product.

2, ask the transfer function of frequency mixing module modulate circuits at different levels afterwards.

The amplification conditioning module is arranged after frequency mixing module, filter module, calculate the transfer function G of these modules ₁(s), G ₂(s) Then, ask the overall transfer function G (s) of these conditioning module, G (s) is the continued product of transfer functions at different levels:

G(s)＝G ₁(s)G ₂(s)… (4)

If these amplify conditioning module is all that fixed gain is amplified, the G that tries to achieve (s) is constant.

3, ask the transfer function of simulation low-pass filter.

The transfer function of second order Butterworth analog filter is:

$H_1\left(s\right)=\frac{w_c^2}{{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA00002948651100031.png,HDA00002948651100051.png"\; state="\{\{state\}\}">s</figure-callout>}}^2+\frac{w_c}{Q}s+w_c^2}---\left(5\right)$

W wherein _cBe the cut-off frequency of filter, Q is quality factor.

4, ask frequency mixing module afterwards to the transfer function H between sampling module (s), namely amplify the overall transfer function of conditioning link and low-pass filtering link, and obtain corresponding unit-sample response h (n).

The overall transfer function of amplifying conditioning link and low-pass filtering link is:

H(s)＝H ₁(s)G(s) (6)

In matlab by c2d () function with Bilinear transformation method with H (s) discretization, be transformed to the transfer function H (z) of digital filter, the jump frequency of the desirable m sequence of discrete frequency.Recycling impz () function is tried to achieve the impulse response h (n) of digital filter.

5, ask observing matrix Φ, quadrature dictionary matrix Ψ and perception matrix Θ

Observing matrix Φ is by pseudo random sequence P _c(n) and unit-sample response h (n) convolution and getting, due to signal at frequency-domain sparse, therefore quadrature dictionary matrix Ψ is Fourier transform matrix.

Ask the flow process of perception matrix Θ as follows:

Step 1: input unit-sample response h (n);

Step 2: to h (n) upset, be that h (n) is carried out inverted order here, try to achieve h _r(n), that is: h (1)=h _r(N) ..., h (N)=h _r(1).

Step 3: use pseudo random sequence P _c(n) and h (n) convolution, i.e. P _c(n) and h _r(n) be shifted successively, multiply each other, sue for peace, try to achieve the Φ of M * N.The size of each displacement is T _s=N/M, N are the length of original signal, also equal pseudo random sequence P _c(n) length, M for the downsample function to filtering after the data amount check adopted when sampling of signal low speed.

for j＝1:M

If j * T _sThe length of≤h (n)

The j of Φ is capable, and the 1st row are classified as to the j * T:

Φ(j，1:j×T _s)＝P _c(1:j×T _s).×h _r((n-j×T _s+1):n) (7)

else

The j of Φ is capable, the j * T _s-n+1 is listed as to the j * T _sClassify as:

Φ(j，(j×T _s-n+1):(j×T _s))＝P _c((j×T _s-n+1):j×T _s).×h _r(1:n) (8)

end

end

Step 4: ask orthogonal basis matrix Ψ.The function dftmtx that Calling MATLAB carries can be in the hope of the Fourier transform matrix Ψ of N * N: Ψ=dftmtx (N);

Step 5: ask perception matrix Θ.According to Θ=Φ Ψ, observing matrix Φ and the Fourier transform matrix Ψ that tries to achieve multiplied each other, obtain the perception matrix Θ of M * N.

6, with OMP signal reconstruction algorithm reconstruct original signal: compressive sensing theory has the multi-signal restructing algorithm, and the step of orthogonal matching pursuit (Orthogonal Matching Pursuit, OMP) algorithm is as follows:

Step 1: set algorithm input, perception matrix Θ, observation signal y, degree of rarefication K.

Step 2: each parameter of initialization, reconstruction signal

Residual error r ₀=y, signal support set

Step 3: iteration, in the l time circulation (l 〉=1), operation following (a)～(d) step.

(a) utilize correlation computations to seek signal and support index:

λ _l＝argmax _{j＝l，...，N}|<r _l-1，θ _j>| (9)

(b) signal that searches out is supported index and adds signal support set:

Λ _lΛ _l-1∪{λ _l} (10)

(c) upgrade residual error:

$r_l=y-{{\mathrm{\&theta;}}_{\mathrm{\&Lambda;}}}_l\left({\mathrm{\&theta;}}_{{\mathrm{\&Lambda;}}_l}^{+}y\right)---\left(11\right)$

(d) if l 〉=K, algorithm finishes.

Step 4: output reconstruction signal

$\hat{x}={\mathrm{\&theta;}}_{{\mathrm{\&Lambda;}}_l}^{+}y,{\hat{x}}_{\{l,...,N\}-{\mathrm{\&Lambda;}}_l}=0---\left(12\right)$

Below adopt concrete emulation experiment checking effect of the present invention:

It is the m sequence of 10kHz that FPGA produces jump frequency, is 2 test signal with signal generator generation degree of rarefication, and frequency component is 3kHz and 4kHz.After mixing, low-pass filtering, sampling and signal reconstruction, the original signal signal contains 3kHz and two frequencies of 4kHz, the waveform that the data point line forms as shown in Figure 6, frequency spectrum is as shown in Figure 7; Shown in.Reconstruction signal data point line waveform as shown in Figure 8, the reconstruction signal frequency spectrum is as shown in Figure 9.

By above-mentioned emulation experiment as seen:

1, the present invention utilizes the sparse characteristic of frequency-domain sparse signal spectrum, under the prerequisite that guarantees the signal recovery effects, reduced the sample rate of frequency-domain sparse signal, when the maximum of the contained frequency component of signal is larger, this effect is more obvious, and can make actual sample rate is Qwest's frequency much smaller than signal.

2, can reduce requirement to the speed of AD device, sampled data output is little, saves memory space, reduces costs, and is conducive to simultaneously the transmission of data.

Claims (6)

1. owe the method for sampling based on the sparse signal of compressed sensing, it is characterized in that: it is realized by following steps:

Step 1, employing are embedded in m sequencer generation m sequence in FPGA; And adopt FPGA synchronously to produce triggering signal;

Step 2, the m sequence that step 1 is produced adopt signal conditioning circuit to carry out signal condition, the m sequence after obtaining to nurse one's health;

After step 3, conditioning that step 2 is obtained, the m sequence adopts multiplier to carry out mixing with tested sparse signal, the acquisition mixed frequency signal;

Step 4, employing low pass filter carry out low-pass filtering to the mixed frequency signal that step 3 obtains, signal after the acquisition low-pass filtering;

Produce triggering signal in step 5, employing step 1 and trigger sample circuit, and after adopting sample circuit to the low-pass filtering of step 4 acquisition, signal is sampled, the acquisition sampled result;

Step 6, employing host computer carry out signal reconstruction to the sampled result that step 5 obtains, and obtain the reconstruction result of original tested sparse signal.

2. the sparse signal based on compressed sensing according to claim 1 is owed the method for sampling, it is characterized in that the concrete grammar that the employing host computer described in step 6 carries out signal reconstruction to the sampled result of step 5 acquisition is:

Steps A, according to formula:

H(s)＝H ₁(s)G(s)

Acquisition is mixed to the transfer function H (s) between sampling;

In formula: H ₁(s) be the transfer function of low pass filter, described low pass filter is second order Butterworth simulation low-pass filter;

G (s) is for being mixed to the continued product of operational amplification circuit transfer functions at different levels between sampling;

H ₁(s) be according to formula:

$H_1\left(s\right)=\frac{w_c^2}{s^2+\frac{w_c}{Q}s+w_c^2}$

Obtain;

In formula: w _cBe the cut-off frequency of low pass filter, Q is quality factor; S is-symbol variable;

G (s) is according to formula:

G(s)＝G ₁(s)G ₂(s)…G _n(s)

Obtain;

In formula: G ₁(s) be first operational amplification circuit transfer function; G ₂(s) be the transfer function of second operational amplification circuit; G _n(s) be the transfer function of n operational amplification circuit; N is positive integer;

Step B, employing Bilinear transformation method are carried out the discretization processing to the transfer function H (s) that is mixed between sampling that steps A obtains, obtain digital filter transfer function H (z), and try to achieve the impulse response h (n) of digital filter transfer function H (z);

Step C, the impulse response h (n) of the digital filter transfer function H in step B (z) is overturn, obtain upset h as a result _r(n);

Step D, with the m sequence P in step 1 _c(n) and the upset that obtains of step C h as a result _r(n) do convolution algorithm, obtain observing matrix Φ;

Step e, according to formula:

Θ＝ΦΨ

Obtain perception matrix Θ;

In formula: Ψ is the orthogonal basis matrix, and described Ψ is according to formula:

Ψ＝dftmtx(N)

Obtain; Described dftmtx be MATLAB software from tape function;

Step F, the perception matrix Θ that obtains according to step e realize signal reconstruction by orthogonal matching pursuit algorithm.

3. the sparse signal based on compressed sensing claimed in claim 1 is owed the implement device of the method for sampling, it is characterized in that: it comprises FPGA (15), modulate circuit (16), multiplier (11), low pass filter (12), sample circuit (13) and host computer (14);

Described FPGA (15) is embedded with the m sequencer, and described m sequencer is for generation of the m sequence;

The m sequence output of described FPGA (15) is connected with the signal input part of signal conditioning circuit (16); The signal output part of described signal conditioning circuit (16) is connected with a signal input part of multiplier (11); No. two signal input parts of described multiplier (11) are used for receiving tested sparse signal; The signal output part of described multiplier (11) is connected with the signal input part of low pass filter (12); The signal output part of described low pass filter (12) is connected with the signal input part of sample circuit (13); The signal output part of described sample circuit (13) is connected with the signal input part of host computer (14).

4. the sparse signal based on compressed sensing according to claim 3 is owed the implement device of the method for sampling, and the model that it is characterized in that FPGA (15) is EP2C8Q208.

5. the sparse signal based on compressed sensing according to claim 3 is owed the implement device of the method for sampling, it is characterized in that it is the chip realization of AD633 that multiplier (11) adopts model.

6. the sparse signal based on compressed sensing according to claim 3 is owed the implement device of the method for sampling, it is characterized in that low pass filter (12) is the second order Butterworth simulation low-pass filter that the chip of MAX275 is built for adopting model.

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