CN108158577A - A kind of low-power consumption electrocardiogram signal processing circuit and its method based on compressed sensing - Google Patents
A kind of low-power consumption electrocardiogram signal processing circuit and its method based on compressed sensing Download PDFInfo
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Abstract
The invention belongs to wearable device technical fields, it is related to a kind of low-power consumption electrocardiogram signal processing circuit based on compressed sensing, with sequence module occurs for clock frequency division module respectively, compress computing module, memory module and control module connection, sequence occurs module output terminal and is connect with compression calculating module input, electrocardiosignal is input to compression and calculates module input, it compresses computing module and the electrocardiogram (ECG) data of input is subjected to compaction algorithms using condensation matrix, compression computing module output terminal is connect with memory module, and operation result is stored to memory module, control module controls being turned on and off for modules by enable signal；The N of input × 1 is tieed up electrocardiogram (ECG) data and M × N-dimensional matrix of module generation occurs by compressing computing module progress compaction algorithms with sequence by the present invention, obtain the compression number of M dimensions, the circuit has smaller circuit area and relatively low power consumption, the compression to electrocardiosignal is completed to handle, while there is good compression performance.
Description
Technical field
The present invention relates to a kind of electrocardiogram signal processing circuit and its method, especially a kind of low-power consumption based on compressed sensing
Electrocardiogram signal processing circuit and its method belong to wearable device technical field.
Background technology
With the development of technology of Internet of things and wearable electronic product, electrocardio is believed using wearable device and wireless network
Number monitoring center is real-time transmitted to, to realize the real-time evaluation function of health states, just as current healthcare industry
A development trend.Typical wireless wearable device is broadly divided into four-stage to the acquisition of electrocardiosignal：1) sensor
Human ecg signal is converted into electric signal；2) analog electrical signal is converted into digital signal by analog-digital converter；3) signal processing
Circuit carries out digital signal processing and obtains the data for needing to transmit；4) radio-frequency module is by data wireless transmission to intelligent terminal etc.
Monitoring device.Research shows that (Chen F, Chandrakasan A P,V.“A signal-agnostic
compressed sensing acquisition system for wireless and implantable sensors.”
Custom Integrated Circuits Conference.San Jose,2010:1-4.), the power consumption of this four-stage accounts for
The proportion of total power consumption respectively may be about 17%, 5%, 5%, 73%.And the power consumption of fourth stage and the data of transmission in the unit interval
Amount is directly proportional, it is seen then that as can significantly compression needs the data transmitted, then can be effectively reduced the total power consumption of system.
Using compressed sensing (Compressed Sensing, CS) theory, pass through M × N (M<<N) the compression square of dimension
Battle array Φ, by the signal X of N-dimensional project to M dimension spatially obtain compressed signal Y (Y=Φ X).As long as X have it is openness, i.e., it is full
Sufficient X=Ψ θ (Ψ is the matrix of a N × N-dimensional, and θ is that matrix is tieed up in N × 1 that a most elements are 0), and Φ and Ψ right and wrong
Relevant, then can original signal X be reconstructed with maximum probability.Chen et al. proposes a kind of compressed sensing circuit using the theory
Structure (Chen F, Chandrakasan A P, Stojanovic V, et al. " Design and analysis of a
hardware-efficient compressed sensing architecture for data compression in
wireless sensors.”IEEE Journal of Solid-State Circuits,2012,47(3):744-756.),
Have the characteristics that power consumption is relatively low, compression ratio (N/M) is higher, but due to the parallel processing manner in its compression process, need M
Arithmetic element so that circuit area is larger, in addition is used to generate the pseudo-random sequence generator of condensation matrix Φ in the structure
Dynamic power consumption still has the space of optimization.
Traditional electrocardiogram signal processing circuit is with the presence of following problem：
1st, traditionally to reduce circuit area, static RAM is mostly replaced using pseudo-random sequence generator
(Static Random Access Memory, SRAM) generates condensation matrix, but the clock frequency of pseudo-random sequence generator
Must be consistent with the change frequency of formation sequence, cause its dynamic power consumption relatively high；
2nd, it since traditional compressed sensing circuit is when carrying out compaction algorithms Y=Φ X, using parallel processing mode, makes
Into the difficulty of multiplexing arithmetic element, cause to compress the use of a large amount of arithmetic elements of calculating section so that the face of condensation matrix module
Product is larger, reduces the portability of wearable device.
Invention content
The purpose of the present invention is be directed at present traditional electrocardiogram signal processing circuit there are the problem of, provide a kind of based on compression
The N of input × 1 is tieed up electrocardiogram (ECG) data and module generation occurs with sequence by the low-power consumption electrocardiogram signal processing circuit and its method of perception
M × N-dimensional matrix do matrix multiplication operation by compressing computing module, obtain the compressed data of M dimensions, and storage to storage mould
Block；The circuit has smaller circuit area and relatively low power consumption, completes the compression processing to electrocardiosignal, while have good
Compression performance.
For realization more than technical purpose, the technical scheme is that：A kind of low-power consumption electrocardio letter based on compressed sensing
Including clock frequency division module, sequence module, compression computing module, memory module and control module occur for number processing circuit,
It is characterized in that：Module, compression computing module, memory module and control module occur with sequence and connects respectively for the clock frequency division module
It connects, the output terminal that module occurs for generating the sequence of M × N-dimensional condensation matrix is connect with compressing the input terminal of computing module, the heart
Electric signal is input to the input terminal of compression computing module, and the N of input × 1 is tieed up electrocardiogram (ECG) data and utilizes M by the compression computing module
× N-dimensional condensation matrix data carry out compaction algorithms, and the output terminal of the compression computing module is connect with memory module, and by operation
As a result memory module is arrived in storage, and module occurs respectively with sequence for the control module, compression computing module is connected with memory module,
And pass through enable signal control sequence and being turned on and off for module, compression computing module and memory module occurs.
Further, the sequence occur module include the pseudo-random sequence generators of four outputs, latch, trigger,
XOR gate or with door, wherein, the first output sequence generator include first group of trigger, first group of trigger be several
The trigger being sequentially connected in series, the input D ends of first group of trigger are connect with the output terminal of XOR gate OX_1, described first group
The output Q ends of trigger are connect with the input D ends of latch one, the output Q ends generation pseudo-random sequence Z of the latch one1；
Second output sequence generator includes second group of trigger, and second group of trigger is the trigger that several are sequentially connected in series,
The input D ends of second group of trigger are connect with the output terminal of XOR gate OX_2, output Q ends generation pseudo-random sequence Z2；The
Three output sequence generators include third group trigger, the trigger that the third group trigger is sequentially connected in series for several, institute
The input D ends for stating third group trigger are connect with the output terminal of XOR gate OX_3, output Q ends generation pseudo-random sequence Z3；4th
Output sequence generator includes the 4th group of trigger, and the 4th group of trigger is the trigger that several are sequentially connected in series, described
The input D ends of 4th group of trigger are connect with the output terminal of XOR gate OX_4, and output Q terminates the input D ends into latch two, institute
It states latch two and exports Q ends generation pseudo-random sequence Z4；
The sequence Z1And Z3Access the input terminal of XOR gate OX_5, the output terminal formation sequence of the XOR gate OX_5
Z1_3, the sequence Z2And Z4Access the input terminal of XOR gate OX_6, the output terminal formation sequence Z of the XOR gate OX_62_4；
The sequence Z1_3Pass through trigger access and an input terminal of door, the sequence Z2_4Pass through the trigger of concatenation
With the access of latch three and another input terminal of door, the output terminal formation sequence Z with door；The sequence Z be length m 0,
1 sequence, and the probability of appearance 1 is 1/4 in sequence, using every M element of sequence Z as a row of matrix, generates a M × N
Condensation matrix Φ, wherein M × N≤m, N correspond to the number of each press cycles signal to be compressed, and M corresponds to compressed signal
Number.
Further, frequency can be f by the clock frequency division module clock division generation frequency be f/2, f/4 when
Clock, the clock frequency division module access the clock of frequency f/4 in the concatenation trigger of the pseudo-random sequence generator of four outputs,
And accessed in latch one and latch two by NOT gate, the clock of frequency f/2 is accessed in trigger, and pass through NOT gate and access
It, will be in the clock access trigger of frequency f in latch three.
Further, the compression computing module includes adder, and the heart is tieed up in the N of input × 1 by the compression computing module
Electric data carry out compaction algorithms using M × N-dimensional condensation matrix data and refer to the condensation matrix Φ of M × N-dimensional and N × 1 tieing up electrocardio
Matrix multiple, using serial computing mode, under the clock of frequency f, can be analyzed to every column data in matrix Φ respectively with N ×
Corresponding data are added again after being multiplied in 1 dimension electrocardio matrix, are exactly 1 since the element in condensation matrix Φ is not 0, entire operation
In only need to do add operation by adder, an input and the sequence of the adder occur module 2 and connect, another is inputted
It is connect with the register in memory module 4, the frequency f meets：f>M×fsample, wherein fsampleElectrocardiogram (ECG) data is tieed up for N × 1
Sample frequency.
Further, the memory module includes M register group, and memory module is a storage using addressing of address
Structure, after often reading or a data being written, corresponding reading address or write address add one automatically, are cached in the register group
The compressed data that compression computing module last time operation obtains, and the compressed data obtained with next operation is added.
Further, the control module includes two counters, and the control module utilizes during compression calculates
Two counters, are counted according to clock, so that it is determined that compression calculates state in which.
For realization more than technology mesh, the present invention also proposes a kind of low-power consumption ECG's data compression side based on compressed sensing
Method, it is characterized in that, include the following steps：
The clock division that frequency is f is generated the clock that frequency is f/2, f/4 by step 1 by clock frequency division module；
At different clock frequencies, module formation sequence Z occurs step 2 for the sequence, by every M member of sequence Z
A row of the element as matrix generate the condensation matrix Φ of a M × N；
Step 3 is by clock frequency division module, and under the clock of frequency f, the compression computing module utilizes condensation matrix
The electrocardiogram (ECG) data of input is carried out compression calculating, and compression result of calculation is stored into memory module by Φ.
Further, in the step 2, under f/4 clock frequencies, using four output pseudo-random sequence generator and
Latch generates four groups of pseudo-random sequence Z1、Z2、Z3、Z4；
Under f/2 clock frequencies, using XOR gate, by sequence Z1、Z2、Z3、Z4Formation sequence Z13And Z24；Wherein
Under f clock frequencies, using with door, by sequence Z1_3And Z2_4Formation sequence Z；Wherein Z=Z1_3 *&Z2_4 *, Z1_3 *It is
Using trigger by Z1_3Sequence after sampling, Z2_4 *It is to utilize trigger and latch three by Z2_4With respect to Z1_3 *Delay half week
Sequence after phase；
Further, in the step 3, under the clock of frequency f, the compression computing module receives sample frequency and is
fsampleThe dimension electrocardiogram (ECG) data of N × 1, and the condensation matrix Φ for M × N that module generates and N × 1 of input are occurred into for the sequence
Dimension electrocardiogram (ECG) data does matrix multiplication, using serial computing mode, successively operation M times, the compressed data caching that each operation obtains
Into the memory module, and the compressed data obtained with next operation is added, and obtains M dimension compressed datas, final to compress
In result of calculation storage to memory module.
Control module is further included, the control module determines compressometer during entire compression calculates using counter
Calculate state in which；Specially after carrying out M times calculating to each electrocardiogram (ECG) data, prbs_en signals are set to 0, pause sequence hair
The function of raw module before the arrival of next electrocardiogram (ECG) data, opens sequence and module occurs；By generating add_en and fifo_en
Signal control compression computing module and memory module are turned on and off；Before each press cycles start, a load is generated
Signal, control sequence occur module loading primary data and generate a sequence identical with last press cycles.
Compared with traditional electrocardiogram signal processing circuit, the present invention has the following advantages：
1) module occurs for sequence of the invention using four output pseudo-random sequence generators and latch with relatively low clock
Frequency generation compression calculates required condensation matrix；
2) compression computing module of the invention coordinates with memory module, by the way of serial computing, is multiplexed arithmetic element
(i.e. adder) so as to reduce the area of compression computing module, and then reduces the area of entire circuit, due to sequence of operations
1 probability occurred is 1/4 in Z, reduces the number of circuit counting to a certain extent, reduces the dynamic power consumption of circuit；
3) control module of the present invention controls opening or closing for each module using enable signal, and modules is made not work
When be closed, can preferably reduce the dynamic power consumption of entire circuit.
Description of the drawings
Fig. 1 is a kind of module map of low-power consumption electrocardiogram signal processing circuit based on compressed sensing provided by the invention.
Fig. 2 is the Organization Chart that module occurs for sequence in the present invention.
Fig. 3 is sequence Z of the present invention1、Z2、Z3、Z4、Z1_3And Z2_4Sequence diagram.
Fig. 4 is that computing module and the structure chart of memory module are compressed in the present invention.
Fig. 5 is the clock timing diagram that computing module is compressed in the present invention.
Fig. 6 is the specific implementation structure chart that module occurs for sequence in the present invention.
Fig. 7 (a), 7 (b) and 7 (c) are the control signal simulation figures of control module in the present invention.
Fig. 8 is the electrocardiosignal inputted in the present invention and the electrocardiosignal schematic diagram of reconstruct.
Reference sign：1-clock frequency division module；Module occurs for 2-sequence；3-compression computing module；4-storage
Module；5-control module.
Specific embodiment
With reference to specific drawings and examples, the invention will be further described.
According to Fig. 1, a kind of low-power consumption electrocardiogram signal processing circuit based on compressed sensing, including clock frequency division module
1st, module 2, compression computing module 3, memory module 4 and control module 5 occur for sequence, it is characterised in that：The clock division
Module 2 occurs respectively with sequence for module 1, compression computing module 3 is connect, and mould occurs for generating the sequence of M × N-dimensional condensation matrix
The output terminal of block 2 is connect with compressing the input terminal of computing module 3, and electrocardiosignal is input to the input terminal of compression computing module 3, institute
It states compression computing module 3 and electrocardiogram (ECG) data is tieed up into using M × N-dimensional condensation matrix data progress compaction algorithms in the N of input × 1, it is described
The output terminal of compression computing module 3 is connect with memory module 4, and operation result is stored to memory module 4, the control module
5 occur module 2, compression computing module 3 and memory module 4 with sequence respectively connects, and pass through enable signal control sequence and occur
Module 2, compression computing module 3 and memory module 4 are turned on and off.
Shown according to fig. 2, the pseudo-random sequence generator, latch, triggering that module 2 includes four outputs occur for the sequence
Device, XOR gate or with door, wherein, the first output sequence generator include first group of trigger, if first group of trigger is
The dry trigger being sequentially connected in series, the input D ends of first group of trigger are connect with the output terminal of XOR gate OX_1, and described the
The output Q ends of one group of trigger are connect with the input D ends of latch one, the output Q ends generation pseudorandom sequence of the latch one
Arrange Z1；Second output sequence generator includes second group of trigger, and second group of trigger is touched for what several were sequentially connected in series
Device is sent out, the input D ends of second group of trigger are connect with the output terminal of XOR gate OX_2, output Q ends generation pseudo-random sequence
Z2；Third output sequence generator includes third group trigger, and the third group trigger is the triggering that several are sequentially connected in series
Device, the input D ends of the third group trigger are connect with the output terminal of XOR gate OX_3, output Q ends generation pseudo-random sequence Z3；
4th output sequence generator includes the 4th group of trigger, and the 4th group of trigger is the trigger that several are sequentially connected in series,
The input D ends of the 4th group of trigger are connect with the output terminal of XOR gate OX_4, and output Q terminates the input D into latch two
End, the latch two export Q ends generation pseudo-random sequence Z4；
The sequence Z1And Z3Access the input terminal of XOR gate OX_5, the output terminal formation sequence of the XOR gate OX_5
Z1_3, the sequence Z2And Z4Access the input terminal of XOR gate OX_6, the output terminal formation sequence Z of the XOR gate OX_62_4；
The sequence Z1_3Pass through trigger access and an input terminal of door, the sequence Z2_4Pass through the trigger of concatenation
With the access of latch three and another input terminal of door, the output terminal formation sequence Z with door；The sequence Z be length m 0,
1 sequence, and the probability of appearance 1 is 1/4 in sequence, using every M element of sequence Z as a row of matrix, generates a M × N
Condensation matrix Φ, wherein M × N≤m, N correspond to the number of each press cycles signal to be compressed, and M corresponds to compressed signal
Number；
The clock division generation frequency that frequency can be f by the clock frequency division module 1 is the clock of f/2, f/4, when described
In the concatenation trigger of pseudo-random sequence generator that clock frequency division module 1 exports the clock access four of frequency f/4, and pass through non-
In door access latch one and latch two, the clock of frequency f/2 is accessed in trigger, and passes through NOT gate and accesses latch three
In, it will be in the clock access trigger of frequency f.
According to Fig. 4, the compression computing module 3 includes adder, and the computing module 3 that compresses is by N × 1 of input
Dimension electrocardiogram (ECG) data carries out compaction algorithms using M × N-dimensional condensation matrix data and refers to tie up the condensation matrix Φ of M × N-dimensional and N × 1
Electrocardio matrix multiple using serial computing mode, under the clock of frequency f, can be analyzed to every column data difference in matrix Φ
It ties up after corresponding data are multiplied in electrocardio matrix with N × 1 and is added again, be exactly 1 since the element in condensation matrix Φ is not 0, it is whole
Add operation need to be only done in a operation by adder, an input and the sequence of the adder occur module 2 and connect, another
A input is connect with the register in memory module 4；
As shown in figure 5, the frequency f meets：f>M×fsample, i.e. f is at least fsampleM times, wherein fsampleFor N ×
The sample frequency of 1 dimension electrocardiogram (ECG) data；
The memory module 4 includes M register group (MEM1、MEM2、…、MEMM), memory module 4 is one and utilizes ground
Location addressing storage organization, often read or be written a data after, it is corresponding reading address or write address automatically plus one, it is described to post
The obtained compressed data of caching compression computing module 3 last time operation in storage group, and with the compressed data that next operation obtains into
Row is added.
The control module 5 includes two counters, and the control module 5 utilizes two meters during compression calculates
Number device, is counted according to clock, so that it is determined that compression calculates state in which.
A kind of low-power consumption ECG's data compression method based on compressed sensing of the present invention, it is characterized in that, include the following steps：
The clock division that frequency is f is generated the clock that frequency is f/2, f/4 by step 1 by clock frequency division module 1；
At different clock frequencies, 2 formation sequence Z of module occurs step 2 for the sequence, by every M member of sequence Z
A row of the element as matrix generate the condensation matrix Φ of a M × N；
Under f/4 clock frequencies, using the pseudo-random sequence generator and latch of four outputs, four groups of pseudorandom sequences are generated
Arrange Z1、Z2、Z3、Z4；
Under f/2 clock frequencies, using XOR gate, by sequence Z1、Z2、Z3、Z4Formation sequence Z1_3And Z2_4；Wherein
Under f clock frequencies, using with door, by sequence Z1_3And Z2_4Formation sequence Z；Wherein Z=Z1_3 *&Z2_4 *, Z1_3 *It is
Using trigger by Z1_3Sequence after sampling, Z2_4 *It is to utilize trigger and latch three by Z2_4With respect to Z1_3 *Delay half week
Sequence after phase；
The sequence occurs the clock of the three kinds of frequencies cooperation that module 2 is generated by clock frequency division module 1 and generates variation frequency
0, the 1 sequence Z that rate is f, length is m, implementation method are as described below：
1., for an electrocardiosignal compression process (by N-dimensional Signal Compression be M dimensional signals), condensation matrix needs M
× N number of matrix element, primitive polynomial h is determined according to the value of M × N0×1+…+hn-2x(n-2)+hn-1x(n-1)+hnxn(M×N≤m
=2n- 1), wherein h0And hnIt is always 1, h1、h2、…、hn-1It is 0 or 1；
2., a primitive polynomial can be write as n × n dimension matrix form：
Wherein t1,1、…、t1,nCorresponding h1、h2、…、hn.To obtain 4 group 0,1 sequence Z1、Z2、Z3、Z4, W=mod need to be calculated
(T×T×T×T,2)：
Mod (A, 2) represents the element in matrix A determining that four output pseudo-random sequences occur according to W respectively to 2 modulus
The connection relation of each trigger in device：
Wherein 1≤i≤n, so that it is determined that the circuit structure of module 2 occurs for sequence as shown in Fig. 2, circuit is divided by dotted line
Three parts, the clock frequency of this three parts are respectively f/4, f/2 and f, and the company of each d type flip flop in figure under f/4 clock frequencies
It connects relationship not draw, can be determined according to formula (3)；
3., step 1. in n determined according to the value of M × N, n=4r+k (1≤k can be write as arbitrary n (n >=7)
≤ 4, r >=1), the part of dotted line frame is determined according to k values in Fig. 2：As k=1, only trigger DFF_4r+1；As k=2,
Only trigger DFF_4r+1 and trigger DFF_4r+2；As k=3, only trigger DFF_4r+1, trigger DFF_4r+2
With trigger DFF_4r+3；As k=4,4 triggers have, trigger DFF_4r+1, trigger DFF_4r+2, trigger
DFF_4r+3 and trigger DFF_4r+4.Z2、Z3And the input of two latch2 of input and latch of one latch1 of latch
It is determined by k：
Due to adding one latch1 of latch and latch two latch2, Z3And Z4Change in the low level of clock, this
Sample Z1、Z2、Z3、Z4、Z1_3And Z2_4Waveform it is as shown in Figure 3.From the figure 3, it may be seen that Z1_3And Z2_4Change frequency be f/2.Equally
Ground, it is f, and the sequence length of Z is still m that the presence of three latch3 of latch, which so that Z change frequencies accelerate,.Since sequence Z is to use
It is generated with logic, therefore the probability of appearance 1 is 1/4 in Z.Module 2 occurs for sequence with regard to being given birth to using the clock compared with low rate in this way
It is f into change frequency, sequence length is 0,1 sequence of m.For sequence Z*, element a1、…、am, by a1、…、aMAs
The first row of condensation matrix, aM+1、…、a2MAs the secondary series of condensation matrix, and so on, this completes condensation matrixes
Generation.
Step 3 is by clock frequency division module 1, and under the clock of frequency f, the compression computing module 3, which utilizes, compresses square
The electrocardiogram (ECG) data of input is carried out compression calculating, and compression result of calculation is stored into memory module 4 by battle array Φ；
Under the clock of frequency f, it is f that the compression computing module 3, which receives sample frequency,sampleThe dimension electrocardiogram (ECG) data of N × 1,
And N × 1 of the condensation matrix Φ for the M × N for generating sequence generation module 2 and input ties up electrocardiogram (ECG) data and does matrix multiplication,
Using serial computing mode, successively operation M times, the compressed data that each operation obtains is cached in the memory module 4, and with
The compressed data that next operation obtains is added, and obtains M dimension compressed datas, final to compress result of calculation storage to memory module
In 4；
The compression computing module 3 coordinates with memory module 4, by the way of serial computing, to be multiplexed arithmetic element, from
And reduce the area of circuit so that the structure is more suitable for low power consuming devices, compresses computing module 3 and the knot of memory module 4
Composition is as shown in Figure 4；Matrix multiplication operation can be write as such as formula (8)：
Using faster clock, (its frequency is f, and f is at least electrocardiosignal and adopts after first electrocardiogram (ECG) data is received
Sample frequency fsampleM times) calculate Φ respectively1,1×X1+0、Φ2,1×X1+0、…、ΦM,1×X1+ 0, and result is stored respectively
To the MEM in memory module 41、MEM2、…、MEMMIn register group, each register group includes 14 registers, when receiving
Φ is calculated respectively using the clock that frequency is f after second electrocardiogram (ECG) data1,2×X2+MEM1、Φ2,2×X2+MEM2、…、ΦM,2×
X2+MEMMAnd store, and so on, thereby realize the serial computing of electrocardiogram (ECG) data.Additionally, due to the member in condensation matrix Φ
It is exactly 1 (Φ that element, which is not 0,1,1、Φ2,1、…、ΦM,1The sequence a that module 2 generates occurs for corresponding sequence1、a2、…、aM, Φ1,2、
Φ2,2、…、ΦM,2Corresponding sequence aM+1、aM+2、…、a2M...), therefore need to only do add operation.
Computing module 3 is compressed with the circuit structure of memory module 4 as shown in figure 4, an input of adder is according to sequence
Row occur module 2 generate matrix determine (true electrocardiogram (ECG) data is inputted when being 1, be 0 when input data be 0), another
Input is the data of memory module 4, and the probability occurred due to 1 is 1/4, reduces the number of circuit counting, drop to a certain extent
The low dynamic power consumption of circuit；
Memory module 4 is a storage organization using addressing of address, corresponding after often reading or a data being written
It reads address or write address adds one automatically.This serial computing mode is in frequency f (f>M×fsample) clock under operation M times, and
Result cache to the memory module 4 for next sampled data arrives when calculate and use, although opposite parallel computation side
Formula (when receiving data, while operation M times), operation frequency has become faster by fsampleBecome f, but the opposite still very littles, and can of f
With multiplex logic units, therefore while low-power consumption is ensured, greatly reduce circuit area.
As shown in fig. 7, the control module 5 controls the switch of each module using enable signal, it is entire preferably to reduce
The dynamic power consumption of circuit；During entire compression calculates, counter (two counters M_counter and N_ are utilized
Counter) determine compression calculate state in which, if such as M_counter=c, N_counter=d, illustrate currently counting
Calculate Φc,d×Xd(1≤c≤M, 1≤d≤N)；Specially after carrying out M times calculating to each electrocardiogram (ECG) data, by prbs_en signals
It sets to 0, the function of module 2 occurs for pause sequence, before the arrival of next electrocardiogram (ECG) data, opens sequence and module 2 occurs；Pass through generation
Add_en and fifo_en signals control compression computing module 3 and memory module 4 are turned on and off；It is opened in each press cycles
Before beginning, a load signal is generated, it is identical with last press cycles that the loading primary data of module 2 generation one occurs for control sequence
Sequence；During to ensure that load signals are effective, sequence occurs module 2 and is in opening, to n-th in each press cycles
After electrocardiogram (ECG) data operation, prbs_en signals can't be set to 0.
Every 256 data boil down tos, 64 data instances chosen below are further described, according to Fig. 6, N here
=256, M=64 select primitive polynomial as 1+x14+x15, sequence length m is 32767=215- 1, more than 256 × 64.To this
Primitive polynomial is calculated：
From (9) formula DFF_5/D=DFF_1/Q；……；DFF_15/D=DFF_11/Q.So that it is determined that f/ in module (2) occurs for sequence
The connection relation of each trigger under 4 clock frequencies, wherein, DFF_1, DFF_5, DFF_9 and DFF_13 are first group of trigger,
DFF_2, DFF_6, DFF_10 and DFF_14 are second group of trigger, and DFF_3, DFF_7, DFF_11 and DFF_15 are touched for third group
Device is sent out, DFF_4, DFF_8 and DFF_12 are the 4th group of trigger；
The generation waveform that control module 5 controls signal is illustrated in figure 7, the control module 5 is to each electrocardiogram (ECG) data
It carries out 64 times after calculating, prbs_en signals is set to 0, the function of module 2 occurs for pause sequence, arrives in next electrocardiogram (ECG) data
Before, it opens sequence and module 2 occurs；Similar generation add_en and fifo_en signal control compression computing module 3 and memory module
4 opening and closing.In addition before each press cycles start, a load signal is generated, control sequence occurs module 2 and loads
Primary data generates 0,1 sequence new but identical with last press cycles；During to ensure that load signals are effective, mould occurs for sequence
Block 2 is in opening, in each press cycles to the 256th electrocardiogram (ECG) data operation after, prbs_en signals can't
It sets to 0.
To verify the correctness of circuit function, by compressed data, in Matlab using Bayesian learning algorithm into
Row reconstruct, original signal are as shown in Figure 8 with reconstruction signal.Utilize root-mean-square error percentage (percentage root-
Mean-squared difference, PRD) it is lost to quantify the information of bio signal：
Wherein, x (n) represents original signal,Represent reconstruction signal.Bayesian learning algorithm reconstruct letter is calculated
Number PRD=1.32%, to being rated " Very good " for reconstruction signal quality.
A kind of low-power consumption electrocardiogram signal processing circuit based on compressed sensing of the present invention uses DC (Design
Compiler it) is integrated, the gross area of the circuit of the present invention is obtained by comprehensive report, then by the gross area divided by call member
The area of two input of minimum and gate cell is to get the quantity of minimum logic gate used to the present invention in component inventory.With it is existing
Signal processing circuit is intuitively compared, and using identical technique, is realized of the present invention a kind of based on compressed sensing
The quantity that low-power consumption electrocardiogram signal processing circuit used resource is equivalent to minimum logic gate is 9256, and uses PTPX
(PrimeTime PX) tool emulates its power consumption, and power consumption result is 0.813 μ W, and existing electrocardiogram signal processing circuit passes through DC institutes
The logic gate quantity and power consumption of report are respectively 11214 and 1.172 μ W, more of the invention therewith to divide on logic gate number and power consumption
17.46% and 30.6% is not reduced.
Compared to existing method, the present invention has following improve：Utilize four output pseudo-random sequence generators and latch
Compression is generated with relatively low clock frequency and calculates required condensation matrix, and pass through multiplexing arithmetic logic so that circuit area reduces,
While low-power consumption requirement is met, circuit area is reduced, can preferably adapt to the requirement of wearable device.
Above to the present invention and embodiments thereof be described, this describe it is no restricted, it is attached it is shown in figure also only
It is one of embodiments of the present invention, practical structures are not limited thereto.All in all if those of ordinary skill in the art
It is enlightened by it, without departing from the spirit of the invention, not inventively designed similar to the technical solution
Frame mode and embodiment, are within the scope of protection of the invention.
Claims (10)
1. including clock frequency division module (1), sequence mould occurs for a kind of low-power consumption electrocardiogram signal processing circuit based on compressed sensing
Block (2), compression computing module (3), memory module (4) and control module (5), it is characterised in that：The clock frequency division module
(1) module (2), compression computing module (3), memory module (4) and control module (5) occur with sequence respectively to connect, for producing
The output terminal that module (2) occurs for the sequence of raw M × N-dimensional condensation matrix is connect with the input terminal of compression computing module (3), electrocardio letter
Number it is input to the input terminal of compression computing module (3), the compression computing module (3) utilizes the dimension electrocardiogram (ECG) data of the N of input × 1
M × N-dimensional condensation matrix data carry out compaction algorithms, and the output terminal of the compression computing module (3) is connect with memory module (4),
And by operation result storage to memory module (4), module (2), compression calculating mould occur respectively with sequence for the control module (5)
Block (3) and memory module (4) connection, and pass through enable signal control sequence and module (2), compression computing module (3) occurs and deposits
Storage module (4) is turned on and off.
2. a kind of low-power consumption electrocardiogram signal processing circuit based on compressed sensing according to claim 1, it is characterised in that：
The sequence occur pseudo-random sequence generator of the module (2) including four outputs, latch, trigger, XOR gate or with door,
In, the first output sequence generator includes first group of trigger, and first group of trigger is the triggering that several are sequentially connected in series
Device, the input D ends of first group of trigger are connect with the output terminal of XOR gate OX_1, the output Q of first group of trigger
End is connect with the input D ends of latch one, the output Q ends generation pseudo-random sequence Z of the latch one1；Second output sequence
Generator includes second group of trigger, and second group of trigger is the trigger that several are sequentially connected in series, and described second group is touched
The input D ends of hair device are connect with the output terminal of XOR gate OX_2, output Q ends generation pseudo-random sequence Z2；Third output sequence is sent out
Raw device includes third group trigger, and the third group trigger is the trigger that several are sequentially connected in series, the third group triggering
The input D ends of device are connect with the output terminal of XOR gate OX_3, output Q ends generation pseudo-random sequence Z3；4th output sequence occurs
Device includes the 4th group of trigger, the trigger that the 4th group of trigger is sequentially connected in series for several, the 4th group of trigger
Input D ends connect with the output terminal of XOR gate OX_4, output Q terminates input D ends into latch two, and the latch two is defeated
Go out Q ends generation pseudo-random sequence Z4；
The sequence Z1And Z3Access the input terminal of XOR gate OX_5, the output terminal formation sequence Z of the XOR gate OX_51_3, institute
State sequence Z2And Z4Access the input terminal of XOR gate OX_6, the output terminal formation sequence Z of the XOR gate OX_62_4；
The sequence Z1_3Pass through trigger access and an input terminal of door, the sequence Z2_4Pass through the trigger and lock of concatenation
Storage three accesses another input terminal with door, the output terminal formation sequence Z with door；
The sequence Z is 0,1 sequence of length m, and occurs 1 probability in sequence for 1/4, using every M element of sequence Z as
One row of matrix generate the condensation matrix Φ of a M × N, and wherein M × N≤m, N correspond to each press cycles signal to be compressed
Number, M correspond to compressed signal number.
3. a kind of low-power consumption electrocardiogram signal processing circuit based on compressed sensing according to claim 2, it is characterised in that：
The clock division that frequency can be f by the clock frequency division module (1) generates the clock that frequency is f/2, f/4, the clock division
In the concatenation trigger of pseudo-random sequence generator that module (1) exports the clock access four of frequency f/4, and pass through NOT gate and connect
Enter in latch one and latch two, the clock of frequency f/2 accessed in trigger, and accessed in latch three by NOT gate,
It will be in the clock access trigger of frequency f.
4. a kind of low-power consumption electrocardiogram signal processing circuit based on compressed sensing according to claim 1, it is characterised in that：
The compression computing module (3) includes adder, and the N of input × 1 is tieed up electrocardiogram (ECG) data and utilizes M by the compression computing module (3)
× N-dimensional condensation matrix data carry out compaction algorithms and refer to the condensation matrix Φ of M × N-dimensional and N × 1 tieing up electrocardio matrix multiple, adopt
With serial computing mode, under the clock of frequency f, the every column data that can be analyzed in matrix Φ ties up electrocardio matrix with N × 1 respectively
In corresponding data be multiplied after be added again, be exactly 1 since the element in condensation matrix Φ is not 0, need to pass through in entire operation
Adder does add operation, and an input and the sequence of the adder occur module (2) and connect, another input and storage mould
Register connection in block (4), the frequency f meet：f>M×fsample, wherein fsampleThe sampling of electrocardiogram (ECG) data is tieed up for N × 1
Frequency.
5. a kind of low-power consumption electrocardiogram signal processing circuit based on compressed sensing according to claim 4, it is characterised in that：
The memory module (4) includes M register group, and memory module (4) is a storage organization using addressing of address, is often read
Or after one data of write-in, corresponding reading address or write address add one automatically, and caching compression in the register group calculates mould
The compressed data that block (3) last time operation obtains, and the compressed data obtained with next operation is added.
6. a kind of low-power consumption electrocardiogram signal processing circuit based on compressed sensing according to claim 1, it is characterised in that：
The control module (5) includes two counters, and the control module (5) is during compression calculates, using two counters,
It is counted according to clock, so that it is determined that compression calculates state in which.
7. a kind of low-power consumption ECG's data compression method based on compressed sensing, it is characterized in that, include the following steps：
The clock division that frequency is f is generated the clock that frequency is f/2, f/4 by step 1 by clock frequency division module (1)；
At different clock frequencies, module (2) formation sequence Z occurs step 2 for the sequence, by every M element of sequence Z
As a row of matrix, the condensation matrix Φ of a M × N is generated；
Step 3 is by clock frequency division module (1), and under the clock of frequency f, the compression computing module (3), which utilizes, compresses square
The electrocardiogram (ECG) data of input is carried out compression calculating, and compression result of calculation is stored into memory module (4) by battle array Φ.
8. a kind of low-power consumption ECG's data compression method based on compressed sensing according to claim 7, which is characterized in that
In the step 2, under f/4 clock frequencies, using the pseudo-random sequence generator and latch of four outputs, four groups of puppets are generated
Random sequence Z1、Z2、Z3、Z4；
Under f/2 clock frequencies, using XOR gate, by sequence Z1、Z2、Z3、Z4Formation sequence Z1_3And Z2_4；Wherein Z1_3=Z1⊕
Z3, Z2_4=Z2⊕Z4；
Under f clock frequencies, using with door, by sequence Z1_3And Z2_4Formation sequence Z；Wherein Z=Z1_3 *&Z2_4 *, Z1_3 *It is to utilize
Trigger is by Z1_3Sequence after sampling, Z2_4 *It is to utilize trigger and latch three by Z2_4With respect to Z1_3 *After postponing half period
Sequence.
9. a kind of low-power consumption ECG's data compression method based on compressed sensing according to claim 7, which is characterized in that
In the step 3, under the clock of frequency f, it is f that the compression computing module (3), which receives sample frequency,sampleThe dimension heart of N × 1
Electric data, and the condensation matrix Φ for M × N that sequence generation module (2) is generated and the N of input × 1 are tieed up electrocardiogram (ECG) data and are done
Matrix multiplication, using serial computing mode, successively operation M times, the compressed data that each operation obtains is cached to the storage mould
In block (4), and the compressed data obtained with next operation is added, and obtains M dimension compressed datas, and final result of calculation of compressing is deposited
It stores up in memory module (4).
10. a kind of low-power consumption ECG's data compression method based on compressed sensing according to claim 7, feature exist
In further including control module (5), the control module (5) determines compressometer during entire compression calculates using counter
Calculate state in which；Specially after carrying out M times calculating to each electrocardiogram (ECG) data, prbs_en signals are set to 0, pause sequence hair
The function of raw module (2) before the arrival of next electrocardiogram (ECG) data, opens sequence and module (2) occurs；By generate add_en and
Fifo_en signals control compression computing module (3) and memory module (4) is turned on and off；Before each press cycles start,
A load signal is generated, it is identical with last press cycles that module (2) loading primary data generation one occurs for control sequence
Sequence.
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| CN109938696A (en) * | 2019-03-22 | 2019-06-28 | 江南大学 | Electroneurographic signal compressed sensing processing method and circuit |
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