CN206727986U - seismic data compression device based on FPGA - Google Patents
seismic data compression device based on FPGA Download PDFInfo
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- CN206727986U CN206727986U CN201720417394.XU CN201720417394U CN206727986U CN 206727986 U CN206727986 U CN 206727986U CN 201720417394 U CN201720417394 U CN 201720417394U CN 206727986 U CN206727986 U CN 206727986U
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Abstract
It the utility model is related to a kind of seismic data compression device based on FPGA, the general layout for the signal transition coding compression that the present apparatus breaks traditions, according to compressive sensing theory, first to the geological data wavelet transformation rarefaction representation of collection, then calculation matrix is generated according to matrix construction principle, dimension-reduction treatment finally is done to sparse coefficient using calculation matrix, so as to obtain compressed data.For geological data in time-domain it is not sparse, and random measurement matrix hardware realizes the problem of difficult and experimental result is not sufficiently stable, the present apparatus realizes one-dimensional wavelet transform, chaos sequence calculation matrix construction and vectorial dimensionality reduction scheduling algorithm on FPGA, the compression to geological data is realized, effectively improves seismic detector data transmission capabilities.The present apparatus complete 256 sampled points to 64 sampled points compression when, time as little as 0.01s used in compression, reconstructed error is less than 0.05.
Description
Technical field
The utility model belongs to seismic data process field, is related to a kind of seismic data compression device based on FPGA.
Background technology
The seismographic real-time data transmission technology of untethered memory-type, it is to influence the main factor that it develops.With earthquake
Exploration deepen continuously so that seismic exploration data be in explosive increase, to untethered it is seismographic sample and be wirelessly transferred speed,
The memory capacity of memory and the processing speed of computer bring stern challenge.It is rational by being carried out to geological data
Compression is handled, and can improve real-time processing speed, improves seismic detector wireless communication data transmission performance.Therefore, geological data pressure
The hardware of compression method is implemented as the problem there is an urgent need to research.
Existing seismic data compression method is broadly divided into two big type of Lossless Compression and lossy compression method.Lossless data compression
Method mainly removes the redundancy in initial data, and initial data is described using code word as few as possible.Damage data compression side
Method mainly utilizes certain orthogonal transformation, and initial data is transformed into frequency domain data, and frequency domain data is quantified, so
Entropy code is carried out to the data after quantization afterwards.
CN105512120A is disclosed《A kind of seismic data compression method, compression storage organization and method of random access》,
The compression method carries out Lossless Compression to earthquake trace header data and earthquake number of samples evidence is entered respectively according to the characteristics of geological data
Row lossy compression method.In trace header compression step, the attribute of each data item in the trace header of a trace header description information recording compressed is utilized
The information such as space size shared by definition and trace header description information itself；In sampling point compression step, calculate seismic channel characteristic value and
The characteristic vector of various points of data, and represent various points of data using seismic channel characteristic value and the characteristic vector of various points of data.
Memory space has been saved for the processing of mass seismic data, has reduced hardware cost, improves operating efficiency.
CN104378118A discloses one kind《Efficient self-adapted geological data stream Lossless Compression and decompression method》, pass through
Using coded system by the adaptive byte of boil down to 1 of 24 original 3 bytewises of sampled data or 2 bytes or 3 bytes or
Person and low volume data are converted into 4 bytes；Before data compression, the byte first according to needed for being carried out the numerical values recited of initial data
Judge, be 1 byte after the data compression in 0~63 and -64~-1 section, the data compression in 64~8191 and -8192~-65 sections
It is 2 bytes afterwards, is 3 bytes after the data compression method operation in 8192~104875 and -104876~-8193 sections, takes word
Section is with original identical, and in addition to above data area, other 24 other integers for having symbol integer data to represent are passing through
4 byte representations are needed to use after compression algorithm operation.This method has a large amount of saving memory spaces, significantly improves data transfer
The advantages of efficiency.
Although above-mentioned prior art can be used for seismic data compression, these data compression schemes cannot be used for data and adopt
The collection stage, it is impossible to geological data is reduced from root；And either lossy compression method or Lossless Compression, it is necessary to complete
Geological data is operated, and can not be to a small amount of several sampled-data processings, and compression process is mainly by upper computer software processing, nothing
Method is to data flow hardware configuration Real Time Compression.
The content of the invention
The purpose of this utility model is that the deficiency for above-mentioned existing earthquake compress technique, is managed with reference to compressed sensing
By a kind of seismic data compression device based on FPGA of proposition.
Compressive sensing theory is thought：If signal is sparse either sparse in some transform domain, then signal can be with
Primary signal is transformed to low-dimensional signal by calculation matrix, then primary signal is obtained by restructing algorithm Optimization Solution.This practicality
New device mainly realizes compression on FPGA (slave computer), when needing to use partial data, transfers data to PC ends
(host computer) decompresses.
A kind of seismic data compression device based on FPGA, is through register a7, WAVELET TRANSFORM MODULUS by data input module 1
Block 2, register b8, compression measurement module 4, register d10 and data outputting module 5 connect；Control logic module 6 respectively with number
According to input module 1, register a7, wavelet transformation module 2, register b8, calculation matrix generation module 3, compression measurement module 4,
Register d10 and data outputting module 5 connect；Calculation matrix generation module 3 is connected structure through register c9 with compression measurement module 4
Into.
The wavelet transformation module 2 is made up of input module, wavelet filter, memory module and output module, wherein
Memory module is made up of RAM1, RAM2, internal RAM 3 and parameter RAM4；The input module is filtered through parameter RAM14 and small echo
Ripple device connects；Input module connects through RAM1 or RAM2, wavelet filter, RAM3 and output module；Control logic module 6 is distinguished
It is connected with input module, RAM1, RAM2, RAM3 and output module.
Compared with prior art, the beneficial effects of the utility model are：
1st, the present apparatus realizes wavelet transformation on FPGA, is easy to data for geological data in the sparse characteristic of wavelet field
Compression and reconstruct；Calculation matrix is generated using Logistic chaos sequences, overcomes the difficult realization of random matrix hardware and certainty
Matrix influences the problem of reconstruction accuracy.
2nd, the present apparatus is used in the acquisition phase of geological data, and geological data amount is reduced from source, alleviates earthquake number
According to transmission pressure, 256 sampled points are handled per second compression, low delay compression, when compression ratio is 0.25, pressure are carried out to geological data
The as little as 0.01s of time used in contracting, reconstructed error are less than 0.05.
Brief description of the drawings
Fig. 1 data compression the general frames；
Fig. 2 wavelet decomposition structure charts；
Wavelet transformation structure charts of the Fig. 3 based on layered shaping；
Fig. 4 wavelet filter internal element figures；
Fig. 5 generates calculation matrix structure chart；
Fig. 6 matrix generator schematic diagrames；
Fig. 7 compresses operation result of measurement structure chart.
In figure：1. the calculation matrix generation module 4. of 2. wavelet transformation module of data input module 3. compresses measurement module
5. the register d of 9. register c of data outputting module 6. control logic module, 7. register a, 8. register b 10..
Embodiment
Describe specific embodiment of the present utility model in detail below in conjunction with the accompanying drawings.
A kind of seismic data compression device based on FPGA, including data input module 1, wavelet transformation module 2, measurement square
Battle array generation module 3, compression measurement module 4, data outputting module 5, control logic module 6, register a7, register b8, deposit
Device c9 and register d10；
The data input module 1 is through register a7, wavelet transformation module 2, register b8, compression measurement module 4, deposit
Device d10 and data outputting module 5 connect；
The calculation matrix generation module 3 is connected through register c9 with compression measurement module 4；
The control logic module respectively with data input module 1, register a7, wavelet transformation module 2, register b8,
Calculation matrix generation module 3, compression measurement module 4, register d10 and data outputting module 5 connect.
The wavelet transformation module 2 is by input module, wavelet filter, memory module, output module and logic control
Unit is formed, and wherein memory module is made up of RAM1, RAM2, internal RAM 3 and parameter RAM4；The input module is through parameter
RAM14 is connected with wavelet filter；Input module connects through RAM1 or RAM2, wavelet filter, RAM3 and output module；Control
Logic module is connected with input module, RAM1, RAM2, RAM3 and output module respectively.
The data input module 1 by the sampling point cache that seismic detector gathers to register a7, as input to be compressed
Data.
The wavelet transformation module 2 carries out symmetric extension, data and filtering after continuation to input data in register a7
Device coefficient convolution, and to convolution results down-sampling, obtain sparse coefficient, data buffer storage to register b8.
The calculation matrix generation module 3 is mainly made up of matrix generator and threshold determination unit, according to the square provided
Battle array aufbauprinciple and matrix element initial value generator matrix element, and matrix element is judged, it is -1 and 1 to obtain element
Pseudo random matrix, this calculation matrix is cached to register c9.
Data in the compression receiving register b8 of measurement module 4 and register c9, it will be pressed by the accumulator in IP kernel
The intermediate variable of compression process is buffered in register d10, then is transmitted compressed data to PC by data outputting module 5.
The implementation of the present apparatus is as follows：
A, in FPGA, the sampled point of 256 seismic detector collections is cached first to register a7, as input to be compressed
Data；
B, due to being not sparse in geological data time-domain, so reading the data in register a7, it is stored in RAM1
Into wavelet transformation module 2, realize that multilayer is decomposed, improve the compressibility (sparse) of data；
C, the wavelet transformation module 2 in FPGA, symmetric extension is carried out to input data, the data after continuation and wave filter system
Number convolution, and to convolution results down-sampling, obtain sparse coefficient, data buffer storage to register b8；
D, go out to compress the calculation matrix used with FPGA fabric；The core of calculation matrix generation module 3 be matrix generator and
Threshold determination unit, according to the matrix construction principle and matrix element initial value provided, to generate matrix element, and to matrix element
Element is judged, finally gives the pseudo random matrix that element is -1 and 1, this calculation matrix is cached into register c9；
E, the data in readout register b8 and register c9, data input is to compression measurement module 4, by compression process
Intermediate variable is buffered in register d10, finally exports obtained compressed data；It is substantially exactly to realize to compress measurement module
It is the dot-product operation of matrix and vector, the main accumulator used in IP kernel is realized.
The fpga chip for the xc6slx25 models that the present apparatus is produced using Xilinx companies, device mainly realize three algorithms
Function：Wavelet transform, generation calculation matrix and calculation matrix compress to sparse coefficient to be observed, as shown in figure 1, with reference to
Accompanying drawing is further described in detail：
1st, wavelet transformation module
1. theory of wavelet transformation
Because wavelet basis and seismic signal have similitude, so after carrying out wavelet transformation to seismic signal, what is obtained is small
Wave system number has openness well.It is public to the discrete wavelet multiresolution analysis of single track microseismic signals, Mallet arthmetic statements
Formula is：
In formula, Cj,k、Dj,kIt is primary signal respectively in yardstick 2-jIt is lower to decompose obtained low frequency component and high fdrequency component, h (m-
2k), g (m-2k) is the coefficient of low pass and high-pass filter respectively.
2. wavelet transformation FPGA is realized
The present apparatus does four decomposition to 256 sampled points with " db1 " wavelet basis, according to wavelet decomposition principle, treats sparse
Low frequency component of the data after a wavelet decomposition, as the input of next wavelet decomposition, by that analogy, until needed for completion
Decomposition order obtain it is final sparse, commonly use wavelet decomposition structure drawing of device as shown in Fig. 2 the gathered data of input first
By first time wavelet decomposition module, the low frequency component for decomposing to obtain is passed to second of small echo as second of input decomposed
Decomposing module carries out next layer of decomposition, by that analogy to the 4th decomposition, exports the 4th low frequency component and high frequency decomposed
Component.If directly according to decomposition principle step by step realize, with increasing for Decomposition order, speed with regard to it is slower and slower, it is necessary to deposit
Store up space and become big, the resource of occupancy is more.So the present apparatus is realized, such as according to decomposition principle step by step using register multiplexing structure
Shown in Fig. 3, mainly include：Input module, wavelet filter, memory module and output module.Input module：Complete data
Receive, including need data to be processed and configuration ripple device coefficient, Decomposition order, signal length, realize RAM1 or RAM2 selection
Operation；The address space specified in filter coefficient, Decomposition order, signal length and parameter RAM4, in case subsequent data is handled
During call；Output module：Output control logic is realized, judges whether current system is completed most directly to export data；It is small
Wave filter：Internal element is as shown in figure 4, realize symmetric extension, convolution and down-sampling computing；Memory module：Be respectively RAM1,
RAM2, internal RAM 3 and parameter RAM4.
Wavelet transformation module workflow：First, the parameter for configuring system is received to be stored in parameter RAM4.Then,
Start data filtering processing.Input data is stored in RAM1, and the low frequency of wavelet coefficient is obtained after first layer wavelet decomposition
Part C1 and HFS D1 are stored in RAM2, low level storage C1, high position storage D1；During second layer wavelet decomposition, by RAM2
In data C1 be sent into wavelet filter in handled, the low frequency part C2 and height of the wavelet coefficient obtained by wavelet decomposition
Frequency part D2 is stored in RAM1, low level storage C2, high position storage D2, and so on, until decomposing and completing for four times.RAM1 and
The buffering method converted back and forth between RAM2, realized by alternative selector.In order to shorten processing delay, it may be considered that will be small
The data handling procedure and data output process of ripple filtering merge, i.e., are designed using 2 level production lines, whole system is divided into：It is defeated
Enter, wavelet filtering and output.Due to reducing flowing water depth, allow result output and data processing in same one-level stream
Carried out on waterline, so as to reduce system delay.Still further aspect also saves the hardware resource for exporting buffering, simplifies
Hardware design, but the intermediate data of a deposit space storage processing must be opened up in addition, internal RAM 3 deposits data processing
Intermediate data in journey.Third layer resolution process process is similar with first layer, and the 4th layer of decomposition is similar with the second layer.
2nd, calculation matrix generation module
1. calculation matrix aufbauprinciple
Shown in known Logistic chaos systems such as formula (2)：
As λ=2.0, the sequence { a as caused by the Logistic systemsnMeet that Bernoulli is distributed, while also meet
RIP properties, the then sequence { a as caused by Logistic systemsnCan be as CS calculation matrix.
Random sequence { the u as caused by the Logistic systemsnBy formula (3) sign function it is mapped to sequence { an,
The correlation distribution of frequency expansion sequence is mapped according to Logistic, takes λ=2.0, u0=0.37, mixed by the Logistic
Ignorant system produces chaos sequence { un, sequence length is M × N-1；Then by the chaos sequence { u of generationnPass through formula (3)
Sign function is mapped to sequence { an}；Finally by the sequence { a of generationnN length is taken to block to form M × N-dimensional calculation matrix Φ.
2. calculation matrix FPGA is realized
The structured flowchart of this module is as shown in figure 5, input module completes λ=2.0, u0=0.37 reception, it is stored in parameter
RAM4 goes forward side by side row address distribution, is subsequently used for matrix generation unit data processing, the present apparatus will realize 64 × 256=16384
Matrix element, the matrix element of generation is first stored in RAM5, then reads out the data in RAM5, and do threshold determination, will sentenced
Fixed result is exported and cached, and obtains testing required pseudorandom calculation matrix, matrix element is made up of -1 and 1.This module
Core cell is matrix generator, as shown in fig. 6, being accomplished that the iterative algorithm of formula (2).
3rd, measurement module is compressed
1. compress measuring principle
Seismic data compression measurement process can be represented with following mathematical modeling：
Y=Φ θ+n (4)
In formula, θ ∈ RNRepresent geological data x ∈ RNIn wavelet field Ψ ∈ RN×NSparse coefficient, i.e. θ=Ψ x, Φ ∈ RM×N
(M ＜ ＜ N) is calculation matrix, and n represents noise, y ∈ RMObtained compressed data.Realize 256 sampled points to 64 on FPGA
The compression of individual sampled point, i.e. M=64, N=256, compression ratio 0.25.
2. compression measurement FPGA is realized
From contraction principle, compressed data is to be less than the matrix and multiplication of vectors of columns by line number, reaches dimensionality reduction effect
What fruit obtained, i.e. Φ θ, perform dot-product operation.Fig. 7 realizes structure chart for dot-product operation.Totally 64 dot products, each dot product are done
256 multiplication, it is contemplated that the durability of matrix-vector module, performed parallel using 16 multiply-accumulators, each dot product uses one
Individual multiply-accumulator, 64 dot products are completed in four times.The present apparatus realizes that the time delay of the accumulator is using IP kernel multiply-accumulator
C+6 clock cycle, C are the group number of input multiplier, therefore the dot product for obtaining 1 × 256 vector and 256 × 1 vectors takes 262
The individual clock cycle, obtaining 64 dot products parallel using 16 multiply-accumulators needs 262 × 4=1048 clock cycle.In Fig. 7,
MAC is multiply-accumulator, and sclr is the control signal of two tunnels distribution.262 clock cycle are completed when counter often counts, represent this
Secondary 16 dot-product operations are completed, and control signal sclr puts 1, a1 ends output result, while 4 select under 1 selector gating all the way, prepare
16 dot-product operations of the following group, other moment slr are the structure that 0, a2 ends export multiply-accumulator, and it is tired in next step to return to accumulator progress
Add.
Claims (2)
- A kind of 1. seismic data compression device based on FPGA, it is characterised in that：It is through register a (7), wavelet transformation module (2), register b (8), compression measurement module by data input module (1) (4), register d (10) and data outputting module (5) are connected with PC；Control logic module (6) respectively with data input module (1), register a (7), wavelet transformation module (2), register b (8), calculation matrix generation module (3), compression measurement module (4), register d (10) and data outputting module (5) connection；Calculation matrix generation module (3) is surveyed through register c (9) and compression Amount module (4) connects and composes.
- A kind of 2. seismic data compression device based on FPGA according to claim 1, it is characterised in that：The small echo becomes Mold changing block (2) be made up of input module, wavelet filter, memory module and output module, wherein memory module by RAM1, RAM2, internal RAM 3 and parameter RAM4 are formed；The input module is connected through parameter RAM4 with wavelet filter；Input module passes through RAM1 or RAM2, wavelet filter, RAM3 and output module connect；Control logic module (6) respectively with input module, RAM1, RAM2, RAM3 connect with output module.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107942377A (en) * | 2018-01-05 | 2018-04-20 | 吉林大学 | A kind of seismic data compression and reconstructing method |
| CN110543939A (en) * | 2019-06-12 | 2019-12-06 | 电子科技大学 | hardware acceleration implementation framework for convolutional neural network backward training based on FPGA |
| CN111132066A (en) * | 2019-12-30 | 2020-05-08 | 三维通信股份有限公司 | Sparse compression data collection method and system and computer equipment |
-
2017
- 2017-04-19 CN CN201720417394.XU patent/CN206727986U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107942377A (en) * | 2018-01-05 | 2018-04-20 | 吉林大学 | A kind of seismic data compression and reconstructing method |
| CN110543939A (en) * | 2019-06-12 | 2019-12-06 | 电子科技大学 | hardware acceleration implementation framework for convolutional neural network backward training based on FPGA |
| CN110543939B (en) * | 2019-06-12 | 2022-05-03 | 电子科技大学 | Hardware acceleration realization device for convolutional neural network backward training based on FPGA |
| CN111132066A (en) * | 2019-12-30 | 2020-05-08 | 三维通信股份有限公司 | Sparse compression data collection method and system and computer equipment |
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