CN103176450A - Servo drive device and servo control system - Google Patents
Servo drive device and servo control system Download PDFInfo
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- CN103176450A CN103176450A CN2013100428838A CN201310042883A CN103176450A CN 103176450 A CN103176450 A CN 103176450A CN 2013100428838 A CN2013100428838 A CN 2013100428838A CN 201310042883 A CN201310042883 A CN 201310042883A CN 103176450 A CN103176450 A CN 103176450A
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Abstract
The invention discloses a servo drive device and a servo control system. The servo drive device includes a power module, a processing module and a coding interface module. The output ends of the power module are respectively connected with each power input end of the processing module and the coding interface module to provide power supply for the processing module and the coding interface module. The coding interface module comprises at least a first position feedback interface unit, a second position feedback interface unit and a power supply interface unit. The output ends of the first position feedback interface unit and the second position feedback interface unit are connected with the processing module, and correspondingly used for acquiring code data of an incremental encoder and an absolute-type encoder and delivering the code data to the processing module after corresponding processing of the code data. The input end of the power supple interface unit is connected with the output end of the power module, and provides working voltage for an external encoder connected with the first position feedback interface unit or the second position feedback interface unit selectively according to configuration parameters. The servo drive device and the servo control system can be compatible with multiple types of encoders including photoelectric rotary encoders with the same or different working voltages.
Description
Technical field
The present invention relates to fields of numeric control technique, particularly relate to a kind of servo drive and servo-control system.
Background technology
Deep development along with industrialization and automatic technology, as the Electric Machine Control of basic link, particularly high-end servomotor is controlled has become the indispensable part that affects work efficiency and performance in full-automatic production line, industrial robot and digital control system.
Such as, in three ring control theories of servomotor, except electric current loop, the real time data that the feedback of speed ring and position ring all needs to obtain machine shaft is processed and is controlled.And obtain how efficiently, quickly and accurately the machine shaft data become affects control accuracy and response speed in Electric Machine Control most important index.
Obtaining the real time data of machine shaft motion by the additional scrambler that is connected to the machine shaft end, is present comparative maturity, feedback system efficiently and accurately.Due to the convenience in technique and use, photoelectric rotary coder is in occupation of dominant position in the market.Yet, the scrambler product that brand is numerous, the corresponding different principle of work of different coding device, different communication protocol and different operating voltage not only allow terminal user be difficult to choice, also allow motor-driven relevant designer and slip-stick artist hover between kinds of schemes is selected.
As shown in Figure 1, Fig. 1 is a kind of servo-control system common in prior art.This servo-control system comprises topworks 10, grating scale 11, servomotor 12, photoelectric rotary coder 13 and servo-driver 14.Wherein, servo-driver 14 comprises FPGA unit 141, the turned position value of the machine shaft of 141 pairs of FPGA unit photoelectric rotary coder, 13 feedbacks is counted, samples and segments, and the motion-control module (as the DSP unit 142 in Fig. 1) that the result after processing passes to servo-driver 14 inside carries out analytical calculation, makes the servo-driver 14 can accurate, high-precision control servomotor 12 operations.
So the encoder interfaces on servo-driver directly has influence on dynamic property and the stable state accuracy of whole servo-drive system.
The photoelectric rotary coder Interface design scheme of servo-driver product roughly is divided into following two classes in the market:
(1) adopt single encoder interfaces, only support motor and the scrambler of appointment.This class servo-driver general with motor and a whole set of sale of scrambler binding, only support a or a few money motor encoders of appointment with a servo-driver.As only supporting increment type TTL incremental encoder or absolute value SSI scrambler, the encoder type of its support is just specified when buying motor driver, and the device kind can not alternate coding.And it generally only supports a kind of operating voltage, as 5V or 15V.
(2) adopt hybrid encoder interfaces, support simultaneously absolute value encoder and incremental encoder.This class servo-driver is generally selected a kind of bus type communication protocol, can support the use with the scrambler of supporting the same bus agreement.Just can compatible incremental encoder or absolute value encoder or hybrid scrambler as EnDat communication protocol.The scrambler model that this class servo-driver is supported is more, and device kind according to the actual requirements can alternate coding after purchase.But it generally also only supports a kind of operating voltage, as 5V or 15V.
Summary of the invention
The technical matters that the present invention mainly solves is to provide a kind of servo drive and servo-control system, can compatible polytype, comprise the photoelectric rotary coder of identical or different operating voltage.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: a kind of servo drive is provided, comprise: power module, processing module and addressable port module, the output terminal of power module connects respectively the power input of processing module and addressable port module, and then provides power supply for processing module and addressable port module; The addressable port module comprises primary importance feedback interface unit, second place feedback interface unit and power interface unit at least; The output terminal of primary importance feedback interface unit connects processing module, is used for obtaining the coded data of incremental encoder and coded data being carried out passing to processing module after respective handling; The output terminal of second place feedback interface unit connects processing module, is used for obtaining the coded data of absolute value encoder and coded data being carried out passing to processing module after respective handling; The input end of power interface unit connects the output terminal of power module, and optionally provides operating voltage for the external encoder that primary importance feedback interface unit or second place feedback interface unit connect according to configuration parameter.
Wherein, processing module comprises the FPGA unit, and the power input of FPGA unit connects the output terminal of power module; Be connected output terminal and connect respectively the input/output terminal of FPGA unit in primary importance feedback interface unit with second place feedback interface unit.
Wherein, primary importance feedback interface unit comprises sinusoidal wave incremental encoder interface circuit; Sinusoidal wave incremental encoder interface circuit comprises the first operational amplifier, the second operational amplifier and ADC analog to digital converter; The first operational amplifier be connected the output terminal of operational amplifier and connect respectively the input end of ADC analog to digital converter, the output terminal of ADC analog to digital converter connects the input/output terminal of FPGA unit; Wherein, the SIN differential signal of outside sinusoidal wave incremental encoder becomes the SIN single-ended signal after by the first operational amplifier conversion and is sent to the ADC analog to digital converter and processes and obtain corresponding SIN signal, the COS differential signal of outside sinusoidal wave incremental encoder becomes the COS single-ended signal after by the second operational amplifier conversion and is sent to the ADC analog to digital converter and processes and obtain corresponding COS signal, and SIN signal and COS signal finally are passed to the FPGA unit and carry out respective handling.
wherein, primary importance feedback interface unit also comprises TTL incremental encoder interface circuit, the first operational amplifier of the multiplexing sinusoidal wave incremental encoder interface circuit of TTL incremental encoder interface circuit and the second operational amplifier, and further comprise the first comparer, the second comparer and the 3rd comparer, the output terminal of the first comparer, the second comparer and the 3rd comparer connects respectively the input/output terminal of FPGA unit, and, output terminal, another input end that one input end of the first comparer connects the first operational amplifier connect reference voltage, and output terminal, another input end that an input end of the second comparer connects the second operational amplifier connect reference voltage, the A phase differential signal of outside TTL incremental encoder becomes A phase single-ended signal after the first operational amplifier conversion, under the effect of the first comparer, obtain the A phase signals after A phase single-ended signal and reference voltage, the B phase differential signal of outside TTL incremental encoder becomes B phase single-ended signal after the second operational amplifier conversion, under the effect of the second comparer, obtain the B phase signals after B phase single-ended signal and reference voltage, the Z phase differential signal of outside TTL incremental encoder directly obtains the Z phase signals after the 3rd comparer conversion, and, the A phase signals, B phase signals and Z phase signals finally are passed to the FPGA unit and carry out respective handling.
Wherein, second place feedback interface unit comprises the absolute value encoder interface circuit; The absolute value encoder interface circuit comprises RS485 transceiver and RS485 transmitter, and wherein, an end of RS485 transceiver connects the input/output terminal of FPGA unit, and the input end of RS485 transmitter connects the input/output terminal of FPGA unit; The DATA differential signal of outside absolute value encoder converts the DATA single-ended signal to through the RS485 transceiver, the DATA single-ended signal is passed to the FPGA unit and carries out respective handling, and the FPGA unit converts the CLOCK single-ended signal CLOCK differential signal to and the DATA single-ended signal is passed to outside absolute value encoder after the RS485 transceiver converts the DATA differential signal to through the RS485 transmitter and carries out respective handling.
Wherein, the external encoder type selecting ground that connects according to primary importance feedback interface unit or second place feedback interface unit, power interface unit provides the first operating voltage or the second operating voltage for external encoder.
Wherein, the power interface unit is the DC/DC electric pressure converter of two-way output, and the DC/DC electric pressure converter comprises input end, the first output terminal, the second output terminal and control end; Wherein, the input end of DC/DC electric pressure converter connects the output terminal of power module, first output terminal output the first operating voltage of DC/DC electric pressure converter, second output terminal output the second operating voltage of DC/DC electric pressure converter; The control end of DC/DC electric pressure converter detects external encoder feedback of feedback magnitude of voltage, and feedback voltage value and the inner reference voltage level that arranges of DC/DC electric pressure converter are compared, when feedback voltage value and reference voltage level are not identical, carry out the PWM width modulation, so make external encoder stable be in the first operating voltage or the second operating voltage.
Wherein, the first operating voltage is 5V, and the second operating voltage is 10V.
Wherein, processing module comprises DSP unit and host computer interface unit; The input/output terminal of DSP unit connects the input/output terminal of FPGA unit, and the input/output terminal of host computer interface unit connects the input/output terminal of DSP unit, and wherein, the host computer interface unit is USB interface or Ethernet interface or RS232 serial ports.
For solving the problems of the technologies described above, another technical solution used in the present invention is: a kind of servo-control system is provided, and servo-control system comprises the described servo drive of above-mentioned arbitrary embodiment.
Wherein, servo-control system also comprises servomotor, photoelectric rotary coder and host computer, and wherein, servo drive connects respectively servomotor, photoelectric rotary coder and host computer; Photoelectric rotary coder is arranged on servomotor, is used for measuring the correlation parameter of servo motor rotor, and correlation parameter is passed to servo drive; Servo drive processes and passes to host computer to correlation parameter; Host computer is according to the control of the correlation parameter realization that obtains after processing to servomotor.
the invention has the beneficial effects as follows: the situation that is different from prior art, the present invention improves by the addressable port to servo drive, primary importance feedback interface unit is set, second place feedback interface unit and power interface unit, wherein, primary importance feedback interface unit and second place feedback interface unit provide the addressable port of at least two types for external encoder, and, can be according to primary importance feedback interface unit, the type of the external encoder that second place feedback interface unit connects, be optionally primary importance feedback interface unit by the power interface unit, the external encoder that second place feedback interface unit connects provides operating voltage, can be compatible dissimilar, the photoelectric rotary coder of different operating voltage, and then can enlarge the scrambler type selecting scope of support, increase the dirigibility of scrambler type selecting, reduce buying expenses and overcome the shortcoming that single operating voltage may cause.
Description of drawings
Fig. 1 is the structural representation of a kind of servo-control system of prior art;
Fig. 2 is the structural representation of servo drive the first embodiment of the present invention;
Fig. 3 is the structural representation of servo drive the second embodiment of the present invention;
Fig. 4 is the electrical block diagram of servo drive shown in Figure 3;
Fig. 5 is the structural representation of servo drive the 3rd embodiment of the present invention.
Embodiment
The present invention is described in detail below in conjunction with the drawings and specific embodiments.
Consult Fig. 2, Fig. 2 is the structural representation of servo drive the first embodiment of the present invention.Embodiment of the present invention comprises: power module 101, processing module 102 and addressable port module 103.
Wherein, the output terminal 1011,1012 of power module 101 connects respectively the power input 1021 of processing module 102 and the power input of addressable port module 103, and then provides power supply for processing module 102 and addressable port module 103.
And addressable port module 103 comprises primary importance feedback interface unit 1031, second place feedback interface unit 1032 and power interface unit 1033 at least.Wherein, the output terminal 10310 of primary importance feedback interface unit 1031 connects processing modules 102, is used for obtaining the coded data of incremental encoder and coded data being carried out passing to processing module 102 after respective handling; The output terminal 10320 of second place feedback interface unit 1032 connects processing module 102, is used for obtaining the coded data of absolute value encoder and coded data being carried out passing to processing module 102 after respective handling.
Further, the input end 10330 of power interface unit 1033 connects the output terminal 1012 of power module 101, and according to configuration parameter, namely the type selecting of external encoder ground provides operating voltage for the external encoder that primary importance feedback interface unit 1031 or second place feedback interface unit 1032 connect.
embodiment of the present invention, improve by the addressable port to servo drive, primary importance feedback interface unit 1031 is set, second place feedback interface unit 1032 and power interface unit 1033, wherein, primary importance feedback interface unit 1031 and second place feedback interface unit 1032 provide the addressable port of at least two types for external encoder, and, can be according to primary importance feedback interface unit 1031, the type of the external encoder that second place feedback interface unit 1032 connects, be optionally primary importance feedback interface unit 1031 by power interface unit 1033, the external encoder that second place feedback interface unit 1032 connects provides operating voltage, can be compatible dissimilar, the photoelectric rotary coder of different operating voltage, and then can enlarge the scrambler type selecting scope of support, increase the dirigibility of scrambler type selecting, reduce buying expenses and overcome the shortcoming that single operating voltage may cause.
Consult Fig. 3 and Fig. 4, Fig. 3 is the structural representation of servo drive the second embodiment of the present invention, and Fig. 4 is the electrical block diagram of servo drive shown in Figure 3.In embodiment of the present invention, processing module 202 comprises FPGA(Field-Programmable Gate Array, field programmable gate array) unit 2021 and DSP(Digital Signal Processing, digital signal processing) unit 2022.
This FPGA unit 2021 comprises power input 20210, the power input 20210 of FPGA unit 2021 connects the output terminal 2011 of power module 201, one group of input/output terminal 20211 of FPGA unit 2021 also connects the input/output terminal 20220 of DSP unit 2022, and the power input 20221 of DSP unit 2022 connects the output terminal 2011 of power modules 201.
Further, the output terminal 20310 of primary importance feedback interface unit 2031 connects one group of input/output terminal 20211(I/O of FPGA unit 2021, Input or Output), the output terminal 20320 of second place feedback interface unit 2032 also connects one group of input/output terminal 20211 of FPGA unit 2021.
Wherein, primary importance feedback interface unit 2031 comprises sinusoidal wave incremental encoder interface circuit, and sinusoidal wave incremental encoder interface circuit comprises the first operational amplifier 400, the second operational amplifier 401 and ADC(Analog-to-Digital Converter) analog to digital converter.
The first operational amplifier 400 be connected the output terminal of operational amplifier 401 and connect respectively the input end of ADC analog to digital converter 402, the output terminal of ADC analog to digital converter 402 connects one group of input/output terminal 20211 of FPGA unit 2021.
Wherein, the SIN differential signal of outside sinusoidal wave incremental encoder becomes the SIN single-ended signal after by the first operational amplifier 400 conversions and is sent to ADC analog to digital converter 402 and processes and obtain corresponding SIN signal, the COS differential signal of outside sinusoidal wave incremental encoder becomes the COS single-ended signal after by the second operational amplifier 401 conversions and is sent to ADC analog to digital converter 402 and processes and obtain corresponding COS signal, and SIN signal and COS signal finally are passed to FPGA unit 2021 and carry out respective handling.
Further, primary importance feedback interface unit 2031 also comprises TTL incremental encoder interface circuit.
The first operational amplifier 400 of the multiplexing sinusoidal wave incremental encoder interface circuit of TTL incremental encoder interface circuit and the second operational amplifier 401, and further comprise the first comparer 403, the second comparer 404 and the 3rd comparer 405.
The output terminal of the first comparer 403, the second comparer 404 and the 3rd comparer 405 connects respectively one group of input/output terminal 20211 of FPGA unit 2021, and, output terminal, another input end that one input end of the first comparer 403 connects the first operational amplifier 400 connect reference voltage, and output terminal, another input end that an input end of the second comparer 404 connects the second operational amplifier 401 connect reference voltage.
the A phase differential signal of outside TTL incremental encoder becomes A phase single-ended signal after the first operational amplifier 400 conversions, under the effect of the first comparer 403, obtain the A phase signals after A phase single-ended signal and reference voltage, the B phase differential signal of outside TTL incremental encoder becomes B phase single-ended signal after the second operational amplifier 401 conversions, under the effect of the second comparer 404, obtain the B phase signals after B phase single-ended signal and reference voltage, the Z phase differential signal of outside TTL incremental encoder directly obtains the Z phase signals after the 3rd comparer 405 conversions, and, the A phase signals, B phase signals and Z phase signals finally are passed to FPGA unit 2021 and carry out respective handling.
In conjunction with Fig. 4, the working method of primary importance feedback interface unit 2031 in servo drive the second embodiment of the present invention is carried out concise and to the point schematic illustration.
(1) when the external encoder of primary importance feedback interface unit 2031 connections was sinusoidal wave incremental encoder (or cosine wave (CW) scrambler), sinusoidal wave incremental encoder connected sinusoidal wave incremental encoder interface circuit.
wherein, the coded data of sinusoidal wave incremental encoder comprises SIN signal and COS signal, the SIN signal is sent to the first operational amplifier 400 with the form of differential signal SIN+ and SIN-, after the amplification of the first operational amplifier 400 is processed, convert to through the single-ended signal SIN+ after amplifying, simultaneously, the COS signal also is sent to the second operational amplifier 401 with the form of differential signal COS+ and COS-, after the amplification of the second operational amplifier 401 is processed, convert to through the single-ended signal COS+ after amplifying, subsequently, ADC analog to digital converter 402 carries out single-ended signal SIN+ and COS+ to obtain SIN+ and COS+ signal after relevant treatment, ADC analog to digital converter 402 is passed to FPGA unit 2021 with SIN+ and COS+ signal and counts, sampling and segmentation, and the result after the processing DSP unit 2022 that passes to processing module 202 carries out analytical calculation and obtains the result that needs.
When the servomotor control accuracy being had relatively high expectations or servomotor itself operation when slower, adopt this sine wave incremental encoder interface circuit to connect sinusoidal wave incremental encoder, the amplitude of the sinusoidal wave incremental encoder that can will collect by ADC analog to digital converter 402 converts concrete data to, because this amplitude degree of accuracy is higher, and then can improve the control accuracy to servomotor.
(2) when the external encoder of primary importance feedback interface unit 2031 connections was the TTL incremental encoder, the TTL incremental encoder connected TTL incremental encoder interface circuit.
wherein, the coded data of TTL incremental encoder comprises the A phase, B phase and Z phase signals, the A phase signals is sent to the first operational amplifier 400 with the form of differential signal A+ and A-, after the amplification of the first operational amplifier 400 is processed, convert to through the single-ended signal A+ after amplifying, simultaneously, the B phase signals also is sent to the second operational amplifier 401 with the form of differential signal B+ and B-, after the amplification of the second operational amplifier 401 is processed, convert to through the single-ended signal B+ after amplifying, the Z phase signals directly is passed to the 3rd comparer 405 with the form of differential signal Z+ and Z-, after the processing of the 3rd comparer 405, directly be converted to single-ended signal Z+, subsequently, A+, B+ and Z+ signal all are passed to FPGA unit 2021 and count, sampling, and the result after the processing DSP unit 2022 that passes to processing module 202 carries out analytical calculation and obtains the result that needs.
Embodiment of the present invention, sinusoidal wave incremental encoder interface circuit and the TTL incremental encoder interface circuit of primary importance feedback interface unit 2031 can be realized interface duplex, can the integration system resource, make circuit structure simpler, be conducive to reduce costs.
Continue to consult Fig. 4, second place feedback interface unit 2032 comprises the absolute value encoder interface circuit.
Wherein, the absolute value encoder interface circuit comprises RS485 transceiver 500 and RS485 transmitter 501, wherein, RS485 transceiver 500 can receive and can send data, further, RS485 transceiver 500 comprises receiving element 5001 and transmitting element 5002, the output terminal of receiving element 5001 connects one group of input/output terminal 20211 of FPGA unit 2021, and the input end of transmitting element 5002 connects one group of input/output terminal 20211 of FPGA unit 2021, and the input end of RS485 transmitter 501 connects one group of input/output terminal 20211 of FPGA unit 2021.
The DATA differential signal of outside absolute value encoder converts the DATA single-ended signal to through RS485 transceiver 500, the DATA single-ended signal is passed to FPGA unit 2021 and carries out respective handling, and FPGA unit 2021 converts the CLOCK single-ended signal CLOCK differential signal to and the DATA single-ended signal is passed to outside absolute value encoder after RS485 transceiver 500 converts the DATA differential signal to through RS485 transmitter 501 and carries out respective handling.
particularly, the coded data of absolute value encoder comprises CLOCK signal and DATA signal, wherein, FPGA unit 2021 is sent to RS485 transmitter 501 with single-ended signal CLOCK+, after processing, RS485 transmitter 501 obtains differential signal CLOCK+ and CLOCK-, obtain this CLOCK+ and CLOCK-by absolute value encoder subsequently, after absolute value encoder gets CLOCK+ and CLOCK-, absolute value encoder is sent to RS485 transceiver 500 with the DATA signal with the form of differential signal DATA+ and DATA-at synchronization, can realize the synchronous transmission of data, thereafter, DATA+ and DATA-convert single-ended signal DATA+ to and are sent to FPGA unit 2021 after RS485 transceiver 500 is processed.Wherein, because absolute value encoder can be preserved coded data, can preserve the DATA signal at least, FPGA can again read at system cut-off or after restarting the DATA value of scrambler preservation and proofread with the DATA value before outage, can realize the check and correction of synchrodata.
By FPGA unit 2021, single-ended signal DATA+ is sent to RS485 transceiver 500, this RS485 transceiver 500 converts DATA+ to differential signal DATA+ and DATA-, this DATA+ and DATA-are received by absolute value encoder, absolute value encoder is after receiving corresponding control or configuration order, himself register value (detected value that comprises temperature sensor, CRC check value etc.) can be passed to FPGA unit 2021.。
Continue to consult Fig. 4, wherein, power interface unit 2033 optionally provides the first operating voltage V1 or the second operating voltage V2 for the external encoder that primary importance feedback interface unit 2031 or second place feedback interface unit 2032 connect according to configuration parameter.For example, this configuration parameter is normal working voltage scope or some concrete value of external encoder, manually external encoder is connected to power interface unit 2033 and provides on the pin of the first operating voltage V1 according to this configuration parameter or be connected on the pin that the second operating voltage V2 is provided.
Particularly, the power interface unit is the DC/DC(Direct Current to Direct Current of two-way output, DC converting becomes direct current) electric pressure converter 2033, DC/DC electric pressure converter 2033 comprises input end, the first output terminal, the second output terminal and control end.
Wherein, the input end of DC/DC electric pressure converter 2033 connects the output terminal of power module 201, first output terminal output the first operating voltage V1 of DC/DC electric pressure converter 2033, second output terminal output the second operating voltage V2 of DC/DC electric pressure converter 2033.
the control end of DC/DC electric pressure converter 2033 detects external encoder feedback of feedback magnitude of voltage V_SENSE, wherein, the real work magnitude of voltage proportion relation that this feedback voltage value V_SENSE and external encoder are current, namely this feedback voltage value V_SENSE can reflect its actual operational voltage value, subsequently, feedback voltage value V_SENSE and the inner corresponding reference voltage level that arranges of DC/DC electric pressure converter 2033 are compared, wherein, corresponding the first reference voltage level of the first operating voltage V1, corresponding the second reference voltage level of the second operating voltage V2, when feedback voltage value V_SENSE is not identical with corresponding reference voltage level, namely, when external encoder adopts the first operating voltage V1, feedback voltage value V_SENSE and the first reference voltage level are compared, and external encoder is when adopting the second operating voltage V2, feedback voltage value V_SENSE and the second reference voltage level are compared.Then, carry out the PWM width modulation, namely make the feedback voltage value identical with reference voltage level or basic identical by the PWM width modulation, so make external encoder stable be in the first operating voltage V1 or the second operating voltage V2.And then can guarantee the reliability of external encoder.
Wherein, the first operating voltage V1 is 5V, and the second operating voltage V2 is 10V.Selection for the first operating voltage V1 and the second operating voltage V2 value, main reference standard is the operating voltage range of scrambler commonly used, as common on the market, the operating voltage of different vendor and different agreement scrambler is different, but be mainly 5V, 7-12V and 10-30V, and be 5V with the first operating voltage V1 value in embodiment of the present invention, be 10V with the second operating voltage V2 value, get final product the compatible above-mentioned operating voltage of mentioning, can satisfy most occasions to the demand of operating voltage.Certainly, for the value of the first operating voltage V1 and the second operating voltage V2, can specific customization, perhaps can be arranged voluntarily by the user, to satisfy actual needs.
Above-mentioned embodiment can compatible absolute value encoder, sinusoidal wave incremental encoder and TTL incremental encoder.
Consult Fig. 5, Fig. 5 is the structural representation of servo drive the 3rd embodiment of the present invention.Only be with the difference of second embodiment of the invention, in embodiment of the present invention, processing module 302 comprises host computer interface unit 3023.Wherein, the input/output terminal 30230 of host computer interface unit 3023 connects the input/output terminal 30221 of DSP unit 3022.
Host computer connects the input/output terminal 30231 of host computer interface unit 3023, and host computer is by controlling DSP unit 3022 and then control servo drive.Wherein, host computer is PC(Personal Computer, PC) or other control terminal.
Further, host computer interface unit 3023 is USB interface or Ethernet interface or RS232 serial ports.Can provide multifarious interface to select, make the host computer of different interface type can be general.
Servo drive is supported the scrambler of EnDat, Biss, Hiperface, SSI, TTL and Sin/Cos communications protocol.What deserves to be explained is, because embodiment of the present invention designs satisfying under the EnDat communications protocol, and the EnDat agreement is a kind of communications protocol the strictest, that be most widely used, therefore, can compatible all the other several scramblers as Biss, Hiperface, SSI, TTL and Sin/Cos communications protocol.
The present invention also provides a kind of servo-control system.
This servo-control system comprises as the described servo drive of above-mentioned arbitrary embodiment.
Particularly, this servo-control system also comprises servomotor, photoelectric rotary coder and host computer.
Wherein, servo drive connects respectively servomotor, photoelectric rotary coder and host computer.
Photoelectric rotary coder is arranged on servomotor, is used for measuring the correlation parameter of servo motor rotor, and correlation parameter is passed to servo drive; Servo drive processes and passes to host computer to correlation parameter; Host computer is according to the control of the correlation parameter realization that obtains after processing to servomotor.
the servo-control system of embodiment of the present invention, because adopt the described servo drive of above-mentioned arbitrary embodiment, improve by the addressable port to servo drive, primary importance feedback interface unit is set, second place feedback interface unit and power interface unit, wherein, primary importance feedback interface unit and second place feedback interface unit provide the addressable port of at least two types for external encoder, and, can be according to primary importance feedback interface unit, the type of the external encoder that second place feedback interface unit connects, be optionally primary importance feedback interface unit by the power interface unit, the external encoder that second place feedback interface unit connects provides operating voltage, can be compatible dissimilar, the photoelectric rotary coder of different operating voltage, and then can enlarge the scrambler type selecting scope of support, increase the dirigibility of scrambler type selecting, reduce buying expenses and overcome the shortcoming that single operating voltage may cause.
These are only embodiments of the present invention; not thereby limit the scope of the claims of the present invention; every equivalent structure or equivalent flow process conversion that utilizes instructions of the present invention and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in scope of patent protection of the present invention.
Claims (11)
1. a servo drive, is characterized in that, comprising:
Power module, processing module and addressable port module, the output terminal of described power module connects respectively the power input of described processing module and described addressable port module, and then provides power supply for described processing module and described addressable port module;
Described addressable port module comprises primary importance feedback interface unit, second place feedback interface unit and power interface unit at least;
The output terminal of described primary importance feedback interface unit connects described processing module, is used for obtaining the coded data of incremental encoder and described coded data being carried out passing to described processing module after respective handling;
The output terminal of described second place feedback interface unit connects described processing module, is used for obtaining the coded data of absolute value encoder and described coded data being carried out passing to described processing module after respective handling;
The input end of described power interface unit connects the output terminal of described power module, and optionally provides operating voltage for the external encoder that described primary importance feedback interface unit or described second place feedback interface unit connect according to configuration parameter.
2. servo drive according to claim 1, is characterized in that,
Described processing module comprises the FPGA unit, and the power input of described FPGA unit connects the output terminal of described power module;
Described primary importance feedback interface unit be connected the output terminal of second place feedback interface unit and connect respectively the input/output terminal of described FPGA unit.
3. servo drive according to claim 2, is characterized in that,
Described primary importance feedback interface unit comprises sinusoidal wave incremental encoder interface circuit;
Described sinusoidal wave incremental encoder interface circuit comprises the first operational amplifier, the second operational amplifier and ADC analog to digital converter;
Described the first operational amplifier be connected the output terminal of the second operational amplifier and connect respectively the input end of described ADC analog to digital converter, the output terminal of described ADC analog to digital converter connects the input/output terminal of described FPGA unit;
Wherein, the SIN differential signal of outside sinusoidal wave incremental encoder becomes the SIN single-ended signal after by described the first operational amplifier conversion and is sent to described ADC analog to digital converter and processes and obtain corresponding SIN signal, the COS differential signal of outside sinusoidal wave incremental encoder becomes the COS single-ended signal after by described the second operational amplifier conversion and is sent to described ADC analog to digital converter and processes and obtain corresponding COS signal, and described SIN signal and described COS signal finally are passed to described FPGA unit and carry out respective handling.
4. servo drive according to claim 3, is characterized in that,
Described primary importance feedback interface unit also comprises TTL incremental encoder interface circuit;
Described first operational amplifier of the multiplexing described sinusoidal wave incremental encoder interface circuit of described TTL incremental encoder interface circuit and described the second operational amplifier, and further comprise the first comparer, the second comparer and the 3rd comparer;
The output terminal of described the first comparer, described the second comparer and described the 3rd comparer connects respectively the input/output terminal of described FPGA unit, and, output terminal, another input end that one input end of described the first comparer connects the first operational amplifier connect reference voltage, and output terminal, another input end that an input end of described the second comparer connects the second operational amplifier connect reference voltage;
the A phase differential signal of outside TTL incremental encoder becomes A phase single-ended signal after the first operational amplifier conversion, under the effect of described the first comparer, obtain the A phase signals after described A phase single-ended signal and reference voltage, the B phase differential signal of outside TTL incremental encoder becomes B phase single-ended signal after the second operational amplifier conversion, under the effect of described the second comparer, obtain the B phase signals after described B phase single-ended signal and reference voltage, the Z phase differential signal of outside TTL incremental encoder directly obtains the Z phase signals after described the 3rd comparer conversion, and, described A phase signals, B phase signals and Z phase signals finally are passed to described FPGA unit and carry out respective handling.
5. servo drive according to claim 4, is characterized in that,
Described second place feedback interface unit comprises the absolute value encoder interface circuit;
Described absolute value encoder interface circuit comprises RS485 transceiver and RS485 transmitter, wherein, one end of described RS485 transceiver connects the input/output terminal of described FPGA unit, and the input end of described RS485 transmitter connects the input/output terminal of described FPGA unit;
The DATA differential signal of outside absolute value encoder converts the DATA single-ended signal to through described RS485 transceiver, described DATA single-ended signal is passed to described FPGA unit and carries out respective handling, and described FPGA unit converts the CLOCK single-ended signal CLOCK differential signal to and the DATA single-ended signal is passed to outside absolute value encoder after described RS485 transceiver converts the DATA differential signal to through the RS485 transmitter and carries out respective handling.
6. servo drive according to claim 5, is characterized in that,
Described power interface unit connects according to described primary importance feedback interface unit or described second place feedback interface unit external encoder type selecting ground provides the first operating voltage or the second operating voltage for external encoder.
7. servo drive according to claim 6, is characterized in that,
Described power interface unit is the DC/DC electric pressure converter of two-way output, and described DC/DC electric pressure converter comprises input end, the first output terminal, the second output terminal and control end;
Wherein, the input end of described DC/DC electric pressure converter connects the output terminal of described power module, first output terminal output the first operating voltage of described DC/DC electric pressure converter, second output terminal output the second operating voltage of described DC/DC electric pressure converter;
The control end of described DC/DC electric pressure converter detects external encoder feedback of feedback magnitude of voltage, and described feedback voltage value and the inner reference voltage level that arranges of described DC/DC electric pressure converter are compared, when described feedback voltage value and described reference voltage level are not identical, carry out the PWM width modulation, so make external encoder stable be in the first operating voltage or the second operating voltage.
8. servo drive according to claim 7, is characterized in that,
Described the first operating voltage is 5V, and described the second operating voltage is 10V.
9. servo drive according to claim 2, is characterized in that,
Described processing module comprises DSP unit and host computer interface unit; The input/output terminal of described DSP unit connects the input/output terminal of described FPGA unit, and the input/output terminal of described host computer interface unit connects the input/output terminal of described DSP unit;
Wherein, described host computer interface unit is USB interface or Ethernet interface or RS232 serial ports.
10. a servo-control system, is characterized in that, described servo-control system comprises as the described servo drive of claim 1-9 any one.
11. servo-control system according to claim 10 is characterized in that,
Described servo-control system also comprises servomotor, photoelectric rotary coder and host computer, and wherein, described servo drive connects respectively described servomotor, described photoelectric rotary coder and host computer;
Described photoelectric rotary coder is arranged on described servomotor, is used for measuring the correlation parameter of described servo motor rotor, and described correlation parameter is passed to described servo drive; Described host computer is processed and passed to described servo drive to described correlation parameter; The correlation parameter that described host computer obtains after according to described processing is realized the control to described servomotor.
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