CN102624375A - Signal processing device compatible with various encoders and resolver interfaces - Google Patents

Abstract

The invention discloses a signal processing device compatible with multiple kinds of interfaces of encoders and rotary transformers. The signal processing device at least comprises an input interface module, a signal conditioning circuit, an FPGA (Field Programmable Gate Array) circuit module and a signal output interface module, wherein the input interface module, the signal conditioning circuit, the FPGA circuit module and the signal output interface module are sequentially connected. The signal processing device can be compatible with all kinds of traditional incremental encoders, absolute type encoders and rotary transformers in the market. The invention can realize that signals of more than one encoder and rotary transformer can be simultaneously processed and one or more signal processing results are output without replacing the signal processing device of a detection element interface, is suitable for detection and processing of position, speed and angle signals of different types of mechanical movement parts, is convenient for filed debugging of technicians, is convenient for use, is good in practicability, and has better actual application value and market competitiveness.

Description

Signal processing device compatible with various encoders and resolver interfaces

technical field

The invention relates to the fields of numerically controlled machine tools, robots and servo control technology, and is especially suitable for a compatible interface signal processing device for various encoders and rotary transformers used to detect the position, speed and angle signals of different actuators.

Background technique

In the fields of CNC machine tools, robots and servo control technology, the detection unit of the position control, speed control or angle control system is an indispensable part, and the detected position, speed or angle information is used as the feedback signal of the closed-loop control to improve The movement speed, precision and efficiency of the equipment.

At present, the detection unit of the position control, speed control or angle control system on the market mainly uses the following three components: incremental encoder, absolute encoder and resolver. Incremental encoders are small in size, low in price, high in precision, fast in response, and stable in performance, and are widely used in radar, photoelectric theodolite, ground commander, robot, CNC machine tools, servo control, and other fields; absolute encoders are controlled by mechanical position Each determined position is absolutely unique, strong anti-interference, easy to memorize and save, can directly read out the absolute position information, no cumulative error, high data reliability, widely used in various industrial systems for angle, length measurement and Positioning control, such as CNC machine tools and robots, where the precision requirements are relatively high. The resolver is a precision angle, position, and speed detection device, which is suitable for all occasions where the rotary encoder is used, especially the occasions where the rotary encoder cannot work normally due to high temperature, severe cold, humidity, high speed, and high vibration. Due to the above characteristics of the resolver, it can completely replace the photoelectric encoder, and is widely used in angle and position detection systems in servo control systems, robot systems, mechanical tools, automobiles, electric power, aerospace, ships, construction and other fields.

In order to achieve compatibility with incremental encoders and absolute encoders, invention patent 200810162067.X proposes an AC servo driver compatible with multiple encoder interfaces. The driver proposed in this invention is compatible with incremental encoders and Absolute encoder; utility model patent 201020575348.0 proposes an AC servo drive compatible with multiple position feedbacks and supports multiple bus protocols. However, these patents do not involve the resolution of the resolver compatibility problem. In the fields of CNC machine tools, robots, and servo control technology, in order to meet the requirements of the control system for accuracy, speed, performance, and environment, the detection units of the position control, speed control, or angle control systems will use different detection elements. It is necessary to design a signal processing device compatible with various incremental encoders, absolute encoders and resolver interfaces.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned deficiencies in the prior art, and provide a signal processing device compatible with various encoders and rotary transformer interfaces, so as to realize motion control between various incremental encoders, absolute encoders, rotary transformers and external connections The unit connection facilitates on-site debugging by technicians, and improves the practicability and market competitiveness of the signal processing device.

Technical scheme of the present invention is summarized as follows:

A signal processing device compatible with interfaces between various encoders and resolvers, at least including a signal input interface module 1, a signal conditioning circuit module 2, an FPGA circuit module 3, and a signal output interface module 4, characterized in that the device can simultaneously process a The signals of the above encoder and resolver, and through parameter configuration, select and output one or more than one signal processing results; the output terminal of the signal input interface module 1 is connected to the input terminal of the signal conditioning circuit module 2, and the signal conditioning circuit module 2 The output end is connected with the FPGA circuit module 3 input pins, and the FPGA circuit module 3 output pins are connected with the signal output interface module 4; the simultaneous processing of signals of more than one encoder and resolver refers to multiple encoders and resolvers All combinations of signals.

The signal input interface module 1 at least includes an incremental encoder signal input interface 11 , an absolute encoder signal input interface 12 , and a resolver signal input interface 13 .

The signal conditioning circuit module 2 at least includes an incremental encoder signal conditioning circuit 21 , an absolute encoder signal conditioning circuit 22 , and a resolver signal conditioning circuit 23 .

Described FPGA circuit module 3 comprises incremental encoder signal processing unit 31 at least, absolute encoder signal processing unit 32, rotary transformer signal processing unit 33, signal output unit 34, and according to encoder and rotary encoder output signal Features and data format, using Verilog HDL hardware description language programming to realize the logic functions of each unit; the absolute encoder signal processing unit 32 at least includes a Tamagawa absolute encoder signal processing unit 321, a Heidenhain absolute encoder signal processing unit 322.

The signal output interface module 4 includes a parallel signal output interface 41 and a serial signal output interface 42 .

The incremental encoder signal conditioning circuit 21 includes a differential single-ended signal conversion circuit 211, a photoelectric isolation circuit 212, and a reverse Schmitt trigger 213; the incremental encoder signal input interface 11 output terminal and the differential single-ended signal The input end of the conversion circuit 211 is connected, the output end of the differential single-ended signal conversion circuit 211 is connected with the input end of the photoelectric isolation circuit 212, the output end of the photoelectric isolation circuit 212 is connected with the input end of the reverse Schmitt trigger 213, and the reverse The output end of the Schmitt trigger 213 is connected with the input end of the incremental encoder signal processing 31 .

The absolute encoder signal input interface 12 at least includes a Tamagawa absolute encoder signal input interface 121 and a HEIDENHAIN absolute encoder signal input interface 122 .

The absolute encoder signal conditioning circuit 22 at least includes a Tamagawa absolute encoder signal conditioning circuit 221 and a HEIDENHAIN absolute encoder signal conditioning circuit 222 .

The Tamagawa absolute encoder signal conditioning circuit 221 includes a differential single-ended signal conversion circuit 2211, a photoelectric isolation circuit 2212, and a reverse Schmitt trigger 2213; the Tamagawa absolute encoder signal input interface 121 and a differential single-ended signal conversion circuit One end of 2211 is connected, the other end of differential single-ended signal conversion circuit 2211 is connected with one end of photoelectric isolation circuit 2212, the other end of photoelectric isolation circuit 2212 is connected with one end of reverse Schmitt trigger 2213, reverse Schmitt trigger The other end of the encoder 2213 is connected to one end of the signal processing unit 321 of the Tamagawa absolute encoder.

The HEIDENHAIN absolute encoder signal conditioning circuit 222 includes an RS485 transceiver chip 2221, a photoelectric isolation circuit 2222, and a reverse Schmitt trigger 2223; one end of the RS485 transceiver chip 2221 is connected to the HEIDENHAIN absolute encoder signal input interface 122 , the other end of the RS485 transceiver chip 2221 is connected to one end of the photoelectric isolation circuit 2222, the other end of the photoelectric isolation circuit 2222 is connected to one end of the reverse Schmitt trigger 2223, and the other end of the reverse Schmitt trigger 2223 is connected to the Hyde One end of the Han absolute encoder signal processing unit 322 is connected.

The rotary transformer signal conditioning circuit 23 includes a differential linear amplifier 231, a comparator 232, a photoelectric isolation circuit 233, a sample and hold circuit 234, and an A/D converter 235; the input terminal of the differential linear amplifier 231 is connected to the rotary transformer signal input interface 13, The output terminal of the differential linear amplifier 231 is connected with the input terminal of the comparator 232 and the sample-and-hold circuit 234 respectively, the output terminal of the comparator 232 is connected with the input terminal of the photoelectric isolation circuit 233, and the output terminal of the sample-hold circuit 234 is connected with the A/D conversion The input end of the converter 235 is connected, and the output ends of the photoelectric isolation circuit 233 and the A/D converter 235 are respectively connected with the input end of the resolver signal processing unit 33 .

The signal output unit 34 is used to register the signal processing results of the incremental encoder, the absolute encoder and the resolver, and select and output one or more signals by configuring the parameters of the control register in the signal output unit 34 The result of processing; the result of more than one signal processing refers to all combinations of the signal processing results of multiple encoders and resolvers; the parameter configuration is made by the external motion control unit through the parallel signal output interface 41 or serial The signal output interface 42 writes the parameter configuration value to the control register in the signal output unit 34 to complete the parameter configuration process; the signal output mode includes parallel signal output and serial output; the external motion control unit is the motion control control unit of the equipment, It can be a digital signal processor DSP, a single-chip microcomputer, a PC, a robot control unit, a numerical control system control unit, and the like.

Compared with prior art, the beneficial effect of the present invention is:

The signal processing device has the signal interface of incremental encoder, absolute encoder and resolver, the incremental encoder signal interface can be compatible with the incremental Absolute encoders with various mainstream protocols; the resolver signal interface is compatible with resolvers of various brands. The present invention can select one or more encoders and resolvers as the detection elements of the position control, speed control or angle control system detection unit through parameter configuration, which overcomes the existing device that can only select one type of encoder as the detection unit at the same time. The shortcomings of the components realize the signal processing device that does not need to replace the interface of the detection component, and can process the signals of more than one encoder and resolver at the same time, which meets the requirements of the control system for accuracy, speed, performance and environment, and is convenient for technicians on site. Debugging, easy to use, good practicability, good practical application value and market competitiveness.

Description of drawings

Fig. 1 is a schematic structural diagram of a signal processing device compatible with various encoders and resolver interfaces;

Fig. 2 is an example diagram of an incremental encoder signal conditioning circuit;

Fig. 3 is an example diagram of an absolute encoder signal conditioning circuit;

Figure 4 is an example diagram of a resolver signal conditioning circuit.

Detailed ways

The present invention will be further described below in conjunction with accompanying drawing.

In the fields of CNC machine tools, robotics and servo control technology, detection units for position control, speed control or angle control systems are indispensable components. A variety of encoders and resolvers are used to detect the position, speed, and angle signals of different actuators. The invention is a signal processing device with interfaces compatible with various encoders and rotary transformers. The device can process signals from more than one encoder and resolver at the same time. The structure of a signal processing device compatible with various encoders and resolver interfaces is shown in Figure 1. The signal processing device at least includes a signal input interface module 1, a signal conditioning circuit module 2, an FPGA circuit module 3, and a signal output interface module 4; The signal input interface module 1 at least includes an incremental encoder signal input interface 11, an absolute encoder signal input interface 12, and a resolver signal input interface 13; the signal conditioning circuit module 2 includes at least an incremental encoder signal conditioning circuit 21, Absolute encoder signal conditioning circuit 22, resolver signal conditioning circuit 23; FPGA circuit module 3 at least includes incremental encoder signal processing unit 31, absolute encoder signal processing unit 32, resolver signal processing unit 33, signal output Unit 34; the signal output interface module 4 includes a parallel signal output interface 41 and a serial signal output interface 42; the signal input interface module 1 output is connected to the signal conditioning circuit module 2 input correspondingly, and the signal conditioning circuit module 2 output is connected to the FPGA circuit The input pins of the module 3 are connected correspondingly, and the output pins of the FPGA circuit module 3 are connected correspondingly with the signal output interface module 4; Parameter configuration of the register, select to output one or more signal processing results and select the way of signal output.

An example diagram of the incremental encoder signal conditioning circuit, as shown in Figure 2, the incremental encoder signal conditioning circuit 21 includes a differential single-ended signal conversion circuit 211, a photoelectric isolation circuit 212, and a reverse Schmitt trigger 213; The input end of the differential single-ended signal conversion circuit 211 is connected with the output end of the incremental encoder signal input interface 11, the output end of the differential single-ended signal conversion circuit 211 is connected with the input end of the photoelectric isolation circuit 212, and the input end of the photoelectric isolation circuit 212 The output terminal is connected to the input terminal of the reverse Schmitt trigger 213 , and the output terminal of the reverse Schmitt trigger 213 is connected to the input terminal of the incremental encoder signal processing 31 . The output signal of the incremental encoder is connected to the differential single-ended signal conversion circuit 211 through the incremental encoder signal input interface 11 to obtain a single-ended signal, and the single-ended signal passes through the photoelectric isolation circuit 212 and the reverse Schmitt trigger 213 is input to the incremental encoder signal processing unit 31. The incremental encoder signal processing unit 31 implements digital filtering, direction identification, frequency doubling, frequency doubling, pulse position counting, and adaptive speed measurement for incremental encoder signals.

An example diagram of an absolute encoder signal conditioning circuit, as shown in Figure 3, the absolute encoder signal input interface 12 at least includes a Tamagawa absolute encoder signal input interface 121, a Heidenhain absolute encoder signal input interface 122, an absolute The encoder signal conditioning circuit 22 includes at least Tamagawa absolute encoder signal conditioning circuit 221, Heidenhain absolute encoder signal conditioning circuit 222, absolute encoder signal processing unit 32 includes at least Tamagawa absolute encoder signal processing unit 321, Heidenhain absolute encoder signal processing unit 321, Heidenhain Han absolute encoder signal processing unit 322 .

The Tamagawa absolute encoder signal conditioning circuit 221 includes a differential single-ended signal conversion circuit 2211, a photoelectric isolation circuit 2212, a reverse Schmitt trigger 2213, one end of the differential single-ended signal conversion circuit 2211 and the Tamagawa absolute encoder signal The output end of the input interface 121 is connected, the other end of the differential single-ended signal conversion circuit 2211 is connected with one end of the photoelectric isolation circuit 2212, the other end of the photoelectric isolation circuit 2212 is connected with one end of the reverse Schmitt trigger 2213, reverse The other end of the Mitter trigger 2213 is connected to one end of the Tamagawa absolute encoder signal processing unit 321 . The output signal of the Tamagawa absolute encoder is connected to the differential single-ended signal conversion circuit 2211 through the Tamagawa absolute encoder signal input interface 121 to obtain a single-ended signal, and the single-ended signal passes through the photoelectric isolation circuit 2212 and the reverse Schmitt trigger 2213 is input to the Tamagawa absolute encoder signal processing unit 321, and the Tamagawa absolute encoder signal processing unit 321 processes the signal according to the Tamagawa absolute encoder data protocol to obtain the position value and status information.

The HEIDENHAIN absolute encoder signal conditioning circuit 222 includes an RS485 transceiver chip 2221, a photoelectric isolation circuit 2222, and a reverse Schmitt trigger 2223; one end of the RS485 transceiver chip 2221 is output to the HEIDENHAIN absolute encoder signal input interface 122 The other end of the RS485 transceiver chip 2221 is connected to one end of the photoelectric isolation circuit 2222, the other end of the photoelectric isolation circuit 2222 is connected to one end of the reverse Schmitt trigger 2223, and the other end of the reverse Schmitt trigger 2223 It is connected to one end of the signal processing unit 322 of the HEIDENHAIN absolute encoder. The HEIDENHAIN absolute encoder outputs a signal after receiving the instruction sent by the HEIDENHAIN absolute encoder signal processing unit 322, and the signal is connected to the RS485 transceiver chip 2221 through the HEIDENHAIN absolute encoder signal input interface 121 to obtain a single-ended signal. The single-ended signal is input to the HEIDENHAIN absolute encoder signal processing unit 322 through the photoelectric isolation circuit 2222 and reverse Schmitt trigger 2223, and the HEIDENHAIN absolute encoder signal processing unit 322 The protocol processes the signals to obtain position values and status information.

An example diagram of a resolver signal conditioning circuit, as shown in Figure 4, the resolver signal conditioning circuit 23 includes a differential linear amplifier 231, a comparator 232, a photoelectric isolation circuit 233, a sample and hold circuit 234, an A/D converter 235, a differential linear The input end of the amplifier 231 is connected to the rotary transformer signal input interface 13, and the output end of the differential linear amplifier 231 is connected to the input end of the comparator 232 and the sample-and-hold circuit 234 respectively; The input end of the sample and hold circuit 234 is connected to the input end of the A/D converter 235; the output end of the photoelectric isolation circuit 233 and the A/D converter 235 is connected to the resolver signal processing unit 33 respectively connected to the input. The sine and cosine signals output by the resolver are respectively subjected to differential linear amplification, sampling and holding, A/D conversion, and sine and cosine signal conversion of the resolver signal conditioning circuit 23 into square wave signals and photoelectric isolation, and the resulting signals are input to the resolver signal processing The unit 33 performs processing such as direction discrimination, subdivision and counting, and the signal output unit 34 outputs the result of signal processing.

Each signal processing unit in the FPGA circuit module 3 completes signal processing according to the data characteristics of the corresponding encoder and resolver signals, and the signal output unit 34 is used to register the signal processing results of the incremental encoder, absolute encoder and resolver , and through the parameter configuration of the control register in the signal output unit 34, select and output the result of any one of the signal processing results of the incremental encoder, Tamagawa absolute encoder, Heidenhain absolute encoder and resolver , or any two signal processing results, or any three signal processing results or all signals, and the signal processing results can be output in the form of parallel signal output or serial output; parameter configuration is controlled by an external motion control unit The parameter configuration process is completed by writing the parameter configuration value to the control register in the signal output unit 34 through the parallel signal output interface 41 or the serial signal output interface 42 . Parameter configuration value: set the control register in the signal output unit 34 to n bits, n≥6, select 2 of them to control the incremental encoder, Tamagawa absolute encoder, HEIDENHAIN absolute encoder and rotary The output mode of the processing result of the transformer signal, select any 4 bits in the remaining to control whether to output the processing result of the incremental encoder, Tamagawa absolute encoder, HEIDENHAIN absolute encoder and resolver signal, when a certain When a bit is set to "1" (high level), the signal processing result controlled by this bit can be output; when a certain bit is set to "0" (low level), the signal processing result controlled by this bit cannot be exported. If the 2 bits controlling the output mode of processing results are set to "10", the result of signal processing can only be output in parallel output mode; if these 2 bits are set to "01", the result of signal processing can only be output in Output in serial output mode, if these 2 bits are set to "11", the result of signal processing can be output in parallel output mode or serial output mode, if these 2 bits are set to "00" , to prohibit the output of the signal processing result; the above is only a provision of the parameter configuration value in one case, and the user can determine it according to his own needs. The external motion control unit is the motion control unit of the equipment, which can be digital signal processor DSP, single chip microcomputer, PC, robot control unit, numerical control system control unit and so on.

In this specification, it should be pointed out that the above embodiments are only representative examples of the present invention. Apparently, the present invention is not limited to the above-mentioned specific embodiments, and various modifications, changes and variations can be made. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive. All simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention shall be deemed to belong to the protection scope of the present invention.

Claims (12)

1. the signal processing apparatus of compatible with multiple encoder and resolver interface; At least comprise signal input interface module (1), signal conditioning circuit module (2), FPGA circuit module (3); Signal output interface module (4); It is characterized in that: this device can be handled the signal of more than one encoders and resolver simultaneously, and through parameter configuration, the result of one or more signal processing is exported in selection; Signal input interface module (1) output links to each other with signal conditioning circuit module (2) input; Signal conditioning circuit module (2) output links to each other with FPGA circuit module (3) input pin, and FPGA circuit module (3) output pin links to each other with signal output interface module (4); The said signal of handling more than one encoders and resolver simultaneously is meant all compound modes of multiple encoder and signals of rotating transformer.

2. the signal processing apparatus of compatible with multiple encoder according to claim 1 and resolver interface; It is characterized in that: said signal input interface module (1) comprises incremental encoder signal input interface (11) at least; Absolute type encoder signal input interface (12), signals of rotating transformer input interface (13).

3. the signal processing apparatus of compatible with multiple encoder according to claim 1 and resolver interface; It is characterized in that: said signal conditioning circuit module (2) comprises incremental encoder signal conditioning circuit (21) at least; Absolute type encoder signal conditioning circuit (22), signals of rotating transformer modulate circuit (23).

4. the signal processing apparatus of compatible with multiple encoder according to claim 1 and resolver interface; It is characterized in that: said FPGA circuit module (3) comprises incremental encoder signal processing unit (31) at least; Absolute type encoder signal processing unit (32); Signals of rotating transformer processing unit (33); Signal output unit (34), and, adopt the programming of Verilog HDL hardware description language to realize the logic function of each unit according to the characteristics and the data format of encoder and rotary encoder output signal; Said absolute type encoder signal processing unit (32) comprises the river absolute type encoder signal processing unit (321) that rubs at least, Heidenhain absolute type encoder signal processing unit (322).

5. the signal processing apparatus of compatible with multiple encoder according to claim 1 and resolver interface is characterized in that: said signal output interface module (4) comprises parallel signal output interface (41) and serial signal output interface (42).

6. according to the signal processing apparatus of claim 1 or 3 described compatible with multiple encoder and resolver interface; It is characterized in that: said incremental encoder signal conditioning circuit (21) comprises difference single-ended signal change-over circuit (211); Photoelectric isolating circuit (212), reverse Schmidt trigger (213); The output of incremental encoder signal input interface (11) links to each other with the input of difference single-ended signal change-over circuit (211); The output of difference single-ended signal change-over circuit (211) links to each other with the input of photoelectric isolating circuit (212); The output of photoelectric isolating circuit (212) links to each other with the input of reverse Schmidt trigger (213), and the output of reverse Schmidt trigger (213) links to each other with the input of incremental encoder signal processing unit (31).

7. the signal processing apparatus of compatible with multiple encoder according to claim 1 and 2 and resolver interface is characterized in that: said absolute type encoder signal input interface (12) comprises the river absolute type encoder signal input interface that rubs at least

(121), Heidenhain absolute type encoder signal input interface (122).

8. according to the signal processing apparatus of claim 1 or 3 described compatible with multiple encoder and resolver interface; It is characterized in that: said absolute type encoder signal conditioning circuit (22) comprises the river absolute type encoder signal conditioning circuit (221) that rubs at least, Heidenhain absolute type encoder signal conditioning circuit (222).

9. according to the signal processing apparatus of claim 1,3 or 8 described compatible with multiple encoder and resolver interface; It is characterized in that: the said river absolute type encoder signal conditioning circuits (221) that rub comprise difference single-ended signal change-over circuit (2211) more; Photoelectric isolating circuit (2212), reverse Schmidt trigger (2213); The river absolute type encoder signal input interface (121) that rubs links to each other with an end of difference single-ended signal change-over circuit (2211) more; The other end of difference single-ended signal change-over circuit (2211) links to each other with an end of photoelectric isolating circuit (2212); The other end of photoelectric isolating circuit (2212) links to each other with an end of reverse Schmidt trigger (2213), and the other end of reverse Schmidt trigger (2213) links to each other with an end of the river absolute type encoder signal processing unit (321) that rubs more.

10. according to the signal processing apparatus of claim 1,3 or 8 described compatible with multiple encoder and resolver interface; It is characterized in that: said Heidenhain absolute type encoder signal conditioning circuit (222) comprises RS485 transceiving chip (2221); Photoelectric isolating circuit (2222), reverse Schmidt trigger (2223); One end of RS485 transceiving chip (2221) links to each other with Heidenhain absolute type encoder signal input interface (122); The other end of RS485 transceiving chip (2221) links to each other with an end of photoelectric isolating circuit (2222); The other end of photoelectric isolating circuit (2222) links to each other with an end of reverse Schmidt trigger (2223), and reverse Schmidt trigger (2223) other end links to each other with an end of Heidenhain absolute type encoder signal processing unit (322).

11. signal processing apparatus according to claim 1 or 3 described compatible with multiple encoder and resolver interface; It is characterized in that: said signals of rotating transformer modulate circuit (23) comprises differential linearity amplifier (231); Comparator (232); Photoelectric isolating circuit (233), sampling hold circuit (234), A/D converter (235); The input termination signals of rotating transformer input interface (13) of differential linearity amplifier (231); The output of differential linearity amplifier (231) links to each other with the input of comparator (232) with sampling hold circuit (234) respectively; The output of comparator (232) links to each other with the input of photoelectric isolating circuit (233); The output of sampling hold circuit (234) links to each other with the input of A/D converter (235), and the output of photoelectric isolating circuit (233) and A/D converter (235) links to each other with the input of signals of rotating transformer processing unit (33) respectively.

12. signal processing apparatus according to claim 1,4 or 5 described compatible with multiple encoder and resolver interface; It is characterized in that: said signal output unit (34) is used to deposit the signal processing results of incremental encoder, absolute type encoder and resolver; Through parameter configuration, select the result of one or more signal processing of output to the control register in the signal output unit (34); The result of said more than one signal processing is all compound modes of multiple encoder and signals of rotating transformer result; Said parameter configuration is to write the parameter configuration value by external motion control unit through parallel signal output interface (41) or the control register of serial signal output interface (42) in signal output unit (34), accomplishes the parameter configuration process.

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