CN103150143A - Five-assembly line digital signal processor based on FPGA - Google Patents
Five-assembly line digital signal processor based on FPGA Download PDFInfo
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- CN103150143A CN103150143A CN2013100462557A CN201310046255A CN103150143A CN 103150143 A CN103150143 A CN 103150143A CN 2013100462557 A CN2013100462557 A CN 2013100462557A CN 201310046255 A CN201310046255 A CN 201310046255A CN 103150143 A CN103150143 A CN 103150143A
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Abstract
A five-assembly line digital signal processor based on FPGA (Field Programmable Gate Array) relates to the field of digital signal processors, and comprises a command storer, a first data memory, a second data memory and a third data memory, a digital signal processing arithmetic element, a logical operation unit, an operand A selector, an operand B selector, an operand C selector, an operand L selector, a branched logic circuit, a program counter, a data shifter, a shifter P1, a shifter, P2 a register P, a register S, a first selector, a second selector, a third selector, a fourth selector, a fifth selector, a sixth selector, a first logic circuit, a second logic circuit, a third logic circuit, a fourth logic circuit, a fifth logic circuit and a sixth logic circuit. The five-assembly line digital signal processor based on FPGA can achieve complex control calculation required by a high-power electricity and electronic device, the actuating efficiency is high, program development is easy, the maintenance is easy, and only a small quantity of FPGA logic resource is occupied.
Description
Technical field:
The present invention relates to the digital signal processor field, be specifically related to a kind of five pipelined digital signal processors based on FPGA.
Background technology:
At present, the control of high power electronic equipment has realized digitizing substantially, namely uses analog to digital converter to gather analog quantity, uses these samplings of digital signal processor processes, and controls output by digital to analog converter or pulse modulation technology.
Along with the raising of market to the high power electronic equipment performance requirement, the complexity of control algorithm also sharply rises.Such as active power filter device, need to extract simultaneously 50 harmonic waves, and current limliting is distinguished in the compensation of these 50 harmonic waves, and all these computings need to be completed in 1 control cycle (only less than 50 microseconds).This just requires digital signal processor that high speed and efficient will be arranged.
Usually, the digital signal processor for high power electronic equipment can have following several form:
1, nextport universal digital signal processor NextPort, this digital signal processor may operate in higher frequency, generally in about 100MHz, although digital signal processing capability not a little less than, the following aspects has limited the performance of its performance:
A) instruction and constant are stored in the FLASH ROM storer of low speed, or the DRAM storer of latent time is arranged.
B) most of instructions can not DASD, the reference-to storage must be by loading or the storage instruction, and each instruction cycle can only access 1 time.
C) for the multiple pipeline digital signal processor, the register conflict of adjacent instructions can cause pipeline blocking, reduces and carries out efficient.
D) because register quantity is more, the stack manipulation during interrupt usually can spend a large amount of instruction cycles.
Therefore, use nextport universal digital signal processor NextPort usually to need the multi-disc parallel processing, and need to simplify Processing tasks, can realize.
2, realize digital signal processing based on the logical circuit of FPGA, utilize the advantage of FPGA parallel processing can realize the digital signal processing task of various high speeds, but this scheme also has several shortcomings:
A) the programming difficulty is large, and the construction cycle is long, for this occasion that needs complicated digital signal to process computing of Active Power Filter-APF, develops with hardware description language merely, and workload is huge.
B) programmed readability is relatively poor, uses the digital signal processing unit of hardware description language exploitation, is combined by some hardware cells, is difficult to and the DSP program hook, and therefore inconvenience is read.
C) difficult in maintenance, even a small amount of the modification usually involves the modification of a lot of signals and parts, mistakes and omissions easily appear.
3, dedicated digital signal processor (ASIC), although performance is original, cost of development is huge, is not suitable for the digital signal processing of high power electronic equipment.
Summary of the invention:
The purpose of this invention is to provide a kind of five pipelined digital signal processors based on FPGA, it can be completed the control of the needed complexity of high power electronic equipment and calculate, and carries out efficient high, and program is easy to exploitation, be easy to safeguard, only take a small amount of fpga logic resource.
in order to solve the existing problem of background technology, the present invention is by the following technical solutions: it comprises command memory ZC, the first data-carrier store-the 3rd data-carrier store SC1-SC3, digital signal processing arithmetic element SCY, arithmetic logic unit LY, operand A selector switch CX1, operand B selector switch CX2, operand C selector switch CX3, operand L selector switch CX4, the logical circuit FL of branch, programmable counter CJ, data shift unit SY, P1 shift unit Y1, P2 shift unit Y2, P register J1, source register J2, first selector-Di six selector switch X1-X6, the first logical circuit-the 6th logical circuit L1-L6, the end of command memory ZC respectively with the end of programmable counter CJ, 4 pin of first selector X1 connect, and the other end of programmable counter CJ is connected with 1 pin of first selector X1, the other end of command memory ZC respectively with 3 pin of first selector X1, 2 pin of the logical circuit FL of branch, 1 pin of second selector X2, 4 pin of second selector X2, 2 pin of the first data-carrier store SC1, 1 pin of the first logical circuit L1, 1 pin of the 4th selector switch X4, 1 pin of the 5th selector switch X5, 1 pin of data shift unit SY, 1 pin of the second data-carrier store SC2, 2 pin of the second data-carrier store SC2, 1 pin of the second logical circuit L2, 4 pin of the 4th selector switch X4, 4 pin of the 5th selector switch X5, 4 pin of the 6th selector switch X6, 2 pin of third selector X3, the end of the 3rd logical circuit L3, 3 pin of the 3rd data-carrier store SC3 connect, 1 pin of the 5th logical circuit L5, 2 pin of arithmetic logic unit LY, 5 pin of digital signal processing arithmetic element SCY, 1 pin of source register J2, 2 pin of the 6th logical circuit L6, 1 pin of P register J1, 2 pin of P1 shift unit Y1, 2 pin of P2 shift unit Y2 connect, and 5 pin of first selector X1 are connected with 4 pin of the logical circuit FL of branch, 3 pin of the logical circuit FL of branch respectively with 2 pin of the first logical circuit L1, 2 pin of the second logical circuit L2, 2 pin of the 5th logical circuit L5, 3 pin of source register J2, 3 pin of the 6th logical circuit L6 connect, and 3 pin of second selector X2 are connected with 1 pin of the first data-carrier store SC1,2 pin of second selector X2 respectively with 5 pin of the 3rd data-carrier store SC3, 2 pin of the 6th selector switch X6, 3 pin of operand L selector switch CX4, 2 pin of the 5th selector switch X5 connect, 3 pin of the first data-carrier store SC1 are connected with 3 pin of the first logical circuit L1,4 pin of the first data-carrier store SC1 are connected with 2 pin of operand B selector switch CX2,5 pin of the first data-carrier store SC1 respectively with 5 pin of the second data-carrier store SC2, 6 pin of the 3rd data-carrier store SC3, 1 pin of P1 shift unit Y1 connects, and 3 pin of the second data-carrier store SC2 are connected with 3 pin of the second logical circuit L2,4 pin of the second data-carrier store SC2 respectively with 2 pin of data shift unit SY, 2 pin of operand L selector switch CX4 connect, and 3 pin of third selector X3 are connected with 1 pin of the 3rd data-carrier store SC3,4 pin of third selector X3 respectively with the other end of the 3rd logical circuit L3, 1 pin of the 4th logical circuit L4 connects, 3 pin of the 4th logical circuit L4 are connected with 2 pin of the 3rd data-carrier store SC3,4 pin of the 3rd data-carrier store SC3 are connected with 3 pin of the 5th logical circuit L5,2 pin of the 4th selector switch X4 respectively with 3 pin of data shift unit SY, 1 pin of the 6th selector switch X6, 2 pin of operand A selector switch CX1 connect, 3 pin of the 4th selector switch X4 are connected with 3 pin of operand B selector switch CX2,3 pin of the 5th selector switch X5 are connected with 3 pin of operand A selector switch CX1,3 pin of the 6th selector switch X6 are connected with 3 pin of operand C selector switch CX3,1 pin of operand A selector switch CX1 respectively with 1 pin of operand C selector switch CX3, 3 pin of P2 shift unit Y2, 3 pin of P1 shift unit Y1, 2 pin of P register J1, 1 pin of operand L selector switch CX4 connects, 4 pin of operand A selector switch CX1 respectively with 6 pin of operand A selector switch CX1, 2 pin of digital signal processing arithmetic element SCY connect, 5 pin of operand A selector switch CX1 respectively with 5 pin of operand B selector switch CX2, 5 pin of operand C selector switch CX3, 5 pin of operand L selector switch CX4 connect, 1 pin of operand B selector switch CX2 respectively with 2 pin of operand C selector switch CX3, 1 pin of P2 shift unit Y2 connects, 4 pin of operand B selector switch CX2 respectively with 6 pin of operand B selector switch CX2, 3 pin of digital signal processing arithmetic element SCY connect, 4 pin of operand C selector switch CX3 respectively with 6 pin of operand C selector switch CX3, 1 pin of digital signal processing arithmetic element SCY connects, 4 pin of operand L selector switch CX4 respectively with 6 pin of operand L selector switch CX4, 1 pin of arithmetic logic unit LY connects, and 3 pin of arithmetic logic unit LY are connected with 4 pin of digital signal processing arithmetic element SCY, 6 pin of digital signal processing arithmetic element SCY respectively with 3 pin of P register J1, 2 pin of source register J2 connect.
The present invention is on the SPARTAN6 of XILINX Series FPGA, its frequency of operation can reach 100MHz, use for Active Power Filter-APF, completing 50 harmonic waves detects, amplitude limit to 50 harmonic compensations is also controlled respectively, realize simultaneously total effective value amplitude limit, altogether only need to less than 1000 clock period, be less than 10 microseconds and can complete control algorithm.Simultaneously, on the XC6SLX45 chip, the logical resource utilization rate only has 3%, has reached the desired design target.
The present invention can complete the control of the needed complexity of high power electronic equipment and calculate, and carries out efficient high, and program is easy to exploitation, is easy to safeguard, only takies a small amount of fpga logic resource.
Description of drawings:
Fig. 1 is hardware configuration schematic diagram of the present invention.
Embodiment:
referring to Fig. 1, this embodiment by the following technical solutions: it comprises command memory ZC, the first data-carrier store-the 3rd data-carrier store SC1-SC3, digital signal processing arithmetic element SCY, arithmetic logic unit LY, operand A selector switch CX1, operand B selector switch CX2, operand C selector switch CX3, operand L selector switch CX4, the logical circuit FL of branch, programmable counter CJ, data shift unit SY, P1 shift unit Y1, P2 shift unit Y2, P register J1, source register J2, first selector-Di six selector switch X1-X6, the first logical circuit-the 6th logical circuit L1-L6, the end of command memory ZC respectively with the end of programmable counter CJ, 4 pin of first selector X1 connect, and the other end of programmable counter CJ is connected with 1 pin of first selector X1, the other end of command memory ZC respectively with 3 pin of first selector X1, 2 pin of the logical circuit FL of branch, 1 pin of second selector X2, 4 pin of second selector X2, 2 pin of the first data-carrier store SC1, 1 pin of the first logical circuit L1, 1 pin of the 4th selector switch X4, 1 pin of the 5th selector switch X5, 1 pin of data shift unit SY, 1 pin of the second data-carrier store SC2, 2 pin of the second data-carrier store SC2, 1 pin of the second logical circuit L2, 4 pin of the 4th selector switch X4, 4 pin of the 5th selector switch X5, 4 pin of the 6th selector switch X6, 2 pin of third selector X3, the end of the 3rd logical circuit L3, 3 pin of the 3rd data-carrier store SC3 connect, 1 pin of the 5th logical circuit L5, 2 pin of arithmetic logic unit LY, 5 pin of digital signal processing arithmetic element SCY, 1 pin of source register J2, 2 pin of the 6th logical circuit L6, 1 pin of P register J1, 2 pin of P1 shift unit Y1, 2 pin of P2 shift unit Y2 connect, and 5 pin of first selector X1 are connected with 4 pin of the logical circuit FL of branch, 3 pin of the logical circuit FL of branch respectively with 2 pin of the first logical circuit L1, 2 pin of the second logical circuit L2, 2 pin of the 5th logical circuit L5, 3 pin of source register J2, 3 pin of the 6th logical circuit L6 connect, and 3 pin of second selector X2 are connected with 1 pin of the first data-carrier store SC1,2 pin of second selector X2 respectively with 5 pin of the 3rd data-carrier store SC3, 2 pin of the 6th selector switch X6, 3 pin of operand L selector switch CX4, 2 pin of the 5th selector switch X5 connect, 3 pin of the first data-carrier store SC1 are connected with 3 pin of the first logical circuit L1,4 pin of the first data-carrier store SC1 are connected with 2 pin of operand B selector switch CX2,5 pin of the first data-carrier store SC1 respectively with 5 pin of the second data-carrier store SC2, 6 pin of the 3rd data-carrier store SC3, 1 pin of P1 shift unit Y1 connects, and 3 pin of the second data-carrier store SC2 are connected with 3 pin of the second logical circuit L2,4 pin of the second data-carrier store SC2 respectively with 2 pin of data shift unit SY, 2 pin of operand L selector switch CX4 connect, and 3 pin of third selector X3 are connected with 1 pin of the 3rd data-carrier store SC3,4 pin of third selector X3 respectively with the other end of the 3rd logical circuit L3, 1 pin of the 4th logical circuit L4 connects, 3 pin of the 4th logical circuit L4 are connected with 2 pin of the 3rd data-carrier store SC3,4 pin of the 3rd data-carrier store SC3 are connected with 3 pin of the 5th logical circuit L5,2 pin of the 4th selector switch X4 respectively with 3 pin of data shift unit SY, 1 pin of the 6th selector switch X6, 2 pin of operand A selector switch CX1 connect, 3 pin of the 4th selector switch X4 are connected with 3 pin of operand B selector switch CX2,3 pin of the 5th selector switch X5 are connected with 3 pin of operand A selector switch CX1,3 pin of the 6th selector switch X6 are connected with 3 pin of operand C selector switch CX3,1 pin of operand A selector switch CX1 respectively with 1 pin of operand C selector switch CX3, 3 pin of P2 shift unit Y2, 3 pin of P1 shift unit Y1, 2 pin of P register J1, 1 pin of operand L selector switch CX4 connects, 4 pin of operand A selector switch CX1 respectively with 6 pin of operand A selector switch CX1, 2 pin of digital signal processing arithmetic element SCY connect, 5 pin of operand A selector switch CX1 respectively with 5 pin of operand B selector switch CX2, 5 pin of operand C selector switch CX3, 5 pin of operand L selector switch CX4 connect, 1 pin of operand B selector switch CX2 respectively with 2 pin of operand C selector switch CX3, 1 pin of P2 shift unit Y2 connects, 4 pin of operand B selector switch CX2 respectively with 6 pin of operand B selector switch CX2, 3 pin of digital signal processing arithmetic element SCY connect, 4 pin of operand C selector switch CX3 respectively with 6 pin of operand C selector switch CX3, 1 pin of digital signal processing arithmetic element SCY connects, 4 pin of operand L selector switch CX4 respectively with 6 pin of operand L selector switch CX4, 1 pin of arithmetic logic unit LY connects, and 3 pin of arithmetic logic unit LY are connected with 4 pin of digital signal processing arithmetic element SCY, 6 pin of digital signal processing arithmetic element SCY respectively with 3 pin of P register J1, 2 pin of source register J2 connect.
This embodiment is on the SPARTAN6 of XILINX Series FPGA, its frequency of operation can reach 100MHz, use for Active Power Filter-APF, completing 50 harmonic waves detects, amplitude limit to 50 harmonic compensations is also controlled respectively, realize simultaneously total effective value amplitude limit, altogether only need to less than 1000 clock period, be less than 10 microseconds and can complete control algorithm.Simultaneously, on the XC6SLX45 chip, the logical resource utilization rate only has 3%, has reached the desired design target.
This embodiment can be completed the control of the needed complexity of high power electronic equipment and calculate, and carries out efficient high, and program is easy to exploitation, is easy to safeguard, only takies a small amount of fpga logic resource.
Claims (1)
1. five pipelined digital signal processors based on FPGA, is characterized in that it comprises command memory (ZC), the first data-carrier store-the 3rd data-carrier store (SC1-SC3), digital signal processing arithmetic element (SCY), arithmetic logic unit (LY), operand A selector switch (CX1), operand B selector switch (CX2), operand C selector switch (CX3), operand L selector switch (CX4), branch's logical circuit (FL), programmable counter (CJ), data shift unit (SY), P1 shift unit (Y1), P2 shift unit (Y2), P register (J1), source register (J2), first selector-Di six selector switchs (X1-X6), the first logical circuit-the 6th logical circuit (L1-L6), an end of command memory (ZC) respectively with an end of programmable counter (CJ), 4 pin of first selector (X1) connect, and the other end of programmable counter (CJ) is connected with 1 pin of first selector (X1), the other end of command memory (ZC) respectively with 3 pin of first selector (X1), 2 pin of branch's logical circuit (FL), 1 pin of second selector (X2), 4 pin of second selector (X2), 2 pin of the first data-carrier store (SC1), 1 pin of the first logical circuit (L1), 1 pin of the 4th selector switch (X4), 1 pin of the 5th selector switch (X5), 1 pin of data shift unit (SY), 1 pin of the second data-carrier store (SC2), 2 pin of the second data-carrier store (SC2), 1 pin of the second logical circuit (L2), 4 pin of the 4th selector switch (X4), 4 pin of the 5th selector switch (X5), 4 pin of the 6th selector switch (X6), 2 pin of third selector (X3), one end of the 3rd logical circuit (L3), 3 pin of the 3rd data-carrier store (SC3) connect, 1 pin of the 5th logical circuit (L5), 2 pin of arithmetic logic unit (LY), 5 pin of digital signal processing arithmetic element (SCY), 1 pin of source register (J2), 2 pin of the 6th logical circuit (L6), 1 pin of P register (J1), 2 pin of P1 shift unit (Y1), 2 pin of P2 shift unit (Y2) connect, and 5 pin of first selector (X1) are connected with 4 pin of branch's logical circuit (FL), 3 pin of branch's logical circuit (FL) respectively with 2 pin of the first logical circuit (L1), 2 pin of the second logical circuit (L2), 2 pin of the 5th logical circuit (L5), 3 pin of source register (J2), 3 pin of the 6th logical circuit (L6) connect, and 3 pin of second selector (X2) are connected with 1 pin of the first data-carrier store (SC1), 2 pin of second selector (X2) respectively with 5 pin of the 3rd data-carrier store (SC3), 2 pin of the 6th selector switch (X6), 3 pin of operand L selector switch (CX4), 2 pin of the 5th selector switch (X5) connect, 3 pin of the first data-carrier store (SC1) are connected with 3 pin of the first logical circuit (L1), 4 pin of the first data-carrier store (SC1) are connected with 2 pin of operand B selector switch (CX2), 5 pin of the first data-carrier store (SC1) respectively with 5 pin of the second data-carrier store (SC2), 6 pin of the 3rd data-carrier store (SC3), 1 pin of P1 shift unit (Y1) connects, and 3 pin of the second data-carrier store (SC2) are connected with 3 pin of the second logical circuit (L2), 4 pin of the second data-carrier store (SC2) respectively with 2 pin of data shift unit (SY), 2 pin of operand L selector switch (CX4) connect, and 3 pin of third selector (X3) are connected with 1 pin of the 3rd data-carrier store (SC3), 4 pin of third selector (X3) respectively with the other end of the 3rd logical circuit (L3), 1 pin of the 4th logical circuit (L4) connects, 3 pin of the 4th logical circuit (L4) are connected with 2 pin of the 3rd data-carrier store (SC3), 4 pin of the 3rd data-carrier store (SC3) are connected with 3 pin of the 5th logical circuit (L5), 2 pin of the 4th selector switch (X4) respectively with 3 pin of data shift unit (SY), 1 pin of the 6th selector switch (X6), 2 pin of operand A selector switch (CX1) connect, 3 pin of the 4th selector switch (X4) are connected with 3 pin of operand B selector switch (CX2), 3 pin of the 5th selector switch (X5) are connected with 3 pin of operand A selector switch (CX1), 3 pin of the 6th selector switch (X6) are connected with 3 pin of operand C selector switch (CX3), 1 pin of operand A selector switch (CX1) respectively with 1 pin of operand C selector switch (CX3), 3 pin of P2 shift unit (Y2), 3 pin of P1 shift unit (Y1), 2 pin of P register (J1), 1 pin of operand L selector switch (CX4) connects, 4 pin of operand A selector switch (CX1) respectively with 6 pin of operand A selector switch (CX1), 2 pin of digital signal processing arithmetic element (SCY) connect, 5 pin of operand A selector switch (CX1) respectively with 5 pin of operand B selector switch (CX2), 5 pin of operand C selector switch (CX3), 5 pin of operand L selector switch (CX4) connect, 1 pin of operand B selector switch (CX2) respectively with 2 pin of operand C selector switch (CX3), 1 pin of P2 shift unit (Y2) connects, 4 pin of operand B selector switch (CX2) respectively with 6 pin of operand B selector switch (CX2), 3 pin of digital signal processing arithmetic element (SCY) connect, 4 pin of operand C selector switch (CX3) respectively with 6 pin of operand C selector switch (CX3), 1 pin of digital signal processing arithmetic element (SCY) connects, 4 pin of operand L selector switch (CX4) respectively with 6 pin of operand L selector switch (CX4), 1 pin of arithmetic logic unit (LY) connects, 3 pin of arithmetic logic unit (LY) are connected with 4 pin of digital signal processing arithmetic element (SCY), 6 pin of digital signal processing arithmetic element (SCY) respectively with 3 pin of P register (J1), 2 pin of source register (J2) connect.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20020133690A1 (en) * | 2000-12-06 | 2002-09-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
| CN1521631A (en) * | 2003-02-13 | 2004-08-18 | 上海汉芯半导体科技有限公司 | Digital signal processor with a repeatable switching buffer memory |
| CN203133813U (en) * | 2013-02-06 | 2013-08-14 | 王鸿雁 | Five processing line digital signal processor based on FPGA |
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2013
- 2013-02-06 CN CN2013100462557A patent/CN103150143A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020133690A1 (en) * | 2000-12-06 | 2002-09-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
| CN1521631A (en) * | 2003-02-13 | 2004-08-18 | 上海汉芯半导体科技有限公司 | Digital signal processor with a repeatable switching buffer memory |
| CN203133813U (en) * | 2013-02-06 | 2013-08-14 | 王鸿雁 | Five processing line digital signal processor based on FPGA |
Non-Patent Citations (1)
| Title |
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| 徐军等: "用FPGA实现多路PWM输出的接口设计与仿真", 《电子工程师》, vol. 33, no. 5, 15 May 2007 (2007-05-15), pages 42 - 44 * |
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