RU72339U1 - MULTI-PROCESSOR COMPUTER SYSTEM MODULE (OPTIONS) - Google Patents

Abstract

The utility model relates to the field of computer engineering, namely to solving labor-intensive computing problems, for example, problems of mathematical physics, linear algebra, modeling of complex systems and can be used in multiprocessor computing systems with distributed memory (mass parallelism). A multiprocessor computing system module designed for parallel-pipelined computing contains a block of macroprocessors based on programmable logic integrated circuits, distributed memory controllers, a call controller that implements an interface with a control device of a computing device, a distributed static memory block is introduced for each macroprocessor, and the controller calls is connected to the information inputs of the block of macroprocessors on 40 bidirectional lines and, at least at least with one block of distributed static memory, and the macro-processors are connected in a ring by 320 bidirectional lines, realizing the possibility of independent information exchange for each pair of macroprocessors sequentially placed in the ring, and each macro-processor is connected to the corresponding distributed static memory block along 65 lines, while inside pairs 2-7 and 3-6 of the macroprocessors, communication is realized along 40 radial bi-directional lines. The utility model makes it possible to increase the performance of a computing system by implementing a topology of connections between virtual processing devices of the ring type, the possibility of independent transmission / reception of signals over a full graph (each with each), and transfers between virtual devices located in adjacent FPGAs of a module in 1 clock cycle lines up to 320 bits long.

Description

The utility model relates to the field of computer engineering, namely to solving labor-intensive computing problems, for example, problems of mathematical physics, linear algebra, modeling complex systems and can be used in multiprocessor computing systems with distributed memory (mass parallelism).

There are a number of distributed memory computing systems containing processors integrated by some communication medium. The most famous among them are: Intel Paragon, IBM SP1 / SP2, Cray T3D and many others, including domestic cluster and mass-parallel installations, for example, MVS-1000M, SKIF Syberia, etc.

These systems mainly differ from each other by the type of processor elements and the communication medium used. Each processor element (PE) contains a processor or several processors, a local memory and an interface for communication with other processor elements. The local memory of each PE is part of the physically distributed, but logically shared memory of the entire computer. Data processing is carried out by processors - devices with programmed control and hard-set logic.

The main disadvantage of such computing systems is low productivity in solving real problems.

The reasons for this drawback are, firstly, in a rigid architecture, due to which the available resources cannot be used completely - a significant part of the processor equipment is idle, waiting for either data not coming from memory or the commands for which this part of the equipment is intended. The second reason for the disadvantage is the large gap between the performance on the one hand, of the processor itself, on the other hand, of RAM and the communication environment.

A number of modules based on programmable logic are known, which are analog-digital receivers and filters with a small total gate resource and a rich interface set. The most widely used of them were modules: XDSP-xMC, ADC-xx, PLISAR-xxx, DSP35X3-xxxx, a specialized line of modules of domestic production M-5xx and others.

The main disadvantage of such modules is the small total valve resource. Often, such products do not provide the function of changing the configuration of programmable logic integrated circuits (FPGA) to perform a different task.

The reason for this drawback is laid at the stage of product design in accordance with the expected functional loads. The available computing power fully satisfies the declared digital processing algorithms according to the available logical resource, and the developed pipeline implementations of the same algorithms - according to the processing speed of the entire volume of the input (output) schedule.

A close analogue of the proposed utility model for functional purpose is the line of computing modules RSP-504, RSP-506, RSP-512 and RSP-517 produced by the domestic company OOO NPO Rosta. These modules are PMC mezzanine modules and are designed to develop high-speed digital data processing devices using FPGA technology. Each module carries on itself two crystals with a tunable architecture of the advanced Virtex II and Virtex 4 series.

The main disadvantage of the RSP series modules is the limited amount of the common gate field, in some cases, which does not allow to efficiently place the entire algorithm in the module.

The reason for this drawback is the presence of only two FPGA crystals on one module, interconnected by an internal bus from 132 to 155 discharges. These modules contain a large number of heterogeneous external interfaces: PMC, LVDS, Local Bus, Expansion Bus, Side Bus, Control Bus. Given the mandatory presence of the entire service periphery (switching and energy bridges, storage devices, generators, etc.),

a limit is formed on the width of the instant line between user FPGAs to 155 lines.

As the closest analogue, i.e. of the prototype, one can cite the invention “Multiprocessor system module” (patent RU No. 2282236, publ. 2006.08.20), containing RAM, a block of multicontrollers of distributed memory, a matrix switch, a block of macroprocessors. This computational module with a tunable architecture, developed by the SRI MVS TRTU, as well as the proposed utility model, has several FPGAs and is functionally designed to solve computationally time-consuming fragments of tasks.

The disadvantage of this invention is the impossibility of constructing a conveyor implementation of a digital data processing algorithm on a common valve field of a module without frequency restrictions imposed by the communication circuit of the computing elements of the module.

The reason for the drawback is the organization of the sharing of valve resources of all FPGAs as a common decisive field through a matrix switch, which imposes high requirements on the synchronization of the final project and limits the information exchange between the crystals.

The problem to which the proposed utility model is directed is to create a multicrystal module of a multiprocessor computing system, which will provide the possibility of pipelining an algorithm for digital processing of information on the common gate field of all computing elements, providing an increase in the performance of the computing module.

This problem is solved by creating a multiprocessor computing system module for performing parallel-pipelined computing, containing a block of macroprocessors based on programmable logic integrated circuits, distributed memory controllers, an access controller that implements an interface with a control machine of a computing device is additionally introduced into it, additionally, at least four macroprocessors, and each distribution microprocessor includes a distribution controller ennoy memory, for each

a distributed static memory unit is introduced, the access controller is connected to the information inputs of the macro-processor unit via bi-directional lines and at least one distributed static memory unit, and the macro-processors are combined in a ring along bi-directional lines, realizing the possibility of independent information exchange for each pair sequentially placed in the ring of macroprocessors, and each macroprocessor is associated with a corresponding block of distributed static memory and wherein the inside two pairs macroprocessor implemented bidirectional communication lines.

In addition, the macro-processors are ringed along 320 bi-directional lines.

In addition, each macro processor is associated with a corresponding block of distributed static memory along 65 lines.

In addition, within pairs of macroprocessors 2-7 and 3-6, communication is implemented along 40 radial bi-directional lines.

This task according to option 2 is solved by creating a module of a multiprocessor computing system designed to perform parallel-pipelined computing, containing a block of macroprocessors based on programmable logic integrated circuits, distributed memory controllers, characterized in that a call controller is introduced into it, which implements an interface with a computer control machine devices, additionally, at least four macroprocessors are introduced into the block of macroprocessors, moreover, the composition of each macro a distributed memory controller is included in the processor, and a distributed static memory block is introduced for each macro processor, and the access controller is connected to information inputs of the macro processor block via 40 bi-directional lines and at least one distributed static memory block, with the macro processors combined in a ring of 320 bidirectional lines, realizing the possibility of independent information exchange for each pair of macroprocessors sequentially placed in the ring, and each macroprocess op associated with a respective unit distributed static memory 65 lines, the inside of the two pairs is realized macroprocessor

communication on bi-directional lines 2-7 and 3-6, communication on 40 radial bi-directional lines is implemented.

The performance limit for the created pipeline is only the maximum amount of information (40 bytes) transferred between the crystals of the module.

The technical result achieved by the implementation of the utility model consists in a coordinated pace of processing and exchange of information on all elements of the module.

To achieve the specified technical result in a utility model, as in the prototype, instead of processor elements introduced macro-processors (MAP) implemented in FPGA. In contrast to the specified prototype, the proposed utility model has, instead of a matrix switch, on the one hand expanding the class of tasks to be solved, on the other hand, using resources and not allowing exchanges between words of the required bit depth, the ring switching topology is used. Which on a number of tasks (when placing the conveyor in several crystals), gives a noticeable gain in performance.

A causal relationship between the set of essential features of the claimed utility model and the technical result achieved is as follows: a fixed topology "ring" allows to increase the performance of the computing module in solving problems due to the structural organization of large operations when it is necessary to place conveyor elements in various macroprocessors (FPGAs) and transferring between them strings up to 320 bits, i.e. the possibility of obtaining higher performance, in contrast to the prototype, in which each unit solves its own problem.

In the future, the proposed utility model is illustrated by specific examples of its implementation and the accompanying drawings, in which:

Fig 1 - depicts a block diagram of a module of a multiprocessor system.

Figure 2 - depicts a block diagram of a high-performance computing device (VVU)

Figure 3 depicts a block diagram of a multiprocessor system module, which shows the loading channels of the FPGA configuration of the base module.

Figure 4 - depicts the format of the configuration registers of the access controller (TO).

The following notation is used on the block diagram of a multiprocessor system module, shown in FIG. 1: VE i — the computing element (macro processor) of the module, KO — the access controller, RAM — the static memory bank, P — connectors. The access controller 9 is intended for information exchange of the module with the computer, which is a control controller 32 (control PC (computer) type IBM PC). KO 9 provides communication between the PCI bus and FPGA chips, which include a distributed memory controller (KRP), and also implements an interface for loading the FPGA configuration. Through connectors P on the LVDS channel is the loading of program and numerical information.

The high-performance computing unit of the VVU (Fig. 2) consists of a module of a multiprocessor computing system 29 connected to a computer through an interface card LVDS channel 31, which provides high-speed exchange between the module of the multiprocessor computer system and the computer.

The multiprocessor system module 29 according to options 1, 2 (Fig. 1) contains a block of macroprocessors based on programmable logic integrated circuits 1-8, each of which includes a distributed memory controller that provides information exchange with the corresponding distributed static memory unit, access controller 9 that implements the interface with the control machine of the computing device (figure 2), while the access controller 9 is connected to the information inputs of the block of macroprocessors 1 and 8 in bidirectional lines and, in m at least, with one block of distributed static memory 13-20, and the macroprocessors 1-8 are connected in a ring by bidirectional lines, realizing the possibility of independent information exchange for each pair of macroprocessors sequentially placed in the ring, and each macroprocessor 1-8 is connected to the corresponding block distributed static memory 21-28.

In addition, the macroprocessors 1-8 are combined in a ring along 320 bidirectional lines.

In addition, each macroprocessor 1-8 is associated with a corresponding block of distributed static memory along 65 lines.

In addition, within pairs of 2-7 and 3-6 macroprocessors, communication is carried out along 40 radial bi-directional lines.

Download software and numerical information through connectors 11, 12.

The device according to options 1, 2 works as follows.

The operation of the device is demonstrated in the best example of execution, shown in figures 1-4. In a block of macro-processors based on programmable logic integrated circuits 1-8, a group of eight macro-processors is considered as a configuration-indivisible unit. The unit can only be configured in its entirety. Before starting the configuration, set the corresponding PROG bit to zero, which will reset the previous FPGA configuration. After setting the PROG bit to one, you can put the FPGA in the standby state.

To implement the download configuration of the FPGA 1-8, two 32-bit configuration registers PK0 36 and PK1 37 were introduced into the access controller 9; FIG. 4.

PK0 configuration register 36.

Discharges (31 ÷ 24) -DATA3 (7: 0), (23 ÷ 16) -DATA2 (7: 0), (15 ÷ 8) -DATA1 (7: 0), (7 ÷ 0) -DATA0 (7: 0) correspond to the bytes of the configuration file loaded into the FPGA.

RK137 configuration register.

The bits (31 ÷ 28) -DONE 1 (3: 0) correspond to the DONE signals — the end of the configuration process coming from the FPGA of the first BM column.

The bits (25 ÷ 24) -PROG_B (1: 0) correspond to the PROG signals — configuration reset applied to all FPGAs of the corresponding BM column.

The digits (23 ÷ 22) -NUM_COLUNM (1: 0) correspond to the selection of the corresponding BM column.

The bits (21 ÷ 20) -NUM_CHIP (1: 0) correspond to the selection of the corresponding FPGA in the BM column.

The bits (15 ÷ 12) -DONE0 (3: 0) correspond to the DONE signals — the end of the configuration process coming from the FPGA of the zero column of the BM.

The remaining bits of the register PK1 are not used (N.U.).

If the FPGA is in the standby state, then when the data arrives in the PK0 configuration register in the access controller 9, the configuration is automatically recorded in the FPGA selected in the PK1 register by generating DATA signals (original data) accompanied by differences in input / output 11-12 CCLK (set frequency) and the corresponding signals RDWR_B (read / write), CS (start / stop) (figure 3).

To load the FPGA configuration, use the LF.exe program. This program works with a boot configuration file that has the extension ba.

The user can create his own ba-file and download the original FPGA configuration. After selecting the ba-file, the program file is installed as a computational file.

The format of the boot configuration file is a sequence of lines that indicate: 0, 1, 2, 3 - the number of the loaded line of the base module; file_name j is the name of the FPGA firmware configuration file (* .bit), where j is the BMP FPGA number.

0 file_name 0 file_name 1 file_name 2 file_name 3 one file_name 4 file_name 5 file_name 6 file_name 7

If it is necessary for the FPGA part to remain unloaded, it is possible to use FPGA firmware. Configurable files should not be skipped. Download FPGA configuration by line. The DONE _i signal in each line is correctly generated only if downloading of four bit-files is used, where i is the number of the loaded line of the base module. A single DONE _i signal level means that the FPGA is loaded correctly.

After loading the data, the START command starts the analysis process.

During operation, the host computer continuously polls the access controller instruction register, in which when an event is found in any of the microcircuits, an interrupt bit is set. Then, using the READ STATUS command, the status register of each of the eight chips is sequentially polled. The status values determine the nature of the event and the number of the chip that issued the interrupt signal.

Events can be of two types: overflow of the counter of the variable part of the key and finding a match with the standard. In the first case, there is a transition to the next iteration of the analysis process with loading new values of the constant part of the key and zeroing the variable part. In the second case, the value of the variable part is read out from the chip in which a match is found using the UNLOAD COUNTER command. In the next iteration, the analysis process begins with the value of the variable part following the found one.

A multiprocessor computing system module designed for parallel-pipelined implementation of computationally-laborious tasks, the solution of which requires a significant hardware resource and is associated with a large number of tests, can be performed with the possibility of organizing calculations in 8 VIRTEX 4 LX80 FPGAs - the possibility of pipelining large operations by combining up to 8 VIRTEX 4 LX80 FPGAs into a single structure of a hardware resource, by the presence of a call controller - the VIRTEX 4 FX60 FPGA, distributed and distributed EFINITIONS 64MB (8 MB FPGA VIRTEX 4 LX80) static memory topology intercrystalline bonds "ring", a width of 320 bits intercrystalline bonds, external terminals LVDS - 28 bits.

The proposed utility model makes it possible to increase the performance of a computing system by implementing the topology of connections between virtual processing devices of the "ring" type, by implementing the possibility of independent transmission / reception of signals over a complete graph (each with each),

transfers between virtual devices located in neighboring FPGAs of a module for 1 clock of lines up to 320 bits long.

Claims (5)

1. The multiprocessor computing system module, designed to perform parallel-pipelined computing, containing a block of macroprocessors based on programmable logic integrated circuits, distributed memory controllers, characterized in that a call controller is introduced into it that implements an interface with the control machine of the computing device, in addition to the block at least four macroprocessors are introduced into the macroprocessors, with each distributed microprocessor having a distributed controller memory, and a distributed static memory block is introduced for each macro processor, while the access controller is connected to the information inputs of the macro processor block in bi-directional lines and at least one block of distributed static memory, and the macro-processors are combined in a ring along bi-directional lines, making it possible to independently information exchange for each pair of macroprocessors sequentially placed in the ring, and each macroprocessor is distributed with the corresponding block ies of static memory, while inside two pairs of macroprocessors communication is realized along bidirectional lines. 2. The multiprocessor computing system module, designed to perform parallel-pipelined computing according to claim 1, characterized in that the macro-processors are combined into a ring along 320 bidirectional lines. 3. The multiprocessor computing system module, designed to perform parallel-pipelined computing according to claim 1, characterized in that each macroprocessor is connected to the corresponding distributed static memory block along 65 lines. 4. The multiprocessor computing system module, designed to perform parallel-pipelined computing according to claim 1, characterized in that within the pairs of macroprocessors 2-7 and 3-6, communication is performed along 40 radial bi-directional lines. 5. A multiprocessor computing system module designed to perform parallel-pipelined computing, containing a block of macroprocessors based on programmable logic integrated circuits, distributed memory controllers, characterized in that a call controller is introduced into it, which implements an interface with the control machine of the computing device, in addition to the block at least four macroprocessors are introduced into the macroprocessors, with each distributed microprocessor having a distributed controller memory, and a distributed static memory block is introduced for each macro processor, while the access controller is connected to information inputs of the macro processor block through 40 bi-directional lines and at least one distributed static memory block, and the macro processors are combined into a ring along 320 bi-directional lines, realizing the possibility of independent information exchange for each pair of macroprocessors sequentially placed in the ring, and each macroprocessor is associated with a corresponding distribution block constant static memory on lines 65, and the inside of the two pairs is realized macroprocessor bidirectional communication lines 2-7 and 3-6 of the radial 40 bidirectional lines.