CN103138262A - Sampling method for active power filter - Google Patents
Sampling method for active power filter Download PDFInfo
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- CN103138262A CN103138262A CN2011103839467A CN201110383946A CN103138262A CN 103138262 A CN103138262 A CN 103138262A CN 2011103839467 A CN2011103839467 A CN 2011103839467A CN 201110383946 A CN201110383946 A CN 201110383946A CN 103138262 A CN103138262 A CN 103138262A
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- power filter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/20—Active power filtering [APF]
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Abstract
The invention discloses a sampling method for an active power filter. The sampling method for the active power filter comprises the following steps: using a field programmable gata array (FPGA) as a main control unit of a sampling system, controlling an analog to digital converter (ADC) to work in a settable sampling frequency, converting analog data of various channel into digital signals, reading a digital value of the ADC through the FPGA, momentarily storing the digital value into a random access memory inside the ADC, after conducting preprocess of the data according to a preset algorithm, sending an interrupt request to a microcontroller, and after the microcontroller receives the interrupt request, reading the data sampled by the FPGA to finish one sampling process. Due to the sampling method for the active power filter, the problems that the high speed and Synchronous sampling requirements of a filter cannot be met in the traditional sampling method are solved, and application effect of the sampling method for the active power filter is obvious.
Description
Technical field
The present invention relates to the electric-power filter technical field, specifically a kind of method of sampling for Active Power Filter-APF.
Background technology
Along with the development of technology, many power consumption equipments are more and more higher to the requirement of the quality of power supply, and the harmonic pollution problem of electrical network is more and more serious simultaneously.How suppressing mains by harmonics becomes the focus of Recent study.Active Power Filter-APF is considered to best results, harmonic compensation method that adaptability is the strongest because of its good dynamic and static performance and to the adaptive ability of electrical network load, system parameter variations always, by a large amount of employings.
Active Power Filter-APF is take the high-speed figure treatment technology as core, and its operation principle is to gather in real time by the compensation equipment voltage and current signal, exports in real time offset current after calculating again.Sample frequency is higher, and is better to its compensation effect.But traditional data acquisition modes can't satisfy the requirement of high-speed synchronous sampling.
Traditional data acquisition modes, directly to control analog to digital converter (hereinafter to be referred as ADC) work with single-chip microcomputer, this mode is used widely in the low speed sampling system, and can meet the demands, but, in High Speed Sampling System, if still sample this mode, will bring sample rate to be subjected to the single-chip microcomputer rate, affect a lot of problems such as operating efficiency, sampling channel Limited Number of single-chip microcomputer.
Summary of the invention
The purpose of this invention is to provide a kind of method of sampling for Active Power Filter-APF, traditional control analog to digital converter work with single-chip microcomputer as core to overcome, cause sample rate to be subjected to the shortcomings such as the impact of single-chip microcomputer speed, the operating efficiency that affects single-chip microcomputer, sampling channel Limited Number.
For achieving the above object, the present invention takes following technical scheme to realize: a kind of method of sampling for Active Power Filter-APF comprises the steps:
Use field programmable gate array (hereinafter to be referred as FPGA) as the temporary core cell of controlling of sampling and data in whole sampling system.FPGA ADC implement is controlled and the temporary transient ADC of preservation by the hardware bandpass filtering after adopt into digital quantity, again the algorithm prepared in advance according to FPGA to adopt into data finish preliminary treatment after, send interrupt requests to microcontroller, after microcontroller is received request, the data that FPGA is collected read into, complete sampling process one time, thereby realize the high-speed, high precision synchronous data collection.
Described sampling system is a standalone module, can be equipped with simultaneously several identical sampling modules on same device, carries out absolute synchronization sampling by microcontroller, and the sampling channel number can spread, and is unrestricted
Outstanding advantages of the present invention is:
Can overcome and traditional control analog to digital converter work with single-chip microcomputer as core, cause sample rate to be subjected to the shortcomings such as the impact of single-chip microcomputer speed, the operating efficiency that affects single-chip microcomputer, sampling channel Limited Number.
On probation in the YH-8010 Power Quality Comprehensive Treatment Device, successful significantly improves the operating efficiency of device.
Description of drawings
Fig. 1 is the hardware block diagram of the method for sampling for Active Power Filter-APF of the present invention.
Fig. 2 is the multimode work schematic diagram of the method for sampling for Active Power Filter-APF of the present invention.
Fig. 3 is the flow chart of the method for sampling for Active Power Filter-APF of the present invention.
Embodiment
Be described further below in conjunction with accompanying drawing and example high-speed synchronous data sampling method and the operation principle thereof to Active Power Filter-APF of the present invention.
As shown in Figure 1, the method for sampling for Active Power Filter-APF of the present invention comprises the steps: to use FPGA as the temporary core cell of controlling of sampling and data in whole sampling system.By its be responsible for controlling ADC samples and the data that sampling obtains are carried out preliminary treatment after, the notice MCU read.
The described method of sampling can be made individual module, and each module realizes function as shown in Figure 1, when sampling channel can't satisfy the demands, can take to increase the mode of module with the expansion sampling channel.As shown in Figure 2, a plurality of modules directly are connected with MCU, and by the coordination control work between the responsible a plurality of modules of MCU, the modules independent operating is done the high-speed synchronous sampling according to the synchronizing signal that MCU sends.
As shown in Figure 3, be the flow chart of the method for sampling for Active Power Filter-APF of the present invention, the below will do explanation one by one to each step:
1) FPGA receives the synchronizing signal that MCU sends, and proofreaies and correct sampling clock, thereby if can accomplish absolute synchronization when guaranteeing to have the polylith sampling plate to sample simultaneously;
2) FPGA controls the transfer process that ADC begins to carry out analogue data is converted to digital quantity;
3) FPGA waits for the ADC EOC
4) whether FPGA differentiation conversion finishes, if finish to continue to carry out preset program backward, waits for if finish continuation;
5) FPGA will convert the signal-obtaining of digital quantity in its inner RAM from ADC;
6) algorithm that presets according to inside of FPGA carries out algorithm process to the digital quantity that gathers, and as fast Fourier transform etc., can share the some work of MCU, increases work efficiency;
7) FPGA after digital quantity is carried out preliminary treatment completing, sends signal, notice MCU reading out data;
8) FPGA waits for that the MCU reading out data finishes;
9) whether FPGA differentiation MCU reading out data finishes, if finish to continue to carry out preset program backward, if finish to continue wait;
10) FPGA waits for that next sampling instant arrives;
11) whether the next sampling instant of FPGA differentiation arrives, if arrive, returns to step 1 and carries out sampling process again; If constantly do not arrive, continue to wait for;
12) the whole course of work arrives circulation between step 11 in step 1.
Claims (5)
1. a method of sampling that is used for Active Power Filter-APF, is characterized in that, comprises the steps:
Use on-site programmable gate array FPGA as the pretreated core cell of controlling of sampling and data in whole sampling system, to analog to digital converter ADC implement to control and the temporary transient ADC of preservation by the hardware bandpass filtering after adopt into digital quantity, again the algorithm prepared in advance according to FPGA to adopt into data finish preliminary treatment after, send interrupt requests to microcontroller, after microcontroller is received request, the data that FPGA is collected read into, complete sampling process one time.
2. the method for sampling for Active Power Filter-APF as claimed in claim 1, it is characterized in that: concrete steps are as follows:
1) FPGA receives the synchronizing signal that MCU sends, and proofreaies and correct sampling clock,
2) FPGA controls the transfer process that ADC begins to carry out analogue data is converted to digital quantity;
3) FPGA waits for the ADC EOC
4) whether FPGA differentiation conversion finishes, if finish to continue to carry out preset program backward, waits for if finish continuation;
5) FPGA will convert the signal-obtaining of digital quantity in its inner RAM from ADC;
6) algorithm that presets according to inside of FPGA carries out algorithm process to the digital quantity that gathers,
7) FPGA after digital quantity is carried out preliminary treatment completing, sends signal, notice MCU reading out data;
8) FPGA waits for that the MCU reading out data finishes;
9) whether FPGA differentiation MCU reading out data finishes, if finish to continue to carry out preset program backward, if finish to continue wait;
10) FPGA waits for that next sampling instant arrives;
11) whether the next sampling instant of FPGA differentiation arrives, if arrive, returns to step 1 and carries out sampling process again; If constantly do not arrive, continue to wait for;
12) the whole course of work arrives circulation between step 11 in step 1.
3. the method for sampling for Active Power Filter-APF as claimed in claim 1, it is characterized in that: the sample frequency of described sampling system is set by the FPGA program, Minimum sample rate 12.8kHz, i.e. 256 points of every cycle.
4. the method for sampling for Active Power Filter-APF as claimed in claim 1, it is characterized in that: described FPGA carries out preliminary treatment according to algorithm prepared in advance to sampled data.
5. the method for sampling for Active Power Filter-APF as claimed in claim 1, it is characterized in that: described sampling system is a standalone module, can be equipped with simultaneously several identical sampling modules on same device and carry out absolute synchronization sampling, the sampling channel number can spread, and is unrestricted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103839467A CN103138262A (en) | 2011-11-28 | 2011-11-28 | Sampling method for active power filter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011103839467A CN103138262A (en) | 2011-11-28 | 2011-11-28 | Sampling method for active power filter |
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| CN103138262A true CN103138262A (en) | 2013-06-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109030972A (en) * | 2018-05-04 | 2018-12-18 | 武汉精测电子集团股份有限公司 | Multichannel liquid crystal module based on FPGA tests apparatus for monitoring power supply |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0254073B1 (en) * | 1986-06-26 | 1995-01-25 | Mitsubishi Denki Kabushiki Kaisha | Harmonic suppressing device |
| CN2546955Y (en) * | 2002-05-31 | 2003-04-23 | 烟台东方电子信息产业股份有限公司 | AC sampling device |
| CN102214923A (en) * | 2011-06-01 | 2011-10-12 | 郑卫平 | Active filter controller based on double-DSP (Digital Signal Processing) and FPGA (Field-Programmable Gate Array) control system |
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2011
- 2011-11-28 CN CN2011103839467A patent/CN103138262A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0254073B1 (en) * | 1986-06-26 | 1995-01-25 | Mitsubishi Denki Kabushiki Kaisha | Harmonic suppressing device |
| CN2546955Y (en) * | 2002-05-31 | 2003-04-23 | 烟台东方电子信息产业股份有限公司 | AC sampling device |
| CN102214923A (en) * | 2011-06-01 | 2011-10-12 | 郑卫平 | Active filter controller based on double-DSP (Digital Signal Processing) and FPGA (Field-Programmable Gate Array) control system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109030972A (en) * | 2018-05-04 | 2018-12-18 | 武汉精测电子集团股份有限公司 | Multichannel liquid crystal module based on FPGA tests apparatus for monitoring power supply |
| CN109030972B (en) * | 2018-05-04 | 2021-08-13 | 武汉精测电子集团股份有限公司 | Multi-channel liquid crystal module testing power supply monitoring device based on FPGA |
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Application publication date: 20130605 |