CN103076836A - Low-power voltage complementary metal oxide semiconductor (CMOS) constant-voltage source circuit - Google Patents
Low-power voltage complementary metal oxide semiconductor (CMOS) constant-voltage source circuit Download PDFInfo
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- CN103076836A CN103076836A CN201210590969XA CN201210590969A CN103076836A CN 103076836 A CN103076836 A CN 103076836A CN 201210590969X A CN201210590969X A CN 201210590969XA CN 201210590969 A CN201210590969 A CN 201210590969A CN 103076836 A CN103076836 A CN 103076836A
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Abstract
The invention discloses a low-power voltage complementary metal oxide semiconductor (CMOS) constant-voltage source circuit, which comprises a primary starting circuit, a primary current generating circuit which is unrelated to the power voltage and influenced by the temperature, a secondary starting circuit, a secondary current generating circuit which is unrelated to the power voltage and influenced by the temperature and a branch current phase reduction circuit. By utilizing the output current of the branch current phase reduction circuit, the output voltage of low-temperature coefficient is realized through load resistance. The low-power voltage CMOS constant-voltage source circuit is free from containing a bipolar device, so that the reference voltage with low temperature coefficient is generated under the lower power voltage environment.
Description
Technical field
The present invention relates to a kind of constant voltage source circuit, specifically, relate to a kind of pure CMOS constant voltage source circuit that is operated under the low supply voltage.
Background technology
In the application of cmos circuit, usually can use the constant voltage source that all has nothing to do with supply voltage and temperature.For example at the biasing circuit of some amplifier, perhaps in some comparers.In these cases, usually need more accurate magnitude of voltage.And we know, because the impact of the various factorss such as technique, magnitude of voltage usually can change along with the variation of one or several factors, wherein two important impacts that factor is exactly supply voltage and temperature.Simultaneously, along with the CMOS process is more and more less, the impact of the various factorss such as temperature is also increasing.Therefore, for the circuit that needs the high-accuracy voltage value, design not the constant voltage source circuit that the variation with supply voltage and temperature changes and just seem most important.
If traditional constant voltage source main circuit utilizes the voltage summation of the positive temperature coefficient (PTC) that the difference of the base stage of double pole triode of the voltage with negative temperature coefficient that produces between the base stage of double pole triode and the emitter and two different sizes and emitter voltage produces, by certain coefficients match, can obtain having the voltage of zero-temperature coefficient.This constant voltage by some mirror images and and have a coupling of uniform temperature coefficient, can produce constant voltage and output at fixing resistance.
In the constant voltage source circuit of high precision commonly used, all need to use the base stage of double pole triode and the voltage between the emitter.We know, the voltage between base stage and the emitter is generally about 0.7V. therefore, this has just limited the big or small minimum 1V that also is greater than of supply voltage.Along with the CMOS process is more and more less, the supply voltage that provides is more and more lower.Simultaneously, for the requirement to the power consumption performance, also need to reduce as much as possible supply voltage.Therefore, supply voltage approaches or when being lower than the base stage of double pole triode and the voltage between the emitter, traditional high-precision constant flow source circuit has just lost effect fully when running into.
Summary of the invention
Goal of the invention: for the problem and shortage of above-mentioned prior art existence, the purpose of this invention is to provide a kind of low supply voltage CMOS constant voltage source circuit, all formed by metal-oxide-semiconductor, be operated under the supply voltage environment of 0.6V, function with low-power consumption, the while has reduced the area of chip greatly.
Technical scheme: for achieving the above object, the technical solution used in the present invention is a kind of low supply voltage CMOS constant voltage source circuit, comprise first order start-up circuit, the first order and independent of power voltage but the current generating circuit of temperature influence, second level start-up circuit, the second level and independent of power voltage but the current generating circuit of temperature influence, branch current subtraction circuit, described branch current subtraction circuit are used for the first order and independent of power voltage but the electric current of temperature influence and the second level and independent of power voltage but the current subtraction of temperature influence; Wherein:
First order start-up circuit comprises a P type MOS transistor, the 2nd P type MOS transistor, the first N-type MOS transistor;
The first order and independent of power voltage but the current generating circuit of temperature influence comprises the 3rd P type MOS transistor, the 4th P type MOS transistor, the second N-type MOS transistor, the 3rd N-type MOS transistor, the first resistance, the 7th N-type MOS transistor;
Second level start-up circuit comprises the 5th P type MOS transistor, the 6th P type MOS transistor, the 4th N-type MOS transistor; The second level and independent of power voltage but the current generating circuit of temperature influence comprises the 7th P type MOS transistor, the 8th P type MOS transistor, the 9th P type MOS transistor, the second resistance, the 5th N-type MOS transistor, the 6th N-type MOS transistor;
The branch current subtraction circuit comprises the tenth P type MOS transistor, the 11 P type MOS transistor, the 12 P type MOS transistor, the 13 P type MOS transistor, the 8th N-type MOS transistor, the 9th N-type MOS transistor, the 3rd resistance, the 4th resistance;
Wherein:
The source electrode of the one P type MOS transistor connects power supply, the grid of the one P type MOS transistor links to each other with the source electrode of the 2nd P type MOS transistor, and the drain electrode of a P type MOS transistor links to each other with the drain electrode of the first N-type MOS transistor; The grid of the first N-type MOS transistor and the drain electrode of self link to each other, and link to each other with the grid of the 2nd P type MOS transistor; The substrate of the 2nd P type MOS transistor and grid separate, and connect power supply; The grounded drain of the source electrode of the first N-type MOS transistor and the 2nd P type MOS transistor; The source electrode of the source electrode of the 3rd P type MOS transistor and the 4th P type MOS transistor connects power supply, and the grid of the grid of the 3rd P type MOS transistor and the 4th P type MOS transistor links to each other and links to each other with the drain electrode of the 3rd P type MOS transistor; Drain electrode links to each other and links to each other with the grid of a P type MOS transistor with the second N-type MOS transistor in the drain electrode of the 3rd P type MOS transistor; The drain electrode of the 4th P type MOS transistor links to each other with the drain electrode of the 3rd N-type MOS transistor; The drain electrode of the 3rd N-type MOS transistor and the grid of itself link to each other; The substrate of the second N-type MOS transistor and source electrode separate and ground connection; One section of the source electrode of the second N-type MOS transistor and the first resistance links to each other; Another section of the first resistance links to each other and the source ground of the 3rd N-type MOS transistor; The source electrode of the 5th P type MOS transistor connects power supply, and grid links to each other with the source electrode of the 6th P type MOS transistor, and drain electrode links to each other with the drain electrode of the 4th P type MOS transistor; The grid of the 4th N-type MOS transistor and the drain electrode of itself link to each other, and link to each other with the grid of the 6th P type MOS transistor; The substrate of the 6th P type MOS transistor and source electrode are separately and connect power supply; The drain electrode of the 6th P type MOS transistor and the source electrode of the 4th N-type MOS transistor be ground connection together; The source electrode of the 7th P type MOS transistor links to each other with an end of the second resistance, and the other end of the second resistance links to each other with power supply; The grid of the grid of the 7th P type MOS transistor and the 8th P type MOS transistor and the grid of the 9th P type MOS transistor link to each other and link to each other with the drain electrode of the 8th P type MOS transistor and the grid of the 5th P type MOS transistor; The source electrode of the 9th P type MOS transistor, drain electrode, the source electrode of substrate and the 8th P type MOS transistor all links to each other with power supply; The grid of the 5th N-type MOS transistor and the drain electrode of itself link to each other, and link to each other with the grid of the 6th N-type MOS transistor; The source electrode of the source electrode of the 5th N-type MOS transistor and the 6th N-type MOS transistor links to each other and ground connection; The grid of the tenth P type MOS transistor links to each other with the drain electrode of the 8th P type MOS transistor, and the source electrode of the tenth P type MOS transistor connects power supply, and drain electrode connects the drain electrode of the 8th N-type MOS transistor; The grid of the grid of the 8th N-type MOS transistor and the 7th N-type MOS transistor and the drain electrode of the 3rd N-type MOS transistor link to each other; The source electrode of the source electrode of the 8th N-type MOS transistor and the 7th N-type MOS transistor, substrate, drain electrode all link to each other with ground; Grid, the drain electrode of the 11 P type MOS transistor, the grid of the 12 P type metal oxide crystal and the grid of the 13 P type MOS transistor link to each other; The source electrode of the 11 P type MOS transistor, the source electrode of the source electrode of the 12 P type MOS transistor, drain electrode, substrate and the 13 P type MOS transistor links to each other with power supply; The drain electrode of the 13 P type MOS transistor links to each other with the 3rd resistance one end, and an end of the other end of the 3rd resistance and the 4th resistance links to each other, the other end ground connection of the 4th resistance; The grid of the 9th N-type MOS transistor is connected to the centre of the 3rd resistance and the 4th resistance, the source electrode of the 9th N-type MOS transistor, substrate and all ground connection that drains.
Constant voltage source circuit of the present invention does not contain bipolar device, has produced the constant voltage that has very high supply-voltage rejection ratio and have low-temperature coefficient under the environment of low supply voltage.
Beneficial effect: compared with prior art, the present invention has following beneficial effect:
1. be operated under the low supply voltage, such as the monolithic solar panel.Constant voltage source circuit of the present invention can be used for the place that the reference circuit of multiple cmos circuit and biasing circuit etc. need constant voltage source.Constant voltage source circuit of the present invention can be operated under the low supply voltage of 0.6V.Because whole circuit all is comprised of the MOS device, has greatly reduced the area of chip.
2. the electric current utilization ratio is high, and is low in energy consumption.Along with the development of CMOS technique, supply voltage is more and more less, and this has proposed challenge to the constant-current source circuit that contains the double pole triode device.Supply voltage do not contain bipolar device among the present invention, so can be lower than the forward voltage of double pole triode.Therefore the power consumption of whole circuit is very low.And in order to produce the higher constant voltage source of precision, the present invention at first designs and is operated under the 0.6V supply voltage and electric current temperature and independent from voltage.Because the temperature coefficient that resistance has is opposite with the temperature coefficient that the electric current that produces has, and then can obtain by the combination of electric current and resistance the lower constant voltage of temperature coefficient.
Description of drawings
Fig. 1 is circuit diagram of the present invention;
Fig. 2 is the oscillogram that voltage of the present invention changes with temperature coefficient.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment only is used for explanation the present invention and is not used in and limits the scope of the invention, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of the various equivalent form of values of the present invention.
As shown in Figure 1, a kind of low supply voltage CMOS constant voltage source circuit of the present invention, comprise first order start-up circuit, the first order and independent of power voltage but the current generating circuit of temperature influence, second level start-up circuit, the second level and independent of power voltage but current generating circuit and the branch current subtraction circuit of temperature influence, described branch current subtraction circuit are used for the first order and independent of power voltage but the electric current of temperature influence and the second level and independent of power voltage but the current subtraction of temperature influence; Wherein:
First order start-up circuit comprises a P type MOS transistor P1, the 2nd P type MOS transistor P2, the first N-type MOS transistor N1;
The first order and independent of power voltage but the current generating circuit of temperature influence comprises the 3rd P type MOS transistor P3, the 4th P type MOS transistor P4, the second N-type MOS transistor N2, the 3rd N-type MOS transistor N3, the first resistance R 1, the seven N-type MOS transistor N7;
Second level start-up circuit comprises the 5th P type MOS transistor P5, the 6th P type MOS transistor P6, the 4th N-type MOS transistor N4;
The second level and independent of power voltage but the current generating circuit of temperature influence comprises the 7th P type MOS transistor P7, the 8th P type MOS transistor P8, the 9th P type MOS transistor P9, the second resistance R 2, the 5th N-type MOS transistor N5, the 6th N-type MOS transistor N6;
The branch current subtraction circuit comprises the tenth P type MOS transistor P10, the 11 P type MOS transistor P11, the 12 P type MOS transistor P12, the 13 P type MOS transistor P13, the 8th N-type MOS transistor N8, the 9th N-type MOS transistor N9, the 3rd resistance R 3, the four resistance R 4;
Wherein:
The source electrode of the one P type MOS transistor P1 connects power supply, the grid of the one P type MOS transistor P1 links to each other with the source electrode of the 2nd P type MOS transistor P2, and the drain electrode of a P type MOS transistor P1 links to each other with the drain electrode of the first N-type MOS transistor N1; The grid of the first N-type MOS transistor N1 and the drain electrode of self link to each other, and link to each other with the grid of the 2nd P type MOS transistor P2; The substrate of the 2nd P type MOS transistor P2 and grid separate, and connect power supply; The grounded drain of the source electrode of the first N-type MOS transistor N1 and the 2nd P type MOS transistor P2; The source electrode of the source electrode of the 3rd P type MOS transistor P3 and the 4th P type MOS transistor P4 connects power supply, and the grid of the grid of the 3rd P type MOS transistor P3 and the 4th P type MOS transistor P4 links to each other and links to each other with the drain electrode of the 3rd P type MOS transistor P3; Drain electrode links to each other and links to each other with the grid of a P type MOS transistor P1 with the second N-type MOS transistor N2 in the drain electrode of the 3rd P type MOS transistor P3; The drain electrode of the 4th P type MOS transistor P4 links to each other with the drain electrode of the 3rd N-type MOS transistor N3; The 3rd N-type MOS transistor N3 drain electrode and the grid of itself link to each other; The substrate of the second N-type MOS transistor N2 and source electrode separate and ground connection; The source electrode of the second N-type MOS transistor N2 links to each other with an end of the first resistance R 1; The source electrode of the other end of the first resistance R 1 and the 3rd N-type MOS transistor N3 links to each other and ground connection; The source electrode of the 5th P type MOS transistor P5 connects power supply, and grid links to each other with the source electrode of the 6th P type MOS transistor P6, and drain electrode links to each other with the drain electrode of the 4th P type MOS transistor P4; The grid of the 4th N-type MOS transistor N4 and the drain electrode of itself link to each other, and link to each other with the grid of the 6th P type MOS transistor P6; The substrate of the 6th P type MOS transistor P6 and source electrode are separately and connect power supply; The drain electrode of the 6th P type MOS transistor P6 and the source electrode of the 4th N-type MOS transistor N4 be ground connection together; The source electrode of the 7th P type MOS transistor P7 links to each other with an end of the second resistance R 2, and the other end of the second resistance R 2 links to each other with power supply; The grid of the grid of the 7th P type MOS transistor P7 and the 8th P type MOS transistor P8 and the grid of the 9th P type MOS transistor P9 link to each other and link to each other with the drain electrode of the 8th P type MOS transistor P8 and the grid of the 5th P type MOS transistor P5; The source electrode of the 9th P type MOS transistor P9, drain electrode, the source electrode of substrate and the 8th P type MOS transistor P8 all links to each other with power supply; The grid of the 5th N-type MOS transistor N5 and the drain electrode of itself link to each other, and link to each other with the grid of the 6th N-type MOS transistor N6; The source electrode of the source electrode of the 5th N-type MOS transistor N5 and the 6th N-type MOS transistor N6 links to each other and ground connection; The grid of the tenth P type MOS transistor P10 links to each other with the drain electrode of the 8th P type MOS transistor P8, and the source electrode of the tenth P type MOS transistor P10 connects power supply, and drain electrode connects the drain electrode of the 8th N-type MOS transistor N8; The grid of the grid of the 8th N-type MOS transistor N8 and the 7th N-type MOS transistor N7 and the drain electrode of the 3rd N-type MOS transistor N3 link to each other; Source electrode, substrate, the drain electrode of the source electrode of the 8th N-type MOS transistor N8 and the 7th N-type MOS transistor N7 all link to each other with ground; Grid, the drain electrode of the 11 P type MOS transistor P11, the grid of the 12 P type MOS transistor P12 and the grid of the 13 P type MOS transistor P13 link to each other; The source electrode of the 11 P type MOS transistor P11, the source electrode of the source electrode of the 12 P type MOS transistor P12, drain electrode, substrate and the 13 P type MOS transistor P13 links to each other with power supply; The drain electrode of the 13 P type MOS transistor P13 links to each other with the 3rd resistance R 3 one ends, and the other end of the 3rd resistance R 3 links to each other with an end of the 4th resistance R 4, the other end ground connection of the 4th resistance R 4; The grid of the 9th N-type MOS transistor N9 is connected to the centre of the 3rd resistance R 3 and the 4th resistance R 4, source electrode, the substrate of the 9th N-type MOS transistor N9 and all ground connection that drains.
The constant voltage source circuit of above-mentioned high precision all is comprised of cmos device.Owing to not containing the double pole triode device, so supply voltage can be lower than the forward voltage of double pole triode, therefore, whole constant-current source circuit can be operated under the low supply voltage of 0.6V, has very low power consumption.And, because the double pole triode device size is very large, so the present invention has reduced the area of chip greatly.Main thought of the present invention is to utilize the first order and independent of power voltage but the current generating circuit of temperature influence and the second level and independent of power voltage but the two-way electric current with synthermal coefficient that the current generating circuit of temperature influence produces, can obtain having the electric current of low-temperature coefficient by the branch current subtraction circuit.Simultaneously, the temperature coefficient of the temperature coefficient that resistance has in the technique and the electric current that produces is opposite, then can utilize the combination of electric current and resistance to obtain the lower constant voltage of temperature coefficient.
First order start-up circuit is by a P type MOS transistor, and the 2nd P type MOS transistor and the first N-type MOS transistor form.When the first order and independent of power voltage but the current generating circuit of temperature influence when being in not starting state, the drain voltage of the 3rd P type MOS transistor P3 is very high, because the drain electrode of the 3rd P type MOS transistor P3 and the source electrode of the 2nd P type MOS transistor P2 link to each other, so the source electrode of the 2nd P type MOS transistor P2 is in noble potential equally.At this moment, the conducting of the 2nd P type MOS transistor P2, a large amount of electric currents flow through the 2nd P type MOS transistor P2 after the conducting, can so that the drain voltage of the 3rd P type MOS transistor P3 reduces, play the function of start-up circuit.In the situation that process is very little, the threshold voltage of metal-oxide-semiconductor is very large.In order better to play the purpose that starts subsequent conditioning circuit, in the circuit substrate of the 2nd P type MOS transistor P2 is connect power supply.The substrate bias effect that utilizes metal-oxide-semiconductor itself to exist reduces threshold voltage.Poor for same drain electrode and source voltage like this, the 2nd P type MOS transistor P2 can pass through larger electric current, and then reduces to a greater extent the drain voltage of the 3rd P type MOS transistor P3, starts better effects if.When circuit is in conducting state, should be so that the 2nd P type MOS transistor P2 be in cut-off state, avoid it to the back first order and independent of power voltage but the impact of the current generating circuit of temperature influence.Circuit when normal operation because the drain voltage of the 3rd P type MOS transistor P3 is higher, so that the 2nd P type MOS transistor P2 be in cut-off state, then should raise the grid voltage of the 2nd P type MOS transistor P2.The grid of the 2nd P type MOS transistor P2 links to each other with the drain electrode of the first N-type MOS transistor N1, so can raise accordingly by the drain voltage of raising the first N-type MOS transistor N1 the grid voltage of the 2nd P type MOS transistor P2.Therefore, in first order start-up circuit, the breadth length ratio of a P type MOS transistor P1 arrange larger, and the first N-type MOS transistor is arranged to down breadth length ratio, namely the wide size of the first N-type MOS transistor is less than channel length.Like this, at circuit working under normal circumstances the time, can be so that the 2nd P type MOS transistor P2 be in cut-off state.Simultaneously, flow through the electric current of first order start-up circuit in the time of also can greatly reducing the circuit normal operation for the setting of a P type MOS transistor P1 and the first N-type MOS transistor N1, thereby further reduce the power consumption of whole circuit.The principle of the second level start-up circuit of back is the same with the principle of first order start-up circuit.
In order to obtain the current value with independent of power voltage, we adopt the first order and independent of power voltage but the current generating circuit of temperature influence.In this circuit, if remove the first resistance R 1, the electric current that then flows through the 3rd P type MOS transistor P3 is that the electric current by mirror image the 4th P type MOS transistor P4 obtains; The electric current that flows through the 3rd N-type MOS transistor N3 is that the electric current by mirror image the second N-type MOS transistor N2 obtains.Therefore as can be known, flow through electric current and the independent of power voltage of whole branch road.But the electric current in the circuit can be arbitrary value at this moment.As long as circuit has a primary current, electric current just can be in two branch roads flows by mirror image back and forth so.In order to obtain the current value of needed concrete size.We add the first resistance R 1 in the source of the first N-type MOS transistor N1.By the setting to the size of the breadth length ratio of each MOS device and the first resistance R 1, the current value of the concrete size that we can obtain wanting.The second level is with independent of power voltage but the current generating circuit employing of temperature influence and the first order and independent of power voltage but the identical principle of the current generating circuit of temperature influence.In order to obtain more stable waveform, utilize the 7th N-type MOS transistor N7 and the 4th P type MOS transistor P4 to come respectively as the first order and independent of power voltage but the filtering device of the current generating circuit of the current generating circuit of temperature influence and the second level and independent of power voltage but temperature influence, come the filtering first order and independent of power voltage but the current generating circuit of temperature influence and the second level and independent of power voltage but contained noise current in the electric current that the current generating circuit of temperature influence produces.
Utilize the first order and independent of power voltage but the current generating circuit of temperature influence, we can obtain the current value with the concrete size of independent of power voltage, but this current value remains the function of flow-route and temperature.For the high-precision constant voltage that obtains also haveing nothing to do with flow-route and temperature, the branch current that this invention has adopted two-way and independent of power voltage still to have same flow-route and temperature coefficient subtracts each other to offset flow-route and temperature to the impact of constant voltage values.In the circuit diagram of this invention, by the 8th N-type MOS transistor N8 come the mirror image first order and independent of power voltage but produce in the current generating circuit of temperature influence with independent of power voltage but be the branch current of flow-route and temperature function; Utilize the tenth P type MOS transistor P10 to come the mirror image second level and independent of power voltage but produce in the current generating circuit of temperature influence with independent of power voltage but be the branch current of flow-route and temperature function; By the tenth P type MOS transistor P10, the 11 P type MOS transistor P11, the 12 P type MOS transistor P12, the 13 P type MOS transistor P13, the 8th N-type MOS transistor N8, the 9th N-type MOS transistor N9, the 3rd resistance R 3, in the branch current subtraction circuit that the 4th resistance R 4 forms, owing to flowing through the electric current of the 8th N-type MOS transistor N8 and the tenth P type MOS transistor P10 temperature and technique had identical Relationship of Coefficients, so coupling by certain coefficient, utilize subtracting each other of two branch currents both can obtain and independent of power voltage, again with the irrelevant constant voltage of high precision of temperature and technique.In circuit diagram, can see, the electric current that flows through the 11 P type MOS transistor P11 be obtain after two branch currents subtract each other by coefficients match with the equal irrelevant electric current of supply voltage and temperature.
The electric current that flows through the 13 P type MOS transistor P13 is that the electric current of mirror image the 11 P type MOS transistor P11 obtains.The coefficient of the 4th resistance R 4 and temperature and technique is opposite with the coefficient of electric current and temperature and technique, so the coupling of magnitude numerical value that can be by resistance and electric current can obtain the higher magnitude of voltage of precision by the Vout point between the 3rd resistance and the 4th resistance.The 12 P type MOS transistor P12 and the 9th N-type MOS transistor N9 play the effect of filtering equally.
Below by simulation comparison the constant voltage source of high precision that the present invention produces and the impact of temperature coefficient are described.
Adopt
Simulation software carries out the constant voltage source of high precision to the scanning analysis of temperature coefficient.Analysis result as shown in Figure 2.As can be seen from Figure 2, output reference voltage from-20 the degree in 80 degree scopes, embodied the single order temperature compensation characteristic, in whole range of temperature, the amplitude of variation of output voltage is controlled in the 1.5mV, can satisfy most application demand.
Claims (1)
1. low supply voltage CMOS constant voltage source circuit, comprise first order start-up circuit, the first order and independent of power voltage but the current generating circuit of temperature influence, second level start-up circuit, the second level and independent of power voltage but current generating circuit and the branch current subtraction circuit of temperature influence, described branch current subtraction circuit are used for the first order and independent of power voltage but the electric current of temperature influence and the second level and independent of power voltage but the current subtraction of temperature influence; Wherein:
First order start-up circuit comprises a P type MOS transistor (P1), the 2nd P type MOS transistor (P2), the first N-type MOS transistor (N1);
The first order and independent of power voltage but the current generating circuit of temperature influence comprises the 3rd P type MOS transistor (P3), the 4th P type MOS transistor (P4), the second N-type MOS transistor (N2), the 3rd N-type MOS transistor (N3), the first resistance (R1), the 7th N-type MOS transistor (N7);
Second level start-up circuit comprises the 5th P type MOS transistor (P5), the 6th P type MOS transistor (P6), the 4th N-type MOS transistor (N4);
The second level and independent of power voltage but the current generating circuit of temperature influence comprises the 7th P type MOS transistor (P7), the 8th P type MOS transistor (P8), the 9th P type MOS transistor (P9), the second resistance (R2), the 5th N-type MOS transistor (N5), the 6th N-type MOS transistor (N6);
The branch current subtraction circuit comprises the tenth P type MOS transistor (P10), the 11 P type MOS transistor (P11), the 12 P type MOS transistor (P12), the 13 P type MOS transistor (P13), the 8th N-type MOS transistor (N8), the 9th N-type MOS transistor (N9), the 3rd resistance (R3), the 4th resistance (R4);
Wherein:
The source electrode of the one P type MOS transistor (P1) connects power supply, the grid of the one P type MOS transistor (P1) links to each other with the source electrode of the 2nd P type MOS transistor (P2), and the drain electrode of a P type MOS transistor (P1) links to each other with the drain electrode of the first N-type MOS transistor (N1); The grid of the first N-type MOS transistor (N1) and the drain electrode of self link to each other, and link to each other with the grid of the 2nd P type MOS transistor (P2); The substrate of the 2nd P type MOS transistor (P2) and grid separate, and connect power supply; The grounded drain of the source electrode of the first N-type MOS transistor (N1) and the 2nd P type MOS transistor (P2); The source electrode of the source electrode of the 3rd P type MOS transistor (P3) and the 4th P type MOS transistor (P4) connects power supply, and the grid of the grid of the 3rd P type MOS transistor (P3) and the 4th P type MOS transistor (P4) links to each other and links to each other with the drain electrode of the 3rd P type MOS transistor (P3); Drain electrode links to each other and links to each other with the grid of a P type MOS transistor (P1) with the second N-type MOS transistor (N2) in the drain electrode of the 3rd P type MOS transistor (P3); The drain electrode of the 4th P type MOS transistor (P4) links to each other with the drain electrode of the 3rd N-type MOS transistor (N3); The drain electrode of the 3rd N-type MOS transistor (N3) and the grid of itself link to each other; The substrate of the second N-type MOS transistor (N2) and source electrode separate and ground connection; The source electrode of the second N-type MOS transistor (N2) links to each other with an end of the first resistance (R1); The source electrode of the other end of the first resistance (R1) and the 3rd N-type MOS transistor (N3) links to each other and ground connection; The source electrode of the 5th P type MOS transistor (P5) connects power supply, and grid links to each other with the source electrode of the 6th P type MOS transistor (P6), and drain electrode links to each other with the drain electrode of the 4th P type MOS transistor (P4); The grid of the 4th N-type MOS transistor (N4) and the drain electrode of itself link to each other, and link to each other with the grid of the 6th P type MOS transistor (P6); The substrate of the 6th P type MOS transistor (P6) and source electrode are separately and connect power supply; The source electrode of the drain electrode of the 6th P type MOS transistor (P6) and the 4th N-type MOS transistor (N4) is ground connection together; The source electrode of the 7th P type MOS transistor (P7) links to each other with an end of the second resistance (R2), and the other end of the second resistance (R2) links to each other with power supply; The grid of the grid of the 7th P type MOS transistor (P7) and the 8th P type MOS transistor (P8) and the grid of the 9th P type MOS transistor (P9) link to each other and link to each other with the drain electrode of the 8th P type MOS transistor (P8) and the grid of the 5th P type MOS transistor (P5); The source electrode of the 9th P type MOS transistor (P9), drain electrode, the source electrode of substrate and the 8th P type MOS transistor (P8) all links to each other with power supply; The grid of the 5th N-type MOS transistor (N5) and the drain electrode of itself link to each other, and link to each other with the grid of the 6th N-type MOS transistor (N6); The source electrode of the source electrode of the 5th N-type MOS transistor (N5) and the 6th N-type MOS transistor (N6) links to each other and ground connection; The grid of the tenth P type MOS transistor (P10) links to each other with the drain electrode of the 8th P type MOS transistor (P8), the source electrode of the tenth P type MOS transistor (P10) connects power supply, and drain electrode connects the drain electrode of the 8th N-type MOS transistor (N8); The grid of the grid of the 8th N-type MOS transistor (N8) and the 7th N-type MOS transistor (N7) and the drain electrode of the 3rd N-type MOS transistor (N3) link to each other; Source electrode, substrate, the drain electrode of the source electrode of the 8th N-type MOS transistor (N8) and the 7th N-type MOS transistor (N7) all link to each other with ground; Grid, the drain electrode of the 11 P type MOS transistor (P11), the grid of the 12 P type MOS transistor (P12) and the grid of the 13 P type MOS transistor (P13) link to each other; The source electrode of the 11 P type MOS transistor (P11), the source electrode of the source electrode of the 12 P type MOS transistor (P12), drain electrode, substrate and the 13 P type MOS transistor (P13) links to each other with power supply; The drain electrode of the 13 P type MOS transistor (P13) links to each other with the 3rd resistance (R3) end, and the other end of the 3rd resistance (R3) links to each other with an end of the 4th resistance (R4), the other end ground connection of the 4th resistance (R4); The grid of the 9th N-type MOS transistor (N9) is connected to the centre of the 3rd resistance (R3) and the 4th resistance (R4), source electrode, the substrate of the 9th N-type MOS transistor (N9) and all ground connection that drains.
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