CN103066984A - Dynamic pulse integral circuit not influenced by frequency - Google Patents

Abstract

The invention discloses a dynamic pulse integral circuit not influenced by frequency. The dynamic pulse integral circuit not influenced by the frequency mainly solves the problem that an existing dynamic pulse integral circuit is influenced by the frequency. The dynamic pulse integral circuit not influenced by the frequency comprises a frequency selection circuit (1), a band-pass filter (2), a comparator (3), an integrator (4) and a schmitt trigger (5), wherein the frequency selection circuit (1) outputs a frequency selection signal VFS which is connected with a first input end of the band-pass filter (2) and a first input end of the integrator (4) , a second input end of the band-pass filter (2) is connected with an input end VIN of a chip where the band-pass filter (2) is located, the band-pass filter (2) outputs a filtering signal VBPF, a comparison signal VCMP is output after the filtering signal VBPF passes the comparator (3), an integrated signal VINT is output to the schmitt trigger (5) after the comparison signal VCMP is integrated by the integrator (4), and after reforming of the schmitt trigger (5), an output signal VOUT of the dynamic pulse integral circuit is output. The dynamic pulse integral circuit not influenced by the frequency enables the dynamic pulse integral circuit to integrate input signals with various frequencies accurately.

Description

Be not subjected to the dynamic pulse integrating circuit of frequency influence

Technical field

The invention belongs to the electronic circuit technology field, relate to analog integrated circuit, particularly a kind of dynamic pulse integrating circuit that is not subjected to frequency influence.

Background technology

The infrared transmission circuit has that cost is low, Period of popularization early, the transmission speed advantages of higher, extensive use in household electrical appliance, vehicle-borne audio-visual navigation system.Infrared remote receiver is the important part of infrared transmission circuit, in infrared remote receiver, usually adopts the integrating circuit that is comprised of integrated operational amplifier to come the filtering carrier frequency, and the performance of integrating circuit directly affects the performance of infrared remote receiver.Therefore, the research of integrating circuit is more and more concerned in the infrared remote receiver.

Figure 1 shows that the circuit theory diagrams of existing integrating circuit, comprise error amplifier EA, resistance R 1, resistance R 2, capacitor C 1; Input pulse signal Va links to each other with an end of resistance R 1, and the other end of resistance R 1 links to each other with the inverting input of error amplifier EA; One end of capacitor C 1 links to each other with the inverting input of error amplifier EA, and the other end of capacitor C 1 links to each other output signal Vo with the output of error amplifier EA; The in-phase input end of error amplifier EA links to each other with an end of resistance R 2, the other end ground connection of resistance R 2; When pulse signal Va was high level, to capacitor C 1 charging, output signal Vo step-down was until saturated by resistance R 1; When pulse signal Va is low level, there is not current flowing resistance R1, the quantity of electric charge on the capacitor C 1 remains unchanged, and the size of output signal Vo also remains unchanged.

Above-mentioned integrating circuit is owing to the time of its integration rising edge is fixed, therefore the output meeting of integrating circuit changes along with the variation of integrated signal frequency, so that integrating circuit can not carry out integration to the integrated signal that comprises multi-frequency exactly, limited the development of infrared receiving circuit.

Summary of the invention

The object of the invention is to the defective for above-mentioned prior art, proposed a kind of dynamic pulse integrating circuit that is not subjected to frequency influence, make integrating circuit carry out integration to the integrated signal that comprises multi-frequency exactly.

For achieving the above object, the present invention includes: frequency selective network 1, band pass filter 2, comparator 3, integrator 4 and Schmidt trigger 5;

Frequency selective network 1 is provided with six input a, b, c, d, e, f and an output g, and these six inputs link to each other with input signal T1, T2, T3, T4, T5, the T6 of its place chip respectively; Output g output frequency is selected signal VFS, and this frequency selects signal VFS to be input to respectively the first input end of the first input end sum-product intergrator 4 of band pass filter 2;

Band pass filter 2, its second input links to each other with the input signal VIN of its place chip, this band pass filter 2 output filtering signal VBPF are by comparator 3, output comparison signal VCMP, this comparison signal VCMP, through integrator 4 integrations, output integrated signal VINT is to Schmidt trigger 5, after Schmidt trigger 5 shapings, the output signal VOUT of output dynamic pulse integrating circuit.

As preferably, said frequencies is selected circuit 1, comprises six NPN pipes, six voltage stabilizing didoes and seven resistance, wherein:

The negative pole of described the first voltage stabilizing didoe D1, emitter, the collector electrode of NPN pipe Q1 all link to each other with the input signal T1 of its place chip, and the first resistance R 1 is connected across between the emitter and base stage of NPN pipe Q1;

The collector electrode of the emitter of the base stage of described NPN pipe Q1, the 2nd NPN pipe Q2, the 2nd NPN pipe Q2 and the negative pole of the second voltage stabilizing didoe D2 link to each other with the input signal T2 of its place chip, and the second resistance R 2 is connected across between the emitter and base stage of the 2nd NPN pipe Q2;

The collector electrode of the emitter of the base stage of described the 2nd NPN pipe Q2, the 3rd NPN pipe Q3, the 3rd NPN pipe Q3 and the negative pole of the 3rd voltage stabilizing didoe D3 link to each other with the input signal T3 of its place chip, and the 3rd resistance R 3 is connected across between the emitter and base stage of the 3rd NPN pipe Q3;

The collector electrode of the emitter of the base stage of described the 3rd NPN pipe Q3, the 4th NPN pipe Q4, the 4th NPN pipe Q4 and the negative pole of the 4th voltage stabilizing didoe D4 link to each other with the input signal T4 of its place chip, and the 4th resistance R 4 is connected across between the emitter and base stage of the 4th NPN pipe Q4;

The collector electrode of the emitter of the base stage of described the 4th NPN pipe Q4, the 5th NPN pipe Q5, the 5th NPN pipe Q5 and the negative pole of the 5th voltage stabilizing didoe D5 link to each other with the input signal T5 of its place chip, and the 5th resistance R 5 is connected across between the emitter and base stage of the 5th NPN pipe Q5;

The base stage of described the 5th NPN pipe Q5 and the negative pole of the 6th voltage stabilizing didoe D6 link to each other with the input signal T6 of its place chip, and base stage and the 6th NPN that the 6th resistance R 6 is connected across the 5th NPN pipe Q5 manage between the collector electrode of Q6;

The base stage of described the 6th NPN pipe Q6 links to each other with the collector electrode of the 6th NPN pipe Q6, output output frequency as frequency selective network (1) is selected signal VFS, the emitter of the 6th NPN pipe Q6 links to each other with an end of the 7th resistance R 7, the plus earth of anodal and the 6th voltage stabilizing didoe D6 of the positive pole of the positive pole of the other end of the 7th resistance R 7, the first voltage stabilizing didoe D1, the positive pole of the second voltage stabilizing didoe D2, the 3rd voltage stabilizing didoe D3, the positive pole of the 4th voltage stabilizing didoe D4, the 5th voltage stabilizing didoe D5.

As preferably, above-mentioned band pass filter 2 comprises the first variable transconductance operational amplifier OTA1, the second variable transconductance operational amplifier OTA2, the first capacitor C 1, the second capacitor C 2, the 8th resistance R 8, the 9th resistance R 9 and current gain network K;

Described the first capacitor C 1 is connected across between the normal phase input end of the input signal VIN of its place chip and the first variable transconductance operational amplifier OTA1; The second capacitor C 2 is connected across between the input and ground of current gain network K;

The inverting input of described the first variable transconductance operational amplifier OTA1 links to each other with an end of the 8th resistance R 8 and an end of the 9th resistance R 9 respectively, the normal phase input end of the first variable transconductance operational amplifier OTA1 links to each other with the output of the second variable transconductance operational amplifier OTA2, and the output of the first variable transconductance operational amplifier OTA1 links to each other with the input of current gain network K;

The other end of described the 8th resistance R 8 links to each other with the in-phase input end of the second variable transconductance operational amplifier OTA2, and the other end of the 9th resistance R 9 links to each other with the inverting input of the second variable transconductance operational amplifier OTA2;

The 3rd input of the 3rd input of described the second variable transconductance operational amplifier OTA2 and the first variable transconductance operational amplifier OTA1 selects signal VFS to link to each other with the frequency that frequency selective network 1 is inputted; The output of current gain network K links to each other with the inverting input of the second variable transconductance operational amplifier OTA2, as the output output filtering signal VBPF of band pass filter 2.

As preferably, above-mentioned integrator 4 comprises three NMOS pipe, five PNP pipes, five NPN pipes, two capacitor C, a resistance R;

The emitter of described the 7th PNP pipe Q7, the emitter of the 8th PNP pipe Q8, the emitter of the 9th PNP pipe Q9, the emitter of the tenth PNP pipe Q10 all links to each other with supply voltage VCC with the emitter of the 11 PNP pipe Q11, the base stage of the 7th PNP pipe Q7, the base stage of the 8th PNP pipe Q8, the collector electrode of the base stage of the 9th PNP pipe Q9 and the 7th PNP pipe Q7 all links to each other with the drain electrode of NMOS pipe MN1, the base stage of the 11 PNP pipe Q11, the collector electrode of the base stage of the tenth PNP pipe Q10 and the tenth PNP pipe Q10 all links to each other with the drain electrode of the 2nd NMOS pipe MN2, the collector electrode of the 8th PNP pipe Q8 links to each other with the collector electrode of the 16 NPN pipe Q16, as the output output integrated signal VINT of integrator 4, the collector electrode of the 9th PNP pipe Q9 links to each other with an end of the tenth resistance R 10;

The collector electrode of the collector electrode of described the 11 PNP pipe Q11 and the 14 NPN pipe Q14 all links to each other with the base stage of the 12 NPN pipe Q12; The grounded emitter of the 13 NPN pipe Q13, the base stage of the 13 NPN pipe Q13 links to each other with the signal VFS that frequency selective network 1 is inputted, the emitter of the emitter of the emitter of the 14 NPN pipe Q14, the 15 NPN pipe Q15 and the 16 NPN pipe Q16 all is connected to the ground, and the base stage of the base stage of the 14 NPN pipe Q14, the 15 NPN pipe Q15 all links to each other with the emitter of the 12 NPN pipe Q12 with the base stage of the 16 NPN pipe Q16; The collector electrode of the 12 NPN pipe Q12 all links to each other with supply voltage VCC with the collector electrode of the 15 NPN pipe Q15;

The grid of described NMOS pipe MN1 links to each other with the reference voltage V REF3 of its place chip, and the source electrode of NMOS pipe MN1 all links to each other with the collector electrode of the 13 NPN pipe with the source electrode of the 2nd NMOS pipe MN2; The grid of the 2nd NMOS pipe MN2 links to each other with the collector electrode of the 9th PNP pipe Q9; The drain electrode of the 3rd NMOS pipe MN3 links to each other with the other end of the tenth resistance R 10, the source ground of the 3rd NMOS pipe MN3, and the grid of the 3rd NMOS pipe MN3 links to each other with the signal VCMP that comparator 3 is inputted;

Between the collector electrode and ground of 3 cross-over connections of described the 3rd capacitor C and the 9th PNP pipe Q9, be used for delay pulse time of integration; Between the collector electrode and ground of 4 cross-over connections of the 4th capacitor C and the 8th PNP pipe Q8, for integrator 4 provides charge and discharge capacitance.

As preferably, the ratio of the 7th PNP pipe Q7, the 8th PNP pipe Q8, the 9th PNP pipe Q9, the tenth PNP pipe Q10 in the above-mentioned integrator 4 and the emitter area of the 11 PNP pipe Q11 is 2: 1: 1: 1: 1; The ratio of the 14 NPN pipe Q14, the 15 NPN pipe Q15 in the above-mentioned integrator 4 and the emitter area of the 16 PNP pipe Q16 is 3: 2: 2.

The present invention compared with prior art has the following advantages:

1, the present invention can regulate the band passband rate of bandwidth-limited circuit, so that the dynamic pulse integrating circuit can be processed the input signal of different frequency owing to added frequency selective network.

2, the present invention has been owing to added bandwidth-limited circuit, so that the charging and discharging currents of integrator is directly proportional with the centre frequency of band pass filter, so that the integrated pulse number of dynamic pulse integrating circuit is not subjected to the impact of frequency input signal.

Description of drawings

Fig. 1 is the topology diagram of existing integrating circuit;

Fig. 2 is topology diagram of the present invention;

Fig. 3 is the circuit theory diagrams that medium frequency of the present invention is selected circuit;

Fig. 4 is the topology diagram of band pass filter among the present invention;

Fig. 5 is the circuit theory diagrams of integrator circuit among the present invention.

Embodiment

The invention will be further described referring to accompanying drawing and embodiment.

With reference to Fig. 2, the present invention includes: frequency selective network 1, band pass filter 2, comparator 3, integrator 4 and Schmidt trigger 5; Wherein:

Frequency selective network 1, be provided with six input a, b, c, d, e, f and an output g, these six inputs link to each other with input signal T1, T2, T3, T4, T5, the T6 of its place chip respectively, output g output frequency is selected signal VFS, by between frequency selective network 1 any two adjacent inputs, adding Zener breakdown voltage, can regulating frequency select the frequency of circuit 1 output to select the frequency of signal VFS; This frequency selects signal VFS to be input to respectively the first input end of the first input end sum-product intergrator 4 of band pass filter 2, is used for the charging and discharging currents with passband rate sum-product intergrator 4 of accommodation zone bandpass filter 2; The second input of band pass filter 2 links to each other with the input signal VIN of its place chip, this band pass filter 2 output filtering signal VBPF are by comparator 3, output comparison signal VCMP, this comparison signal VCMP, through integrator 4 integrations, output integrated signal VINT, the time of integration of integrator 4, the centre frequency with filtering signal VBPF was directly proportional, integrated signal VINT is to Schmidt trigger 5, after Schmidt trigger 5 shapings, the output signal VOUT of output dynamic pulse integrating circuit, this output signal VOUT is not subjected to the impact of its place chip input signal VIN frequency.

With reference to Fig. 3, frequency selective network 1 of the present invention, including, but not limited to six NPN pipes, six voltage stabilizing didoes and seven resistance, wherein:

The negative pole of described the first voltage stabilizing didoe D1, emitter, the collector electrode of NPN pipe Q1 all link to each other with the input signal T1 of its place chip, and the first resistance R 1 is connected across between the emitter and base stage of NPN pipe Q1;

The collector electrode of the emitter of the base stage of described NPN pipe Q1, the 2nd NPN pipe Q2, the 2nd NPN pipe Q2 and the negative pole of the second voltage stabilizing didoe D2 link to each other with the input signal T2 of its place chip, and the second resistance R 2 is connected across between the emitter and base stage of the 2nd NPN pipe Q2;

The collector electrode of the emitter of the base stage of described the 2nd NPN pipe Q2, the 3rd NPN pipe Q3, the 3rd NPN pipe Q3 and the negative pole of the 3rd voltage stabilizing didoe D3 link to each other with the input signal T3 of its place chip, and the 3rd resistance R 3 is connected across between the emitter and base stage of the 3rd NPN pipe Q3;

The collector electrode of the emitter of the base stage of described the 3rd NPN pipe Q3, the 4th NPN pipe Q4, the 4th NPN pipe Q4 and the negative pole of the 4th voltage stabilizing didoe D4 link to each other with the input signal T4 of its place chip, and the 4th resistance R 4 is connected across between the emitter and base stage of the 4th NPN pipe Q4;

The collector electrode of the emitter of the base stage of described the 4th NPN pipe Q4, the 5th NPN pipe Q5, the 5th NPN pipe Q5 and the negative pole of the 5th voltage stabilizing didoe D5 link to each other with the input signal T5 of its place chip, and the 5th resistance R 5 is connected across between the emitter and base stage of the 5th NPN pipe Q5;

The base stage of described the 5th NPN pipe Q5 and the negative pole of the 6th voltage stabilizing didoe D6 link to each other with the input signal T6 of its place chip, and base stage and the 6th NPN that the 6th resistance R 6 is connected across the 5th NPN pipe Q5 manage between the collector electrode of Q6;

The base stage of described the 6th NPN pipe Q6 links to each other with the collector electrode of the 6th NPN pipe Q6, output output frequency as frequency selective network 1 is selected signal VFS, the emitter of the 6th NPN pipe Q6 links to each other with an end of the 7th resistance R 7, the plus earth of anodal and the 6th voltage stabilizing didoe D6 of the positive pole of the positive pole of the other end of the 7th resistance R 7, the first voltage stabilizing didoe D1, the positive pole of the second voltage stabilizing didoe D2, the 3rd voltage stabilizing didoe D3, the positive pole of the 4th voltage stabilizing didoe D4, the 5th voltage stabilizing didoe D5.

With reference to Fig. 4, band pass filter 2 of the present invention is including, but not limited to the first variable transconductance operational amplifier OTA1, the second variable transconductance operational amplifier OTA2, the first capacitor C 1, the second capacitor C 2, the 8th resistance R 8, the 9th resistance R 9 and current gain network K;

Described the first capacitor C 1 is connected across between the normal phase input end of the input signal VIN of its place chip and the first variable transconductance operational amplifier OTA1, is used for the low-frequency component of input signal VIN of its place chip of filtering; The second capacitor C 2 is connected across between the input and ground of current gain network K, as the load capacitance of the first variable transconductance operational amplifier OTA1;

The inverting input of described the first variable transconductance operational amplifier OTA1 links to each other with an end of the 8th resistance R 8 and an end of the 9th resistance R 9 respectively, the normal phase input end of the first variable transconductance operational amplifier OTA1 links to each other with the output of the second variable transconductance operational amplifier OTA2, and the output of the first variable transconductance operational amplifier OTA1 links to each other with the input of current gain network K;

The other end of described the 8th resistance R 8 links to each other with the in-phase input end of the second variable transconductance operational amplifier OTA2, and the other end of the 9th resistance R 9 links to each other with the inverting input of the second variable transconductance operational amplifier OTA2;

The 3rd input of the 3rd input of described the second variable transconductance operational amplifier OTA2 and the first variable transconductance operational amplifier OTA1 selects signal VFS to link to each other with the frequency that frequency selective network 1 is inputted; The output of current gain network K links to each other with the inverting input of the second variable transconductance operational amplifier OTA2, as the output output filtering signal VBPF of band pass filter 2.

With reference to Fig. 5, integrator 4 of the present invention is including, but not limited to three NMOS pipe, five PNP pipes, five NPN pipes, two capacitor C, a resistance R;

The emitter of described the 7th PNP pipe Q7, the emitter of the 8th PNP pipe Q8, the emitter of the 9th PNP pipe Q9, the emitter of the tenth PNP pipe Q10 all links to each other with supply voltage VCC with the emitter of the 11 PNP pipe Q11, the base stage of the 7th PNP pipe Q7, the base stage of the 8th PNP pipe Q8, the collector electrode of the base stage of the 9th PNP pipe Q9 and the 7th PNP pipe Q7 all links to each other with the drain electrode of NMOS pipe MN1, the base stage of the 11 PNP pipe Q11, the collector electrode of the base stage of the tenth PNP pipe Q10 and the tenth PNP pipe Q10 all links to each other with the drain electrode of the 2nd NMOS pipe MN2, the collector electrode of the 8th PNP pipe Q8 links to each other with the collector electrode of the 16 NPN pipe Q16, as the output output integrated signal VINT of integrator 4, the collector electrode of the 9th PNP pipe Q9 links to each other with an end of the tenth resistance R 10; Emitter area and the collector current size of the 7th PNP pipe Q7, the 8th PNP pipe Q8, the 9th PNP pipe Q9, the tenth PNP pipe Q10 and the 11 PNP pipe Q11 are directly proportional, and the ratio of the emitter area of these five PNP pipes is 2: 1: 1: 1: 1.

The collector electrode of the collector electrode of described the 11 PNP pipe Q11 and the 14 NPN pipe Q14 all links to each other with the base stage of the 12 NPN pipe Q12; The grounded emitter of the 13 NPN pipe Q13, the base stage of the 13 NPN pipe Q13 links to each other with the signal VFS that frequency selective network 1 is inputted, the emitter of the emitter of the emitter of the 14 NPN pipe Q14, the 15 NPN pipe Q15 and the 16 NPN pipe Q16 all is connected to the ground, and the base stage of the base stage of the 14 NPN pipe Q14, the 15 NPN pipe Q15 all links to each other with the emitter of the 12 NPN pipe Q12 with the base stage of the 16 NPN pipe Q16; The collector electrode of the 12 NPN pipe Q12 all links to each other with supply voltage VCC with the collector electrode of the 15 NPN pipe Q15; Emitter area and the collector current size of the 14 NPN pipe Q14, the 15 NPN pipe Q15 and the 16 PNP pipe Q16 are directly proportional, and the ratio of the emitter area of these three NPN pipes is 3: 2: 2;

The grid of described NMOS pipe MN1 links to each other with the reference voltage V REF3 of its place chip, and the source electrode of NMOS pipe MN1 all links to each other with the collector electrode of the 13 NPN pipe with the source electrode of the 2nd NMOS pipe MN2; The grid of the 2nd NMOS pipe MN2 links to each other with the collector electrode of the 9th PNP pipe Q9; The drain electrode of the 3rd NMOS pipe MN3 links to each other with the other end of the tenth resistance R 10, the source ground of the 3rd NMOS pipe MN3, and the grid of the 3rd NMOS pipe MN3 links to each other with the signal VCMP that comparator 3 is inputted;

Between the collector electrode and ground of 3 cross-over connections of described the 3rd capacitor C and the 9th PNP pipe Q9, the 3rd capacitor C 3 has postponed the pulse integration time, has improved the signal to noise ratio of dynamic pulse integrating circuit; Between the collector electrode and ground of 4 cross-over connections of the 4th capacitor C and the 8th PNP pipe Q8, for providing, integrator 4 discharges and recharges.

Operation principle of the present invention is as follows:

Frequency selective network 1 produces frequency-selecting electric current I 1, and the large I of this frequency-selecting electric current I 1 is expressed as:

$\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="HDA00002625042500012.png,HDA00002625042500031.png"\; state="\{\{state\}\}">I</figure-callout>}1=\frac{\mathrm{Vref}1-\mathrm{Vbe}\left(Q6\right)}{R1+R2+R3+R4+R5+R6+R7}---1)$

Wherein Vref1 is the reference voltage of its place chip, Vbe (Q6) is the voltage difference between the 6th NPN pipe Q6 base stage and the emitter, and R1, R2, R3, R4, R5, R6, R7 are respectively the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7 in the frequency selective network 1;

Band pass filter 2 carries out bandpass filtering to the input signal VIN of its place chip, and with reference to Fig. 4, the transfer function H (S) of this band pass filter can be expressed as:

$H\left(S\right)=\frac{\frac{\mathrm{gm}}{C2}\mathrm{<figure-callout\; id="2"\; label="S\; S"\; filenames="HDA00002625042500031.png"\; state="\{\{state\}\}">S</figure-callout>}}{S^{}}---2)$

Wherein gm is respectively the mutual conductance of the first variable transconductance operational amplifier OTA1 and the second variable transconductance operational amplifier OTA2, and R8, R9, C1, C2 are respectively the 8th resistance R 8, the 9th resistance R 9, the first capacitor C 1, the second capacitor C 2 in the band pass filter 2;

The mutual conductance gm of the first variable transconductance operational amplifier OTA1 can be expressed as:

gm=I1/Vt 3)

Wherein Vt at room temperature size be 25.9mV;

By formula 2) as can be known, the centre frequency f0 of band pass filter circuit 2 is:

$f0=\frac{\mathrm{<figure-callout\; id="2"\; label="gm"\; filenames="HDA00002625042500031.png"\; state="\{\{state\}\}">gm</figure-callout>}}{2\mathrm{\&pi;}\sqrt{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="HDA00002625042500012.png,HDA00002625042500031.png"\; state="\{\{state\}\}">C</figure-callout>}1\&CenterDot;C2}}---4)$

Simultaneous formula 3) and formula 4), the centre frequency f0 of band pass filter circuit 2 can be expressed as:

$f0=\frac{I1}{2\mathrm{\&pi;<figure-callout\; id="1"\; label="Vt\; C"\; filenames="HDA00002625042500012.png,HDA00002625042500031.png"\; state="\{\{state\}\}">Vt</figure-callout>}\sqrt{C}\sqrt{1\&CenterDot;C2}}---5)$

By formula 5) can find out that the centre frequency f0 of band pass filter circuit 2 is directly proportional with the frequency-selecting electric current I 1 of frequency selective network 1, by regulating the size of frequency-selecting electric current I 1, can regulate the centre frequency f0 of band pass filter circuit 2.

With reference to Fig. 5, in integrator 4, the integration rising time Tup of integrator 4 can be expressed as:

$\mathrm{Tup}=\frac{2\mathrm{<figure-callout\; id="4"\; label="C"\; filenames="HDA00002625042500012.png"\; state="\{\{state\}\}">C</figure-callout>}4\&CenterDot;\mathrm{\&Delta;}U\max }{I2}=\frac{2\mathrm{<figure-callout\; id="4"\; label="C"\; filenames="HDA00002625042500012.png"\; state="\{\{state\}\}">C</figure-callout>}4\&CenterDot;\mathrm{\&Delta;}U\max }{k\&CenterDot;I1}---6)$

Wherein Δ Umax is the maximum of voltage difference on the 4th capacitor C 4, and I2 is the collector current of the 13 NPN pipe Q13, and k is constant 1/8;

Simultaneous 5) formula and 6) formula, the integrated pulse of integrator 4 rising edges is counted dup and can be expressed as:

$\mathrm{dup}=\mathrm{Tup}\&CenterDot;f0=\frac{\mathrm{<figure-callout\; id="4"\; label="C"\; filenames="HDA00002625042500012.png"\; state="\{\{state\}\}">C</figure-callout>}4\&CenterDot;\mathrm{\&Delta;}U\max }{\mathrm{\&pi;<figure-callout\; id="1"\; label="kVt\; C"\; filenames="HDA00002625042500012.png,HDA00002625042500031.png"\; state="\{\{state\}\}">kVt</figure-callout>}\sqrt{C}\sqrt{1\&CenterDot;C2}}---7)$

With reference to Fig. 5, the integrated pulse of integrator 4 trailing edges is counted ddown and can be expressed as:

$\mathrm{ddown}=\frac{3\mathrm{<figure-callout\; id="4"\; label="C"\; filenames="HDA00002625042500012.png"\; state="\{\{state\}\}">C</figure-callout>}4\&CenterDot;\mathrm{\&Delta;}\mathrm{<figure-callout\; id="4"\; label="U\; max"\; filenames="HDA00002625042500012.png"\; state="\{\{state\}\}">U</figure-callout>}\max }{4\mathrm{\&pi;<figure-callout\; id="1"\; label="kVt\; C"\; filenames="HDA00002625042500012.png,HDA00002625042500031.png"\; state="\{\{state\}\}">kVt</figure-callout>}\sqrt{C}\sqrt{1\&CenterDot;C2}}---8)$

By formula 7) and formula 8) can find out, the integrated pulse of integrator 4 rising edges is counted the integrated pulse of dup and trailing edge and is counted the impact that ddown all is not subjected to its place chip input signal Vin frequency, can make described dynamic pulse integrating circuit carry out integration to the input signal that comprises multi-frequency exactly.

Below only be a preferred example of the present invention, do not consist of any limitation of the invention, obviously under design of the present invention, can carry out different changes and improvement to its circuit, but these are all at the row of protection of the present invention.

Claims (6)

1. dynamic pulse integrating circuit that is not subjected to frequency influence, it is characterized in that: it comprises frequency selective network (1), band pass filter (2), comparator (3), integrator (4) and Schmidt trigger (5);

Described frequency selective network (1) is provided with six input a, b, c, d, e, f and an output g, and these six inputs link to each other with input signal T1, T2, T3, T4, T5, the T6 of its place chip respectively; Output g output frequency is selected signal VFS, and this frequency selects signal VFS to be input to respectively the first input end of the first input end sum-product intergrator (4) of band pass filter (2);

Described band pass filter (2), its second input links to each other with the input signal VIN of its place chip, this band pass filter (2) output filtering signal VBPF is by comparator (3), output comparison signal VCMP, this comparison signal VCMP, through integrator (4) integration, output integrated signal VINT is to Schmidt trigger (5), after Schmidt trigger (5) shaping, export the output signal VOUT of described dynamic pulse integrating circuit.

2. according to claims 1 described dynamic pulse integrating circuit that is not subjected to frequency influence, it is characterized in that frequency selective network (1), comprise six NPN pipes, six voltage stabilizing didoes and seven resistance, wherein:

The negative pole of the first voltage stabilizing didoe D1, emitter, the collector electrode of NPN pipe Q1 all link to each other with the input signal T1 of its place chip, and the first resistance R 1 is connected across between the emitter and base stage of NPN pipe Q1;

The collector electrode of the emitter of the base stage of the one NPN pipe Q1, the 2nd NPN pipe Q2, the 2nd NPN pipe Q2 and the negative pole of the second voltage stabilizing didoe D2 link to each other with the input signal T2 of its place chip, and the second resistance R 2 is connected across between the emitter and base stage of the 2nd NPN pipe Q2;

The collector electrode of the emitter of the base stage of the 2nd NPN pipe Q2, the 3rd NPN pipe Q3, the 3rd NPN pipe Q3 and the negative pole of the 3rd voltage stabilizing didoe D3 link to each other with the input signal T3 of its place chip, and the 3rd resistance R 3 is connected across between the emitter and base stage of the 3rd NPN pipe Q3;

The collector electrode of the emitter of the base stage of the 3rd NPN pipe Q3, the 4th NPN pipe Q4, the 4th NPN pipe Q4 and the negative pole of the 4th voltage stabilizing didoe D4 link to each other with the input signal T4 of its place chip, and the 4th resistance R 4 is connected across between the emitter and base stage of the 4th NPN pipe Q4;

The collector electrode of the emitter of the base stage of the 4th NPN pipe Q4, the 5th NPN pipe Q5, the 5th NPN pipe Q5 and the negative pole of the 5th voltage stabilizing didoe D5 link to each other with the input signal T5 of its place chip, and the 5th resistance R 5 is connected across between the emitter and base stage of the 5th NPN pipe Q5;

The base stage of the 5th NPN pipe Q5 and the negative pole of the 6th voltage stabilizing didoe D6 link to each other with the input signal T6 of its place chip, and base stage and the 6th NPN that the 6th resistance R 6 is connected across the 5th NPN pipe Q5 manage between the collector electrode of Q6;

The base stage of the 6th NPN pipe Q6 links to each other with the collector electrode of the 6th NPN pipe Q6, output output frequency as frequency selective network (1) is selected signal VFS, the emitter of the 6th NPN pipe Q6 links to each other with an end of the 7th resistance R 7, the plus earth of anodal and the 6th voltage stabilizing didoe D6 of the positive pole of the positive pole of the other end of the 7th resistance R 7, the first voltage stabilizing didoe D1, the positive pole of the second voltage stabilizing didoe D2, the 3rd voltage stabilizing didoe D3, the positive pole of the 4th voltage stabilizing didoe D4, the 5th voltage stabilizing didoe D5.

3. according to claims 1 described dynamic pulse integrating circuit that is not subjected to frequency influence, it is characterized in that band pass filter (2), comprise the first variable transconductance operational amplifier OTA1, the second variable transconductance operational amplifier OTA2, the first capacitor C 1, the second capacitor C 2, the 8th resistance R 8, the 9th resistance R 9 and current gain network K;

The first capacitor C 1 is connected across between the normal phase input end of the input signal VIN of its place chip and the first variable transconductance operational amplifier OTA1; The second capacitor C 2 is connected across between the input and ground of current gain network K;

The inverting input of the first variable transconductance operational amplifier OTA1 links to each other with an end of the 8th resistance R 8 and an end of the 9th resistance R 9 respectively, the normal phase input end of the first variable transconductance operational amplifier OTA1 links to each other with the output of the second variable transconductance operational amplifier OTA2, and the output of the first variable transconductance operational amplifier OTA1 links to each other with the input of current gain network K;

The other end of the 8th resistance R 8 links to each other with the in-phase input end of the second variable transconductance operational amplifier OTA2, and the other end of the 9th resistance R 9 links to each other with the inverting input of the second variable transconductance operational amplifier OTA2;

The 3rd input of the 3rd input of the second variable transconductance operational amplifier OTA2 and the first variable transconductance operational amplifier OTA1 selects signal VFS to link to each other with the frequency that frequency selective network (1) is inputted; The output of current gain network K links to each other with the inverting input of the second variable transconductance operational amplifier OTA2, as the output output filtering signal VBPF of band pass filter (2).

4. according to claims 1 described dynamic pulse integrating circuit that is not subjected to frequency influence, it is characterized in that integrator (4), comprise three NMOS pipe, five PNP pipes, five NPN pipes, two capacitor C, a resistance R;

The emitter of the 7th PNP pipe Q7, the emitter of the 8th PNP pipe Q8, the emitter of the 9th PNP pipe Q9, the emitter of the tenth PNP pipe Q10 all links to each other with supply voltage VCC with the emitter of the 11 PNP pipe Q11, the base stage of the 7th PNP pipe Q7, the base stage of the 8th PNP pipe Q8, the collector electrode of the base stage of the 9th PNP pipe Q9 and the 7th PNP pipe Q7 all links to each other with the drain electrode of NMOS pipe MN1, the base stage of the 11 PNP pipe Q11, the collector electrode of the base stage of the tenth PNP pipe Q10 and the tenth PNP pipe Q10 all links to each other with the drain electrode of the 2nd NMOS pipe MN2, the collector electrode of the 8th PNP pipe Q8 links to each other with the collector electrode of the 16 NPN pipe Q16, as the output output integrated signal VINT of integrator (4), the collector electrode of the 9th PNP pipe Q9 links to each other with an end of the tenth resistance R 10;

The collector electrode of the collector electrode of the 11 PNP pipe Q11 and the 14 NPN pipe Q14 all links to each other with the base stage of the 12 NPN pipe Q12; The grounded emitter of the 13 NPN pipe Q13, the base stage of the 13 NPN pipe Q13 links to each other with the signal VFS that frequency selective network (1) is inputted, the emitter of the emitter of the emitter of the 14 NPN pipe Q14, the 15 NPN pipe Q15 and the 16 NPN pipe Q16 all is connected to the ground, and the base stage of the base stage of the 14 NPN pipe Q14, the 15 NPN pipe Q15 all links to each other with the emitter of the 12 NPN pipe Q12 with the base stage of the 16 NPN pipe Q16; The collector electrode of the 12 NPN pipe Q12 all links to each other with supply voltage VCC with the collector electrode of the 15 NPN pipe Q15;

The grid of the one NMOS pipe MN1 links to each other with the reference voltage V REF3 of its place chip, and the source electrode of NMOS pipe MN1 all links to each other with the collector electrode of the 13 NPN pipe with the source electrode of the 2nd NMOS pipe MN2; The grid of the 2nd NMOS pipe MN2 links to each other with the collector electrode of the 9th PNP pipe Q9; The drain electrode of the 3rd NMOS pipe MN3 links to each other with the other end of the tenth resistance R 10, the source ground of the 3rd NMOS pipe MN3, and the grid of the 3rd NMOS pipe MN3 links to each other with the signal VCMP that comparator (3) is inputted;

Between the collector electrode and ground of 3 cross-over connections of the 3rd capacitor C and the 9th PNP pipe Q9, be used for delay pulse time of integration, 4 cross-over connections of the 4th capacitor C are managed between the collector electrode and ground of Q8, for integrator (4) provides charge and discharge capacitance with the 8th PNP.

5. according to claims 4 described integrators (4), it is characterized in that the ratio of the emitter area of the 7th PNP pipe Q7, the 8th PNP pipe Q8, the 9th PNP pipe Q9, the tenth PNP pipe Q10 and the 11 PNP pipe Q11 is 2: 1: 1: 1: 1.

6. according to claims 4 described integrators (4), it is characterized in that the ratio of the emitter area of the 14 NPN pipe Q14, the 15 NPN pipe Q15 and the 16 PNP pipe Q16 is 3: 2: 2.

Images