CN103401404A - Noise eliminating method and noise eliminating circuit - Google Patents

Noise eliminating method and noise eliminating circuit Download PDF

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CN103401404A
CN103401404A CN2013103308999A CN201310330899A CN103401404A CN 103401404 A CN103401404 A CN 103401404A CN 2013103308999 A CN2013103308999 A CN 2013103308999A CN 201310330899 A CN201310330899 A CN 201310330899A CN 103401404 A CN103401404 A CN 103401404A
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signal
frequency
output
circuit
voltage
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CN103401404B (en
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曹何金生
余峰
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Hangzhou Silergy Semiconductor Technology Ltd
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Hangzhou Silergy Semiconductor Technology Ltd
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Abstract

The invention relates to the field of electronics and discloses a noise eliminating method and a noise eliminating circuit. The noise eliminating method comprises the following steps of sampling output voltage signals of a power-level circuit, and obtaining a current output feedback signal; and determining whether the frequency of a first driving signal currently input to the power-level circuit is in an audio range according to a current output feedback signal, if yes, disconnecting the power-level circuit and a circuit of the first driving signal, outputting a first low-frequency driving signal and a first high-frequency driving signal to the power-level circuit, wherein the frequency of the first low-frequency driving signal is lower than the lower limit of the audio, and the frequency of the first high-frequency driving signal is higher than the upper limit of the audio. The application of the technical scheme of the invention facilitates the reduction of the circuit noise and avoidance of the circuit loss.

Description

Noise cancellation method and noise canceller circuit
Technical field
The present invention relates to electronic applications, relate in particular to a kind of noise cancellation method and noise canceller circuit.
Background technology
Power supply generally is comprised of power stage circuit and control circuit, and when power stage circuit was in the underloading operating state, the output feedback signal of the sign output voltage that control circuit detects can reduce.In control circuit, generally can set one be used to characterizing the threshold value of load light condition, during lower than this threshold value, it is burst mode that power stage circuit enters the underloading operating state when the size of output feedback signal.At this moment, control circuit can intermittently be worked, and the frequency that namely inputs to the driving signal of power stage circuit reduces, and along with load lightens, the frequency that drives signal also can reduce.
In circuit, when the frequency that drives signal low when entering audiorange (being the about 20Hz-20kHz of earshot of people's ear), circuit generation audio-frequency noise.
In order to reduce audio-frequency noise, prior art generally makes the mode of load increase improve the frequency of the driving signal that inputs to power stage circuit by increasing by a dummy load, to avoid driving frequency, drop in audiorange, namely avoids the appearance of circuit audio noise.
But in carrying out research process of the present invention, the inventor finds prior art, and there are the following problems at least:
The technical scheme of prior art, eliminate noise for adopting the mode that increases dummy load, and the application of this technical scheme can cause circuit loss to increase.
Summary of the invention
One of embodiment of the present invention purpose is: a kind of noise cancellation method is provided, applies this technical scheme and be conducive to reduce circuit noise and avoid circuit loss.
Two of embodiment of the present invention purpose is: a kind of noise canceller circuit is provided, applies this technical scheme and be conducive to reduce circuit noise and avoid circuit loss.
A kind of noise cancellation method that the embodiment of the present invention provides comprises:
The output voltage signal of sampled power level circuit, obtain current output feedback signal;
According to current described output feedback signal, determine that current the first driving signal frequency that inputs to described power stage circuit is whether in the scope of audio frequency, if so:
Cut off described power stage circuit and be connected with the described first circuit that drives signal,
To described power stage circuit output the first low frequency drive signal, the first high-frequency driving signal, the frequency of wherein said the first low frequency drive signal is lower than described audio frequency lower limit, and the frequency of described the first high-frequency driving signal is higher than the described audio frequency upper limit.
Alternatively, to described power stage circuit output the first low frequency drive signal, comprising:
More current described output feedback signal and low frequency reference ramp voltage, output frequency is lower than the first level signal of described audio frequency lower limit, and described low frequency reference ramp voltage is predefined for: the output feedback voltage fiducial value when the frequency of the driving signal of described power stage circuit during for the predeterminated frequency lower than described audio frequency lower limit;
According to described the first level signal and the first default clock signal, generate described the first low frequency drive signal.
Alternatively, according to described the first level signal and the first default clock signal, generate described the first low frequency drive signal, comprising:
To described first level signal of reset terminal input of the first trigger,
To the default clock signal of set end input described first of described the first trigger,
Described the first trigger is under the triggering of described the first level signal, the first default clock signal, in described the first low frequency drive signal of output output.
Alternatively, the predetermined frequency of the described first default clock signal is the described audio frequency upper limit.
Alternatively, to described power stage circuit output the first high-frequency driving signal, comprising:
More current described output feedback signal and the first low frequency output feedback lower limit, output the first comparison signal,
Under described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is the first low frequency, the output feedback voltage lower limit within the cycle of a described driving signal;
More current described output feedback signal and the first low frequency output feedback upper limit, output the second comparison signal,
On described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is described the first low frequency, the output feedback voltage higher limit within the cycle of a described driving signal;
According to described the first comparison signal, the second comparison signal, generate the second electrical level signal;
According to described second electrical level signal and the second default high-frequency signal, generate described the first high-frequency driving signal,
The frequency of the described second default high-frequency signal is greater than the described audio frequency upper limit.
Alternatively, according to described the first comparison signal, the second comparison signal, generate the second electrical level signal, comprising:
Described the first comparison signal of set end input to the second trigger;
Described the second comparison signal of reset terminal input to described the second trigger;
Described the second trigger is under the triggering of described the first comparison signal, the second comparison signal, at the described second electrical level signal of output output.
Alternatively, according to described second electrical level signal and the second default high-frequency signal, generate described the first high-frequency driving signal, specifically:
To first input end, second input of AND circuit, input respectively described second electrical level signal and the second default high-frequency signal,
Described AND circuit is according to described second electrical level signal, the second default high-frequency signal, at described the first high-frequency driving signal of output output.
Alternatively, to described power stage circuit output the first high-frequency driving signal, comprising:
More current described output feedback signal and the first low frequency output feedback lower limit, output the 3rd comparison signal,
Under described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is the first low frequency, the output feedback voltage lower limit within the cycle of a described driving signal;
According to described the 3rd comparison signal, generate and output output feedback upper limit floating voltage signal, described output feedback upper limit floating voltage signal is greater than described the first low frequency output feedback lower limit;
More current described output feedback signal and described output feedback upper limit floating voltage signal, output the 4th comparison signal,
According to described the 3rd comparison signal, the 4th comparison signal, generate three level signal;
According to described three level signal and the second default high-frequency signal, generate described the first high-frequency driving signal,
The frequency of the described second default high-frequency signal is greater than the described audio frequency upper limit.
Alternatively, according to described the 3rd comparison signal, generate and output output feedback upper limit floating voltage signal, comprising:
The level signal of described the 3rd comparison signal is converted to the first voltage signal,
According to the voltage difference of described the first voltage signal and output voltage lower limit preset value, generate the first current signal,
Described output voltage lower limit preset value is greater than described the first low frequency output feedback lower limit;
Described the first current signal charges to the first building-out capacitor, and the charging voltage signal of described the first building-out capacitor is described output feedback upper limit floating voltage signal.
Alternatively, according to described the 3rd comparison signal, the 4th comparison signal, generate three level signal, comprising:
Described the 3rd comparison signal of set end input to the 3rd trigger;
Described the 4th comparison signal of reset terminal input to described the 3rd trigger;
Described the 3rd trigger is under the triggering of described the 3rd comparison signal, the 4th comparison signal, at the described three level signal of output output.
Alternatively, according to described three level signal and the second default high-frequency signal, generate described the first high-frequency driving signal, specifically:
To first input end, second input of AND circuit, input respectively described three level signal and the second default high-frequency signal,
Described AND circuit is according to described three level signal and the second default high-frequency signal, at described the first high-frequency driving signal of output output.
Alternatively, to described power stage circuit output the first high-frequency driving signal, comprising:
The current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the first low-frequency cycle, the voltage difference of described initial value and described end value is converted into to the second current signal, described the second current signal charges to the second building-out capacitor, at described the second building-out capacitor two ends, obtain the second building-out capacitor voltage signal, described the second building-out capacitor voltage signal is converted into to the first high-frequency signal through voltage controlled oscillator
The frequency of wherein said the first low frequency is lower than described audio frequency lower limit, and the frequency of described the first high frequency is higher than the described audio frequency upper limit,
According to the pulse number of the second default clock signal counting described first high-frequency signal within described first low-frequency cycle, output the first high-frequency count pulse;
More described the first high-frequency count pulse and described the first high-frequency signal, output the 5th comparison signal;
According to the pulse number of the described second default clock signal counting described first low frequency signal within described first low-frequency cycle, output the first low frequency count pulse;
More described the first low frequency count pulse and described the first low frequency signal, output the 6th comparison signal;
According to described the 5th comparison signal, the 6th comparison signal, generate the 4th level signal;
According to described the 4th level signal and the second default high-frequency signal, generate described the first high-frequency driving signal,
The frequency of the described second default high-frequency signal is greater than the described audio frequency upper limit.
Alternatively, according to the pulse number of the second default clock signal counting described first high-frequency signal within described first low-frequency cycle, output the first high-frequency count pulse, specifically:
According to the pulse number of described the first high-frequency signal of the described second default clock signal counting, export described the first high-frequency count pulse, until the voltage difference of described initial value and described end value is while being zero, counting makes zero counts again.
According to described the 5th comparison signal, the 6th comparison signal, generate the 4th level signal, comprising:
Described the 5th comparison signal of reset terminal input to the 4th trigger;
Described the 6th comparison signal of set end input to described the 4th trigger;
Described the 4th level signal of output output at described the 4th trigger.
Alternatively, to described power stage circuit output the first high-frequency driving signal, comprising:
The current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the second low-frequency cycle, the voltage difference of described initial value and described end value is converted into to the 3rd current signal, described the 3rd current signal charges to the 3rd building-out capacitor, at described the 3rd building-out capacitor two ends, obtain the 3rd building-out capacitor voltage signal, described the 3rd building-out capacitor voltage signal is converted into to the second low frequency signal through voltage controlled oscillator, and the frequency of wherein said the second low frequency is lower than described audio frequency lower limit;
According to the pulse number of the second default clock signal counting described second low frequency signal within described second low-frequency cycle, output the second low frequency count pulse;
More described the second low frequency count pulse and described the second low frequency signal, output the 7th comparison signal;
According to the pulse number of the described second default clock signal counting described second high-frequency signal within described second low-frequency cycle, output the second high-frequency count pulse;
More described the second high-frequency count pulse and described the second high-frequency signal, output the 8th comparison signal;
According to described the 7th comparison signal, the 8th comparison signal, generate the 5th level signal;
According to described the 5th level signal and the second default high-frequency signal, generate described the first high-frequency driving signal,
The frequency of the described second default high-frequency signal is greater than the described audio frequency upper limit.
Alternatively, according to the pulse number of the second default clock signal counting described second low frequency signal within described second low-frequency cycle, specifically:
According to the pulse number of described the second low frequency signal of the described second default clock signal counting, export described the second low frequency count pulse, until the voltage difference of described initial value and described end value is while being zero, counting makes zero counts again.
Alternatively, according to described the 7th comparison signal, the 8th comparison signal, generate the 5th level signal, comprising:
Described the 7th comparison signal of set end input to the 5th trigger;
Described the 8th comparison signal of reset terminal input to described the 5th trigger;
Described the 5th level signal of output output at described the 5th trigger.
Alternatively, according to current described output feedback signal, determine that current the first driving signal frequency that inputs to described power stage circuit whether in the scope of audio frequency, comprising:
Current output feedback signal and the voltage difference of the first reference voltage signal of setting according to described output feedback signal are converted to the 4th current signal,
Described the 4th current signal charges to the 4th building-out capacitor, on described the 4th building-out capacitor, obtains described output feedback error signal,
More described output feedback error signal and audio threshold voltage, determine that according to comparative result current the first driving signal frequency that inputs to described power stage circuit is whether in the scope of audio frequency,
Described audio threshold voltage is set as current described the first driving signal frequency and enters the reference voltage of the output feedback error signal of described audiorange critical moment,
If described output feedback error signal greater than described audio threshold voltage, judges that current the first driving signal frequency that inputs to described power stage circuit is in the scope of audio frequency, otherwise,
Judge that current the first driving signal frequency of described power stage circuit that inputs to is not in the scope of audio frequency.
A kind of noise canceller circuit that the embodiment of the present invention provides comprises:
The sampling feedback circuit, for the output voltage signal of sampled power level circuit, obtain current output feedback signal;
Testing circuit, be connected with the output of described sampling feedback circuit, for determining that according to current described output feedback signal current the first driving signal frequency that inputs to described power stage circuit is whether in the scope of audio frequency;
Audio-frequency noise is eliminated circuit, with described testing circuit, is connected, and described audio-frequency noise is eliminated circuit and comprised:
Switch switching circuit, in determining the current scope of the first driving signal frequency at audio frequency that inputs to described power stage circuit the time, cuts off described power stage circuit and is connected with the circuit of described the first driving signal,
The low frequency driving input circuit, for when in the definite current scope of the first driving signal frequency at audio frequency that inputs to described power stage circuit, to described power stage circuit output the first low frequency drive signal, the frequency of described the first low frequency drive signal is lower than described audio frequency lower limit
The high-frequency drive input circuit, for when in the definite current scope of the first driving signal frequency at audio frequency that inputs to described power stage circuit, to described power stage circuit output the first high-frequency driving signal, the frequency of described the first high-frequency driving signal is higher than the described audio frequency upper limit.
Alternatively, described low frequency driving input circuit comprises:
The first comparator, be connected with described sampling feedback circuit, and for relatively exporting feedback error signal and low frequency reference ramp voltage, output frequency is lower than the first level signal of described audio frequency lower limit,
Described low frequency reference ramp voltage is predefined for: the output feedback voltage fiducial value when the frequency of the driving signal of described power stage circuit during for the predeterminated frequency lower than described audio frequency lower limit;
The first trigger, described first level signal of reset terminal access of described the first trigger, the set termination enters the first default clock signal, and described the first trigger is under the triggering in described the first level signal, the first default clock signal, in described the first low frequency drive signal of output output.
Alternatively, described high-frequency drive input circuit comprises:
The second comparator, be connected with described sampling feedback circuit, for more current described output feedback signal and the first low frequency output feedback lower limit, and output the first comparison signal,
Under described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is the first low frequency, the output feedback voltage lower limit within the cycle of a described driving signal;
The 3rd comparator, be connected with described sampling feedback circuit, for more current described output feedback signal and the first low frequency output feedback upper limit, and output the second comparison signal,
On described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is described the first low frequency, the output feedback voltage higher limit within the cycle of a described driving signal;
The second trigger, the set termination of described the second trigger enters described the first comparison signal, described the second comparison signal of reset terminal access, described the second trigger are under the triggering of described the first comparison signal, the second comparison signal, at the described second electrical level signal of output output;
The first AND circuit, the first input end of described AND circuit, the second input access respectively described second electrical level signal, higher than second of the described audio frequency upper limit, preset high-frequency signal, described AND circuit, for according to described second electrical level signal and the second default high-frequency signal, is exported described the first high-frequency driving signal at output.
Alternatively, described high-frequency drive input circuit comprises:
The 4th comparator, be connected with described sampling feedback circuit, for more described output signal and the first low frequency output feedback lower limit, and output the 3rd comparison signal,
Under described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is the first low frequency, the output feedback voltage lower limit within the cycle of a described driving signal;
The RC filter circuit, be connected with the output of described the 4th comparator, for the level signal by described the 3rd comparison signal, is converted to the first voltage signal,
The first mutual conductance amplifying circuit, with described RC filter circuit, be connected, for the voltage difference according to described the first voltage signal and output voltage lower limit preset value, generate the first current signal, described the first current signal charges to the first building-out capacitor, at described the first building-out capacitor two ends, obtain output feedback upper limit floating voltage signal, described output voltage lower limit preset value is greater than described the first low frequency output feedback lower limit;
The 5th comparator, be connected respectively with the output of described sampling feedback circuit, mutual conductance amplifying circuit, for more current described output feedback signal and described output feedback upper limit floating voltage signal, and output the 4th comparison signal,
The 3rd trigger, the set termination of described the 3rd trigger enters described the 3rd comparison signal, described the 4th comparison signal of reset terminal access, described the 3rd trigger are under the triggering of described the 3rd comparison signal, the 4th comparison signal, at output output three level signal;
The second AND circuit, the first input end of described AND circuit, the second input access respectively described three level signal and the second default high-frequency signal, described AND circuit, for according to described three level signal and the second default high-frequency signal, is exported described the first high-frequency driving signal at output;
The frequency of the described second default high-frequency signal is higher than the described audio frequency upper limit.
Alternatively, described high-frequency drive input circuit comprises:
The second mutual conductance amplifying circuit, with described sampling feedback circuit, be connected, be used for according to the current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the first low-frequency cycle, the voltage difference of described initial value and described end value is converted into to the second current signal, described the second current signal charges to the second building-out capacitor, at described the second building-out capacitor two ends, obtains the second building-out capacitor voltage signal
The first oscillating circuit, with the output of described mutual conductance amplifying circuit, be connected, for described the second building-out capacitor voltage signal is converted into to the first high-frequency signal through voltage controlled oscillator, the frequency of wherein said the first low frequency is lower than described audio frequency lower limit, and the frequency of described the first high frequency is higher than the described audio frequency upper limit;
The first counter, be connected with the output of described oscillating circuit, for the pulse number according to the second default clock signal counting described first high-frequency signal within described first low-frequency cycle, output the first high-frequency count pulse;
The 6th comparator, be connected with the output of described the first counter, for more described the first high-frequency count pulse and described the first high-frequency signal, and output the 5th comparison signal;
The second counter, for the pulse number according to the described second default clock signal counting described first low frequency signal within described first low-frequency cycle, output the first low frequency count pulse;
The 7th comparator, be connected with the output of described the second counter, for more described the first low frequency count pulse and described the first low frequency signal, and output the 6th comparison signal;
The 4th trigger, the reset terminal of described the 4th trigger, set end are connected with the output of described the 6th comparator, the 7th comparator respectively, under the triggering at described the 5th comparison signal, the 6th comparison signal, in output output the 4th level signal;
The 3rd AND circuit, the first input end of described the 3rd AND circuit, the second input access respectively described the 4th level signal and the second default high-frequency signal, described the 3rd AND circuit, for according to described the 4th level signal and the second default high-frequency signal, is exported described the first high-frequency driving signal at output.
Alternatively, described high-frequency drive input circuit comprises:
The 3rd mutual conductance amplifying circuit, with described sampling feedback circuit, be connected, be used for according to the current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the second low-frequency cycle, the voltage difference of described initial value and described end value is converted into to the 3rd current signal, described the 3rd current signal charges to the 3rd building-out capacitor, at described the 3rd building-out capacitor two ends, obtains the 3rd building-out capacitor voltage signal
The second oscillating circuit, be connected with the output of described mutual conductance amplifying circuit, and for described the 3rd building-out capacitor voltage signal is converted into to described the second low frequency signal through voltage controlled oscillator, the frequency of wherein said the second low frequency signal is lower than described audio frequency lower limit;
The 3rd counter, be connected with the output of described oscillating circuit, for according to the second default clock signal, counts the pulse number of described the second low frequency signal within described second low-frequency cycle, output the second low frequency count pulse;
The 8th comparator, be connected with the output of described the 3rd counter, for more described the second low frequency count pulse and described the second low frequency signal, and output the 7th comparison signal;
Four-counter, for according to the described second default clock signal, count the pulse number of described the second high-frequency signal, output the second high-frequency count pulse, and the frequency of wherein said the second high frequency is higher than the described audio frequency upper limit;
The 9th comparator, be connected with the output of described four-counter, for more described the second high-frequency count pulse and described the second high-frequency signal, and output the 8th comparison signal;
The 5th trigger, the set end of described the 5th trigger, reset terminal are connected with the output of described the 8th comparator, the 9th comparator respectively, under the triggering at described the 7th comparison signal, the 8th comparison signal, in output output the 5th level signal;
The 4th AND circuit, the first input end of described AND circuit, the second input access respectively described the 5th level signal and the second default high-frequency signal, described AND circuit, for according to described the 5th level signal and the second default high-frequency signal, is exported described the first high-frequency driving signal at output.
Alternatively, described testing circuit comprises:
Error amplifying circuit, with described sampling feedback circuit, be connected, for current output feedback signal and the voltage difference of the first reference voltage signal of setting according to described output feedback signal are converted to the 4th current signal, described the 4th current signal charges to the 4th building-out capacitor, on described the 4th building-out capacitor, obtain described output feedback error signal
The tenth comparator, with the output of described error amplifying circuit, be connected, for more described output feedback error signal and audio threshold voltage, to described audio-frequency noise, eliminate the Enable Pin output enable control signal of circuit, if described output feedback error signal is greater than described audio threshold voltage, to described audio-frequency noise, eliminate the Enable Pin output enable control signal of circuit, to drive described audio-frequency noise, eliminate circuit working
Described audio threshold voltage is set as current described the first driving signal frequency and enters the reference voltage of the output feedback error signal of described audiorange critical moment.
therefore, application the present embodiment technical scheme, can determine that whether the frequency of the current driving signal that inputs to power stage circuit is in audiorange by the Real-Time Monitoring of output feedback voltage, in case it enters in audiorange, cut off the input of this signal of driving in audiorange (be designated as first and drive signal), replace to power stage circuit input not in the low frequency drive signal of audiorange, high-frequency driving signal, by this low frequency drive signal, the common combination of high-frequency driving signal, and simulate former first, drive the driving input of signal to power stage circuit, in the driving of power stage circuit, produce the effect substantially constant with former driving input.And due to this moment, input to the frequency of driving signal of power stage circuit all not in audiorange, therefore can not produce audio-frequency noise on circuit, be conducive to eliminate the circuit audio noise.
With respect to prior art, by adding dummy load, improve the technical scheme that driving signal frequency avoids audio-frequency noise to produce, adopt the present embodiment technical scheme, without increasing dummy load, without the loss that increases circuit.
The accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, does not form inappropriate limitation of the present invention, in the accompanying drawings:
The noise cancellation method schematic flow sheet that Fig. 1 provides for the embodiment of the present invention 1;
The noise canceller circuit theory structure schematic diagram that Fig. 2 provides for embodiment of the present invention 1-6;
The first low frequency drive signal input circuit theory structure schematic diagram that Fig. 3 provides for the embodiment of the present invention 2;
The stagnant around-France first high-frequency driving signal input circuit theory structure schematic diagram of realizing of employing that Fig. 4 provides for the embodiment of the present invention 3;
The employing penalty method that Fig. 5 provides for the embodiment of the present invention 4 realizes the first high-frequency driving signal input circuit theory structure schematic diagram;
The employing high frequency frequency variation method that Fig. 6 provides for the embodiment of the present invention 5 is realized the first high-frequency driving signal input circuit theory structure schematic diagram;
The employing low frequency frequency variation method that Fig. 7 provides for the embodiment of the present invention 6 is realized the first high-frequency driving signal input circuit theory structure schematic diagram;
Fig. 8 is the prior art first output feedback signal waveform schematic diagram when driving signal and entering audiorange;
Fig. 9 is when the first driving signal enters audiorange, the output feedback signal waveform schematic diagram that the technical scheme that application embodiment of the present invention 1-6 provides obtains.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, describe the present invention in detail, in this illustrative examples of the present invention and explanation, be used for explaining the present invention, but not as a limitation of the invention.
Embodiment 1:
Shown in Figure 1, the present embodiment provides a kind of noise cancellation method, and the method mainly comprises the following steps:
Step S101: the output voltage signal of sampled power level circuit, obtain current output feedback signal.
Output at power stage circuit passes through sampling feedback circuit 202 sampling and outputting voltage signals, by sampling feedback circuit 202, obtains current output feedback signal, and this output feedback signal changes with the current output voltage signal intensity.For example:
In Fig. 2, by the electric resistance partial pressure sample circuit, as sampling feedback circuit 202, be connected to the power stage circuit output, obtain output feedback signal Vs, this output feedback signal Vs and the proportional relation of output voltage signal Vo, Vs=Vo*R2/ (R1+R2).
Step S102: determine that according to current output feedback signal current the first driving signal frequency that inputs to power stage circuit is whether in the scope of audio frequency.
In circuit, when power stage circuit is in the underloading operating state, input to the corresponding reduction of frequency of the driving signal of power stage circuit, output feedback signal can corresponding reduction.Therefore can judge by the real-time change that detects output feedback signal the frequency range of the driving signal that inputs to power stage circuit in practice.
In circuit, when the frequency of the driving signal that inputs to power stage circuit entered audiorange, circuit can produce audio-frequency noise.And can utilize the Real-Time Monitoring of output feedback signal in the present embodiment and monitor to determine whether the current frequency that inputs to the driving signal of power stage circuit falls into audiorange, and carry out corresponding audio-frequency noise elimination, inhibitory control is processed.
The frequency range that can hear of described audiorange behaviour ear, generally be set as 20Hz to 20kHz in the present embodiment.
In the present embodiment, the former external drive signal that inputs to power stage circuit is designated as to f_q1.
Shown in Figure 2, according to current described output feedback signal, determine that the current f_q1 frequency that inputs to power stage circuit 201 whether in the scope of audio frequency, can be, but not limited to realize by the following technical solutions.
Can be, but not limited to adopt error amplifying circuit 203 that the voltage difference of current output feedback signal Vs and the first reference voltage signal Vref1 (it is according to the predefined reference signal of Vs) is converted to the 4th current signal, the 4th current signal charges to the 4th building-out capacitor C4, on the 4th building-out capacitor C4, obtains exporting feedback error signal Vc.
then will export feedback error signal Vc and input to the tenth comparator C OMP10, the tenth comparator C OMP10 relatively exports feedback error signal Vc and audio threshold voltage Vc-th compares, this moment can be according to the Output rusults of the tenth comparator C OMP10, determine that the current f_q1 frequency that inputs to power stage circuit is whether in the scope of audio frequency: if output feedback error signal Vc is less than audio threshold voltage Vc-th, determine that the current f_q1 frequency of power stage circuit that inputs to is not in the scope of audio frequency, to noise canceller circuit 204 output disable control signals, noise canceller circuit 204 does not carry out work, the processing of execution step S106, otherwise the current f_q1 frequency that inputs to described power stage circuit is in the scope of audio frequency, and to noise canceller circuit 204 output enable control signals, noise canceller circuit 204 enables to work under control signal control at this, the processing of execution step S104-S105.
Wherein, audio threshold voltage Vc-th is people's default threshold limit values during according to the circuit actual motion, and be specially: current f_q1 frequency enters the reference voltage of the output feedback error signal of described audiorange critical moment.
Step S103: if the first driving signal frequency that inputs to power stage circuit performs step S104 in the scope of audio frequency, otherwise redirect execution step S106.
If the frequency of former f_q1, when audiorange, performs step S104, otherwise, according to prior art, carry out, continue to input this f_q1 to this power stage circuit, realize power drive.
Step S104: rupturing duty level circuit is connected with the described first circuit that drives signal.
In this step, cut off current frequency in the f_q1 of the audiorange driving input to power stage circuit, and switch to the low-and high-frequency drive input of the present embodiment.
Shown in Figure 2, can in the low-and high-frequency of power stage circuit 201 and f_q1, the present embodiment, drive between signal the switching tube Qb work that switch switching circuit makes power stage circuit that arranges, for in the scope of f_q1 frequency at audio frequency when inputing to power stage circuit 201 time, cut off current frequency in the f_q1 of the audiorange driving input to power stage circuit 201, and switch to the low-and high-frequency drive input of the present embodiment.
Step S105: to power stage circuit output the first low frequency drive signal f_Lq, the first high-frequency driving signal f_Hq.
To the power stage circuit output frequency lower than the first low frequency drive signal f_Lq of audio frequency lower limit and frequency the first high-frequency driving signal f_Hq higher than the audio frequency upper limit.
Further the input circuit about the first low frequency signal, the first high-frequency signal specifically can be, but not limited to the detailed description that vide infra, and also can generate and input in the power stage circuit of the present embodiment according to prior art.
Step S106: the driving input that keeps f_q1.
In the present embodiment, this audio frequency lower limit set is 20Hz, and the audio frequency upper limit is set as 20kHz.
therefore, application the present embodiment technical scheme, can determine that whether the frequency of the current driving signal that inputs to power stage circuit is in audiorange by the Real-Time Monitoring of output feedback voltage, in case it enters in audiorange, cut off the input of this signal of driving in audiorange (being designated as f_q1), replace to power stage circuit input not in the low frequency drive signal of audiorange, high-frequency driving signal, by this low frequency drive signal, the common combination of high-frequency driving signal, and simulate former f_q1, the driving of power stage circuit is inputted, in the driving of power stage circuit, produce the effect substantially constant with former driving input.And due to this moment, input to the frequency of driving signal of power stage circuit all not in audiorange, therefore can not produce audio-frequency noise on circuit, be conducive to eliminate the circuit audio noise.
With respect to prior art, by adding dummy load, improve the technical scheme that driving signal frequency avoids audio-frequency noise to produce, adopt the present embodiment technical scheme, without increasing dummy load, without the loss that increases circuit.
Shown in Fig. 8,9, visible, adopt the present embodiment technical scheme can be without increasing dummy load, on the basis without the loss that increases circuit, change the frequency that drives signal and realize the effect substantially constant with former driving input.
Embodiment 2:
1 difference of the present embodiment and embodiment only is:
As the signal of the present embodiment, as the first low frequency drive signal f_Lq lower than the audio frequency lower limit that inputs to power stage circuit, can be, but not limited to obtain by the following technical solutions, it mainly comprises the following steps:
Step S1051: relatively export feedback error signal and low frequency reference ramp voltage, output frequency is lower than the first level signal of audio frequency lower limit.
In the present embodiment low frequency reference ramp voltage can be predefined for: the output feedback voltage when the frequency of the driving signal of power stage circuit during for the predeterminated frequency lower than the audio frequency lower limit is designated as Vramp.While for example can be, but not limited to be 10Hz by driving frequency, corresponding output voltage signal is set as low frequency reference ramp voltage Vramp, and wherein, Vramp is a ramp voltage.
In this step, can be, but not limited to adopt the first comparator C OMP1 relatively to export feedback error signal Vc and low frequency reference ramp voltage Vramp, thereby in the level signal of output output one frequency lower than the audio frequency lower limit, be designated as the first level signal, because the first level signal is relevant to the output feedback error signal, and the output feedback error signal is relevant to the output voltage signal of power stage circuit, therefore the first level signal that obtains is relevant to the output voltage signal of power stage circuit, can reflect the characteristic of the output voltage signal of current power level circuit.
in the present embodiment, can also but be not limited to before relatively exporting feedback error signal and low frequency reference ramp voltage, adopt as shown in Figure 2 error amplifying circuit 203 that the voltage difference of current output feedback signal Vs and the first reference voltage signal Vref1 (it is according to the predefined reference signal of Vs) is converted to the 4th current signal, the 4th current signal charges to the 4th building-out capacitor C4, on the 4th building-out capacitor C4, obtain exporting feedback error signal Vc, then as shown in Figure 3, output feedback error signal Vc and the corresponding low frequency reference ramp of this signal voltage Vramp after by the first comparator C OMP1, error being amplified compare, obtain the first above-mentioned level signal.
Step S1052: according to the first level signal, the first default clock signal, generate the first low frequency drive signal f_Lq.
This first default clock signal clk 1 is the clock signal predefined during according to the circuit actual motion by the user, that frequency is not more than the audio frequency upper limit in the present embodiment.Can be, but not limited in the present embodiment be set for frequency is the clock signal of clock upper limit 20kHz, can also but to be not limited to be set for frequency be the clock signal of 18kHZ.
This step is not preset clock signal clk 1 higher than first of the audio frequency upper limit according to frequency lower than the first level signal and the frequency of audio frequency lower limit, generate the first low frequency drive signal f_Lq of audio frequency lower than the audio frequency lower limit, output it to power stage circuit, in order to jointly drive this power stage circuit with the first high-frequency driving signal f_Hq.
At the present embodiment, can be, but not limited to adopt trigger, be designated as the first trigger 301 and generate this first low frequency drive signal f_Lq, specifically shown in Figure 3.
Reset terminal " R " input the first level signal d1 to the first trigger 301, the default clock signal clk 1 of set end " S " input first to the first trigger 301, the first trigger 301 is under the triggering of the first level signal d1, the first default clock signal clk 1, at described the first low frequency drive signal f_Lq of output " Q " output.When set end " S " is high level " 1 ", when reset terminal " R " is low level " 0 ", the output of the first trigger 301 " Q " output high level " 1 "; When set end " S " is low level " 0 ", when reset terminal " R " is high level " 1 ", the output of the first trigger 301 " Q " output low level " 0 "; Other input states, the output of the first trigger 301 " Q " keeps former output state.
Embodiment 3:
1 difference of the present embodiment and embodiment only is:
As the signal of the present embodiment, as the first high-frequency driving signal f_Hq higher than the audio frequency upper limit that inputs to power stage circuit, can be, but not limited to adopt stagnant around-France realization.According to the stagnant around-France first high-frequency driving signal f_Hq technical scheme of obtaining, mainly comprise the following steps:
Step S301: more current output feedback signal and the first low frequency output feedback lower limit, output the first comparison signal f1.
Wherein, the first low frequency output feedback lower limit is predetermined to be and can characterizes the output feedback signal minimum value.
The first low frequency output feedback lower limit can but do not limit and be set to: when the frequency of the driving signal of power stage circuit during for the first low frequency lower than audio frequency, the output feedback voltage lower limit within a cycle that drives signal.
The first low frequency output feedback lower limit can also but be not limited to be set to: according at least two frequencies, lower than the output feedback signal lower limit of the driving signal of audio frequency lower limit, add up the mean value of acquisition.
More current output feedback signal, the first low frequency output feedback lower limit, the level signal of output comparative result, be designated as the first comparison signal f1.
Step S302: more current output feedback signal and the first low frequency output feedback upper limit, output the second comparison signal f2,
Wherein, the first low frequency output feedback upper limit is predetermined to be and can characterizes the output feedback signal maximum.
The first low frequency output feedback upper limit can but do not limit and be set to: when the frequency of the driving signal of power stage circuit is above-mentioned the first low frequency, the output feedback voltage higher limit within a cycle that drives signal.
The first low frequency output feedback upper limit can also but be not limited to be set to: according at least two frequencies, lower than the output feedback signal higher limit of the driving signal of audio frequency lower limit, add up the mean value of acquisition.
More current output feedback signal, the first low frequency output feedback upper limit, the level signal of output comparative result, be designated as the second comparison signal f2.
Step S303: according to the first comparison signal f1, the second comparison signal f2, generate second electrical level signal fd2.
In the present embodiment, by more current output feedback signal and the first low frequency output feedback lower limit and more current output feedback signal and the first low frequency are exported the size of feeding back the upper limit respectively, and the state at definite current output feedback signal place, according to comparative result, to export the level signal that meets current power level circuit working state, be designated as second electrical level signal fd2, in order to further generate the first high-frequency driving signal f_Hq according to this second electrical level signal fd2.
Step S304: according to second electrical level signal fd2 and the second default high-frequency signal f_h2, generate the first high-frequency driving signal f_Hq.
In the present embodiment, can be, but not limited to first input end, the second input to AND circuit and input respectively above-mentioned second electrical level signal fd2, frequency the second default high-frequency signal f_h2 greater than the audio frequency upper limit, AND circuit, according to second electrical level signal fd2 and the second default high-frequency signal f_h2, is exported the first high-frequency driving signal f_Hq of this frequency higher than the audio frequency upper limit at output.
Stagnant around-France circuit enforcement technical scheme can be, but not limited to shown in Figure 4, for example:
Can be, but not limited to input respectively at in-phase input end, the inverting input of the second comparator C OMP2: the first low frequency output feedback lower limit (being designated as Vs_L), current output feedback signal Vs, the output of the second comparator C OMP2 is exported this first comparison signal f1 to the set end " S " of the second trigger 402.
At in-phase input end, the inverting input of the 3rd comparator C OMP3, input respectively current output feedback signal Vs, the first low frequency output feedback upper limit (being designated as Vs-H), the output of the 3rd comparator C OMP3 is exported this second comparison signal f2 to the reset terminal " R " of the second trigger 402.The second trigger 402 is under the triggering of the first comparison signal f1, the second comparison signal f2, at output " Q " output second electrical level signal fd2, the first input end of the first AND circuit 401 receives second electrical level signal fd2, the second input of the first AND circuit 401 receives the second default high-frequency signal f_h2, the first 401 pairs of AND circuit second electrical level signal fd2, the second default high-frequency signal f_h2 carry out and computing, obtain the first above-mentioned high-frequency driving signal f_Hq.
In Fig. 4 circuit, if Vs<Vs_L, can determine the current underfrequency that inputs to the f_q1 of power stage circuit, fallen into audiorange, the signal that inputs to set end " S " end of the second trigger 402 this moment is high level " 1 ", the signal that inputs to reset terminal " R " end of the second trigger 402 is low level " 0 ", and the second electrical level signal of the output " Q " of the second trigger 402 output at this moment is high level " 1 ".
If Vs > Vs_H, can determine that the frequency of the current f_q1 that inputs to power stage circuit is higher and higher than the audio frequency upper limit, set end " S " end that inputs to the second trigger 402 this moment is low level " 0 ", reset terminal " R " end that inputs to the second trigger 402 is high level " 1 ", and the second electrical level signal of the output " Q " of the second trigger 402 output at this moment is low level " 0 ".
If Vs_L<Vs<Vs_H, the frequency that can determine the current f_q1 that inputs to power stage circuit is lower, but can not determine whether it has fallen into audiorange, the signal that inputs to set end " S " end of the second trigger 402 this moment is low level " 0 ", the signal that inputs to reset terminal " R " end of the second trigger 402 is low level " 0 ", this moment the second trigger 402 the second electrical level signal of output " Q " the output state of remaining stationary, namely identical with the state in a upper moment.
Embodiment 4:
1 difference of the present embodiment and embodiment only is:
As the signal of the present embodiment, as the first high-frequency driving signal f_Hq higher than the audio frequency upper limit that inputs to power stage circuit, can be, but not limited to adopt penalty method to realize.According to penalty method, obtaining the first high-frequency driving signal f_Hq technical scheme mainly comprises the following steps:
Step S401: more current output feedback signal and the first low frequency output feedback lower limit, output the 3rd comparison signal f3.
With above-mentioned steps S301 in like manner, the first low frequency output feedback lower limit in this penalty method is predetermined to be and can characterizes the output feedback signal minimum value.The first low frequency output feedback lower limit can but do not limit and be set to: when the frequency of the driving signal of power stage circuit during for the first low frequency lower than audio frequency, the output feedback voltage lower limit within a cycle that drives signal.
The first low frequency output feedback lower limit can also but be not limited to be set to: according at least two frequencies, lower than the output feedback signal lower limit of the driving signal of audio frequency lower limit, add up the mean value of acquisition.
Can be, but not limited to by the more current output feedback signal of the 4th comparator and the first low frequency output feedback lower limit, the level signal of output comparative result, be designated as the 3rd comparison signal f3.
Step S402: according to the 3rd comparison signal f3, generate output feedback upper limit floating voltage signal.
In the present embodiment, because the 3rd comparison signal f3 is relevant to current output feedback signal, therefore it can reflect state and the characteristic of current output feedback signal.In the present embodiment, according to the 3rd comparison signal f3, generate and export a signal of the output feedback upper limit floating voltage greater than the first low frequency output feedback lower limit, be designated as Vs-H2, this output feedback upper limit floating voltage signal Vs-H2 can be used as and characterizes the peaked parameter of output feedback signal.
In the present embodiment, the variation of following the tracks of current output feedback signal due to output feedback upper limit floating voltage signal Vs-H2 changes, therefore applying it eliminates to control to noise and more can reflect the current state that inputs to the driving signal of power stage circuit, make its inhibition to the circuit audio noise, eliminate and control more realistic circuit state, make to control more accurate.
Step S403: more current output feedback signal and output feedback upper limit floating voltage signal, output the 4th comparison signal f4.
More current output feedback signal and output feedback upper limit floating voltage signal, the level signal of output comparative result, be designated as the 4th comparison signal f4.
Step S404: according to the 3rd comparison signal f3, the 4th comparison signal f4, generate three level signal fd3.
In the present embodiment, by lower limit is fed back in more current output feedback signal and the output of the first low frequency respectively, and more current output feedback signal and the size of exporting feedback upper limit floating voltage signal, and the state at definite current output feedback signal place, according to comparative result, to export the level signal that meets current power level circuit working state, be designated as three level signal fd3, in order to further generate the first high-frequency driving signal f_Hq according to this three level signal fd3.
Step S405: according to three level signal fd3 and the second default high-frequency signal f_h2, generate the first high-frequency driving signal f_Hq.
With step S304 in like manner, the second default high-frequency signal f_h2 of the present embodiment is the frequency signal of frequency greater than the audio frequency upper limit.
In the present embodiment, can be, but not limited to first input end, the second input to the second AND circuit 502 and input respectively above-mentioned three level signal fd3, frequency the second default high-frequency signal f_h2 greater than the audio frequency upper limit, AND circuit, according to three level signal fd3 and the second default high-frequency signal f_h2, is exported the first high-frequency driving signal f_Hq of this frequency higher than the audio frequency upper limit at output.
The circuit of penalty method is implemented technical scheme and be can be, but not limited to shown in Figure 5:
The in-phase input end, the inverting input that can be, but not limited at the 4th comparator C OMP4 are inputted respectively the first low frequency output feedback lower limit (being designated as Vs_L), current output feedback signal Vs, the output of the 4th comparator C OMP4, to the level signal of set end " S " the output comparative result of the 3rd trigger 503, is designated as the 3rd comparison signal f3.
and the 3rd comparison signal f3 is passed through by filter resistance Rf, and the RC filter circuit 501 of filter capacitor Cf composition, the 3rd comparison signal f3 is converted to voltage signal, be designated as V1, this voltage signal V1 is inputed to the first mutual conductance amplifying circuit Gm1, the first mutual conductance amplifying circuit Gm1 is converted into current signal by voltage signal V1 with the voltage difference be used to the reference signal Vref2 (being output voltage lower limit preset value) that characterizes the output voltage minimum value, be designated as the first current signal, the first current signal charges to the first building-out capacitor C1, obtain output feedback upper limit floating voltage signal Vs-H2.
At in-phase input end, the inverting input of the 5th comparator C OMP5, input respectively current output feedback signal Vs, output feedback upper limit floating voltage signal Vs-H2, the output of the 5th comparator C OMP5 is exported the comparative result level signal to the reset terminal " R " of the 3rd trigger 503: the 4th comparison signal f4.The 3rd trigger 503 is under the triggering of the 3rd comparison signal f3, the 4th comparison signal f4, at the first input end output three level signal fd3 of output " Q " to the second AND circuit 502, the second 502 pairs of AND circuit three level signal fd3, higher than the second default high-frequency signal f_h2 of the described audio frequency upper limit, carry out and computing, obtain the first above-mentioned high-frequency driving signal f_Hq.
With Fig. 4 in like manner, in Fig. 5, if Vs<Vs-L, can determine the current underfrequency that inputs to the f_q1 of power stage circuit, fallen into audiorange, the signal that inputs to set end " S " end of the 3rd trigger 503 this moment is high level " 1 ", and the signal that inputs to reset terminal " R " end of the 3rd trigger 503 is low level " 0 ", and the three level signal fd3 of the output " Q " of the 3rd trigger 503 output at this moment is high level " 1 ".
If Vs > Vs-H2, can determine that the frequency of the current f_q1 that inputs to power stage circuit is higher and higher than the audio frequency upper limit, the signal that inputs to set end " S " end of the 3rd trigger 503 this moment is low level " 0 ", the signal that inputs to reset terminal " R " end of the 3rd trigger 503 is high level " 1 ", and the three level signal fd3 of the output " Q " of the 3rd trigger 503 output at this moment is low level " 0 ".
If Vs-L<Vs<Vs-H2, the frequency that can determine the current f_q1 that inputs to power stage circuit is lower, but can not determine whether it has fallen into audiorange, the signal that inputs to set end " S " end of the 3rd trigger 503 this moment is low level " 0 ", the signal that inputs to reset terminal " R " end of the 3rd trigger 503 is low level " 0 ", this moment the 3rd trigger 503 the three level signal fd3 of output " Q " the output state of remaining stationary, namely identical with the state in a upper moment.
Embodiment 5:
1 difference of the present embodiment and embodiment only is:
As the signal of the present embodiment, as the first low frequency drive signal f_Hq higher than the audio frequency upper limit that inputs to power stage circuit, can be, but not limited to adopt the high frequency frequency variation method to realize.According to the high frequency frequency variation method, obtaining the first high-frequency driving signal f_Hq technical scheme mainly comprises the following steps:
step S501: the current output feedback signal of Real-Time Monitoring, obtain the voltage initial value Vs_s at the default output feedback signal of the first low frequency lower than the audio frequency lower limit (being designated as fL1) in the cycle, end value Vs_e, the second transconductance circuit Gm2 is converted into the second current signal by the voltage difference of the end value Vs_e of the initial value Vs_s of Real-time Obtaining and Real-time Obtaining, the second current signal charges to the second building-out capacitor C2, at the second building-out capacitor C2 two ends, obtain the second building-out capacitor voltage signal V2, the second building-out capacitor voltage signal V2 is converted into to the first high-frequency signal fH1 of frequency higher than the described audio frequency upper limit through voltage controlled oscillator 600, wherein the frequency of the first high-frequency signal fH1 can be determined by the setting parameter of voltage controlled oscillator 600.
Step S502: according to the second default clock signal clk 2, the pulse number of counting first high-frequency signal fH1 within the first low frequency signal fL1 cycle, output the first high-frequency count pulse f_hm1.
In the present embodiment, signal as the present embodiment, can be, but not limited to determine according to the voltage difference of voltage initial value Vs_s, the end value Vs_e of the output feedback signal of Real-Time Monitoring the time range at fL1 cycle place, be this step specifically, pulse number according to second default clock signal clk 2 counting the first high-frequency signal fH1, export the first high-frequency count pulse f_hm1, until the voltage difference of the current output feedback signal initial value Vs_s that obtains and end value Vs_e is while being zero, the counting counting again that makes zero.
On circuit is realized, can be, but not limited to ground shown in Figure 6, by the first counter 601, under the driving of the second default clock signal clk 2, calculate the pulse number of the first high-frequency signal fH1, output the first high-frequency count pulse f_hm1.
Step S503: compare the first high-frequency count pulse f_hm1 and the first high-frequency signal fH1, output the 5th comparison signal f5.
On circuit is realized, can be, but not limited to ground shown in Figure 6, to in-phase input end, the inverting input of the 6th comparator C OMP6, input respectively the first high-frequency signal fH1, the first high-frequency count pulse f_hm1 respectively, the level signal of output comparative result, be designated as the 5th comparison signal f5.
Step S504: according to the second above-mentioned default clock signal clk 2, the pulse number of counting first low frequency signal fL1 within the first low frequency signal fL1 cycle, output the first low frequency count pulse f_lm1.
On circuit is realized, can be, but not limited to ground shown in Figure 6, by the second counter 602 under the driving of the second default clock signal clk 2, according to the pulse number of frequency counting the first low frequency signal fL1 of CLK2, output the first low frequency count pulse f_lm1.
Step S505: compare the first low frequency count pulse f_lm1 and the first low frequency signal fL1, output the 6th comparison signal f6.
On circuit is realized, can be, but not limited to ground shown in Figure 6, to in-phase input end, the inverting input of the 7th comparator C OMP7, input respectively the first low frequency signal fL1, the first low frequency count pulse f_lm1 respectively, the level signal of output comparative result, be designated as the 6th comparison signal f6.
Step S506: according to the 5th comparison signal f5, the 6th comparison signal f6, generate the 4th level signal fd4.
On circuit is realized, can be, but not limited to ground shown in Figure 6, to reset terminal " R ", the set end " S " of the 4th trigger 604, input respectively respectively: the 5th comparison signal f5, the 6th comparison signal f6, at output " Q " output the 4th level signal fd4 of the 4th trigger 604.
Step S507: according to the 4th level signal fd4 and the second default high-frequency signal f_h2, generate described the first high-frequency driving signal f_Hq.
On circuit is realized, can be, but not limited to ground shown in Figure 6, with above-mentioned stagnant around-France, penalty method in like manner, in the present embodiment, can be, but not limited to first input end, the second input to the 3rd AND circuit 603 and input respectively above-mentioned second electrical level signal fd2, frequency the second default high-frequency signal f_h2 greater than the audio frequency upper limit, the 3rd AND circuit 603, according to second electrical level signal fd2 and the second default high-frequency signal f_h2, is exported the first low frequency drive signal f_Hq of this frequency higher than the audio frequency upper limit at output.
Embodiment 6
1 difference of the present embodiment and embodiment only is:
As the signal of the present embodiment, as the first low frequency drive signal f_Hq higher than the audio frequency upper limit that inputs to power stage circuit, can be, but not limited to adopt the low frequency frequency variation method to realize.According to the low frequency frequency variation method, obtaining the first high-frequency driving signal f_Hq technical scheme mainly comprises the following steps:
step S601: the current output feedback signal of Real-Time Monitoring, obtain the voltage initial value Vs_s at the default output feedback signal of the second low frequency signal lower than the audio frequency lower limit (being designated as fL2) in the cycle, end value Vs_e, the 3rd transconductance circuit Gm3 is converted into the 3rd current signal by the voltage difference of the end value Vs_e of the initial value Vs_s of Real-time Obtaining and Real-time Obtaining, the 3rd current signal charges to the 3rd building-out capacitor C3, at the 3rd building-out capacitor C3 two ends, obtain the 3rd building-out capacitor voltage signal V3, the 3rd building-out capacitor voltage signal V3 is converted into to the second low frequency signal fL2 of frequency lower than the audio frequency lower limit through voltage controlled oscillator 700, wherein the frequency of the second low frequency signal fL2 can be determined by the setting parameter of voltage controlled oscillator 700.
Step S602: according to the second default clock signal clk 2, the pulse number of counting second low frequency signal fL2 within the cycle of the second low frequency signal fL2, output the second low frequency count pulse f_lm2.
In the present embodiment, as the signal of the present embodiment, can be, but not limited to determine the time range at the second low frequency signal fL2 cycle place according to the voltage difference of voltage initial value Vs_s, the end value Vs_e of the output feedback signal of Real-Time Monitoring.Be this step specifically, the 3rd counter 703 is according to the pulse number of second default clock signal counting the second low frequency signal fL2, export the second low frequency count pulse f_lm2, until the voltage difference of the current output feedback signal initial value Vs_s that obtains and end value Vs_e is while being zero, the counting counting again that makes zero.
Step S603: compare the second low frequency count pulse f_lm2 and the second low frequency signal fL2, output the 7th comparison signal f7.
On circuit is realized, can be, but not limited to ground shown in Figure 7, to in-phase input end, the inverting input of the 8th comparator C OMP8, input respectively the second low frequency signal fL2, the second low frequency count pulse f_lm2 respectively, the level signal of output comparative result, be designated as the 7th comparison signal f7.
Step S604: according to the second above-mentioned default clock signal clk 2, the pulse number of counting the second high-frequency signal fH2, output the second high-frequency count pulse f_hm2.
On circuit is realized, can be, but not limited to ground shown in Figure 7, by four-counter 704 under the driving of the second default clock signal clk 2, according to the pulse number of frequency counting the second high-frequency signal fH2 of CLK2, output the second high-frequency count pulse f_hm2.
Step S605: compare the second high-frequency count pulse f_hm2 and the second high-frequency signal fH2, output the 8th comparison signal f8.
On circuit is realized, can be, but not limited to ground shown in Figure 7, to in-phase input end, the inverting input of the 9th comparator C OMP9, input respectively the second high-frequency signal fH2, the second high-frequency count pulse f_hm2 respectively, the level signal of output comparative result, be designated as the 8th comparison signal f8.
Step S606: according to the 7th comparison signal f7, the 8th comparison signal f8, generate the 5th level signal fd5.
On circuit is realized, can be, but not limited to ground shown in Figure 7, to set end " S ", the reset terminal " R " of the 5th trigger 705, input respectively respectively: the 7th comparison signal f7, the 8th comparison signal f8, at output " Q " output the 5th level signal fd5 of the 5th trigger 705.
Step S607: according to the 5th level signal fd5 and the second default high-frequency signal f_h2, generate the first high-frequency driving signal f_Hq.
On circuit is realized, can be, but not limited to ground shown in Figure 7, with above-mentioned stagnant around-France, penalty method, low frequency frequency variation method in like manner, in the present embodiment, can be, but not limited to first input end, the second input to the 4th AND circuit 706 and input respectively above-mentioned second electrical level signal fd2, frequency the second default high-frequency signal f_h2 greater than the audio frequency upper limit, the 4th AND circuit 706, according to second electrical level signal fd2 and the second default high-frequency signal f_h2, is exported the first high-frequency driving signal f_Hq of this frequency higher than the audio frequency upper limit at output.
Above-described execution mode, do not form the restriction to this technical scheme protection range.The modification of doing within any spirit at above-mentioned execution mode and principle, be equal to and replace and improvement etc., within all should being included in the protection range of this technical scheme.

Claims (25)

1. a noise cancellation method, is characterized in that, comprising:
The output voltage signal of sampled power level circuit, obtain current output feedback signal;
According to current described output feedback signal, determine that current the first driving signal frequency that inputs to described power stage circuit is whether in the scope of audio frequency, if so:
Cut off described power stage circuit and be connected with the described first circuit that drives signal,
To described power stage circuit output the first low frequency drive signal, the first high-frequency driving signal, the frequency of wherein said the first low frequency drive signal is lower than described audio frequency lower limit, and the frequency of described the first high-frequency driving signal is higher than the described audio frequency upper limit.
2. noise cancellation method according to claim 1, is characterized in that,
To described power stage circuit output the first low frequency drive signal, comprising:
More current described output feedback signal and low frequency reference ramp voltage, output frequency is lower than the first level signal of described audio frequency lower limit, and described low frequency reference ramp voltage is predefined for: the output feedback voltage fiducial value when the frequency of the driving signal of described power stage circuit during for the predeterminated frequency lower than described audio frequency lower limit;
According to described the first level signal and the first default clock signal, generate described the first low frequency drive signal.
3. noise cancellation method according to claim 2, is characterized in that,
According to described the first level signal and the first default clock signal, generate described the first low frequency drive signal, comprising:
To described first level signal of reset terminal input of the first trigger,
To the default clock signal of set end input described first of described the first trigger,
Described the first trigger is under the triggering of described the first level signal, the first default clock signal, in described the first low frequency drive signal of output output.
4. noise cancellation method according to claim 3, is characterized in that,
The predetermined frequency of the described first default clock signal is the described audio frequency upper limit.
5. the arbitrary described noise cancellation method of according to claim 1 to 4, is characterized in that,
To described power stage circuit output the first high-frequency driving signal, comprising:
More current described output feedback signal and the first low frequency output feedback lower limit, output the first comparison signal,
Under described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is the first low frequency, the output feedback voltage lower limit within the cycle of a described driving signal;
More current described output feedback signal and the first low frequency output feedback upper limit, output the second comparison signal,
On described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is described the first low frequency, the output feedback voltage higher limit within the cycle of a described driving signal;
According to described the first comparison signal, the second comparison signal, generate the second electrical level signal;
According to described second electrical level signal and the second default high-frequency signal, generate described the first high-frequency driving signal,
The frequency of the described second default high-frequency signal is greater than the described audio frequency upper limit.
6. noise cancellation method according to claim 5, is characterized in that,
According to described the first comparison signal, the second comparison signal, generate the second electrical level signal, comprising:
Described the first comparison signal of set end input to the second trigger;
Described the second comparison signal of reset terminal input to described the second trigger;
Described the second trigger is under the triggering of described the first comparison signal, the second comparison signal, at the described second electrical level signal of output output.
7. noise cancellation method according to claim 5, is characterized in that,
According to described second electrical level signal and the second default high-frequency signal, generate described the first high-frequency driving signal, specifically:
To first input end, second input of AND circuit, input respectively described second electrical level signal and the second default high-frequency signal,
Described AND circuit is according to described second electrical level signal, the second default high-frequency signal, at described the first high-frequency driving signal of output output.
8. the arbitrary described noise cancellation method of according to claim 1 to 4, is characterized in that,
To described power stage circuit output the first high-frequency driving signal, comprising:
More current described output feedback signal and the first low frequency output feedback lower limit, output the 3rd comparison signal,
Under described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is the first low frequency, the output feedback voltage lower limit within the cycle of a described driving signal;
According to described the 3rd comparison signal, generate and output output feedback upper limit floating voltage signal, described output feedback upper limit floating voltage signal is greater than described the first low frequency output feedback lower limit;
More current described output feedback signal and described output feedback upper limit floating voltage signal, output the 4th comparison signal,
According to described the 3rd comparison signal, the 4th comparison signal, generate three level signal;
According to described three level signal and the second default high-frequency signal, generate described the first high-frequency driving signal,
The frequency of the described second default high-frequency signal is greater than the described audio frequency upper limit.
9. noise cancellation method according to claim 8, is characterized in that,
According to described the 3rd comparison signal, generate and output output feedback upper limit floating voltage signal, comprising:
The level signal of described the 3rd comparison signal is converted to the first voltage signal,
According to the voltage difference of described the first voltage signal and output voltage lower limit preset value, generate the first current signal,
Described output voltage lower limit preset value is greater than described the first low frequency output feedback lower limit;
Described the first current signal charges to the first building-out capacitor, and the charging voltage signal of described the first building-out capacitor is described output feedback upper limit floating voltage signal.
10. noise cancellation method according to claim 8, is characterized in that,
According to described the 3rd comparison signal, the 4th comparison signal, generate three level signal, comprising:
Described the 3rd comparison signal of set end input to the 3rd trigger;
Described the 4th comparison signal of reset terminal input to described the 3rd trigger;
Described the 3rd trigger is under the triggering of described the 3rd comparison signal, the 4th comparison signal, at the described three level signal of output output.
11. noise cancellation method according to claim 8, is characterized in that,
According to described three level signal and the second default high-frequency signal, generate described the first high-frequency driving signal, specifically:
To first input end, second input of AND circuit, input respectively described three level signal and the second default high-frequency signal,
Described AND circuit is according to described three level signal and the second default high-frequency signal, at described the first high-frequency driving signal of output output.
12. the arbitrary described noise cancellation method of according to claim 1 to 4, is characterized in that,
To described power stage circuit output the first high-frequency driving signal, comprising:
The current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the first low-frequency cycle, the voltage difference of described initial value and described end value is converted into to the second current signal, described the second current signal charges to the second building-out capacitor, at described the second building-out capacitor two ends, obtain the second building-out capacitor voltage signal, described the second building-out capacitor voltage signal is converted into to the first high-frequency signal through voltage controlled oscillator
The frequency of wherein said the first low frequency is lower than described audio frequency lower limit, and the frequency of described the first high frequency is higher than the described audio frequency upper limit,
According to the pulse number of the second default clock signal counting described first high-frequency signal within described first low-frequency cycle, output the first high-frequency count pulse;
More described the first high-frequency count pulse and described the first high-frequency signal, output the 5th comparison signal;
According to the pulse number of the described second default clock signal counting described first low frequency signal within described first low-frequency cycle, output the first low frequency count pulse;
More described the first low frequency count pulse and described the first low frequency signal, output the 6th comparison signal;
According to described the 5th comparison signal, the 6th comparison signal, generate the 4th level signal;
According to described the 4th level signal and the second default high-frequency signal, generate described the first high-frequency driving signal,
The frequency of the described second default high-frequency signal is greater than the described audio frequency upper limit.
13. noise cancellation method according to claim 12, is characterized in that,
According to the pulse number of the second default clock signal counting described first high-frequency signal within described first low-frequency cycle, output the first high-frequency count pulse, specifically:
According to the pulse number of described the first high-frequency signal of the described second default clock signal counting, export described the first high-frequency count pulse, until the voltage difference of described initial value and described end value is while being zero, counting makes zero counts again.
14. noise cancellation method according to claim 12, is characterized in that,
According to described the 5th comparison signal, the 6th comparison signal, generate the 4th level signal, comprising:
Described the 5th comparison signal of reset terminal input to the 4th trigger;
Described the 6th comparison signal of set end input to described the 4th trigger;
Described the 4th level signal of output output at described the 4th trigger.
15. the arbitrary described noise cancellation method of according to claim 1 to 4, is characterized in that,
To described power stage circuit output the first high-frequency driving signal, comprising:
The current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the second low-frequency cycle, the voltage difference of described initial value and described end value is converted into to the 3rd current signal, described the 3rd current signal charges to the 3rd building-out capacitor, at described the 3rd building-out capacitor two ends, obtain the 3rd building-out capacitor voltage signal, described the 3rd building-out capacitor voltage signal is converted into to the second low frequency signal through voltage controlled oscillator, and the frequency of wherein said the second low frequency is lower than described audio frequency lower limit;
According to the pulse number of the second default clock signal counting described second low frequency signal within described second low-frequency cycle, output the second low frequency count pulse;
More described the second low frequency count pulse and described the second low frequency signal, output the 7th comparison signal;
According to the pulse number of the described second default clock signal counting described second high-frequency signal within described second low-frequency cycle, output the second high-frequency count pulse;
More described the second high-frequency count pulse and described the second high-frequency signal, output the 8th comparison signal;
According to described the 7th comparison signal, the 8th comparison signal, generate the 5th level signal;
According to described the 5th level signal and the second default high-frequency signal, generate described the first high-frequency driving signal,
The frequency of the described second default high-frequency signal is greater than the described audio frequency upper limit.
16. noise cancellation method according to claim 15, is characterized in that,
According to the pulse number of the second default clock signal counting described second low frequency signal within described second low-frequency cycle, specifically:
According to the pulse number of described the second low frequency signal of the described second default clock signal counting, export described the second low frequency count pulse, until the voltage difference of described initial value and described end value is while being zero, counting makes zero counts again.
17. noise cancellation method according to claim 15, is characterized in that,
According to described the 7th comparison signal, the 8th comparison signal, generate the 5th level signal, comprising:
Described the 7th comparison signal of set end input to the 5th trigger;
Described the 8th comparison signal of reset terminal input to described the 5th trigger;
Described the 5th level signal of output output at described the 5th trigger.
18. the arbitrary described noise cancellation method of according to claim 1 to 4, is characterized in that,
According to current described output feedback signal, determine that current the first driving signal frequency that inputs to described power stage circuit whether in the scope of audio frequency, comprising:
Current described output feedback signal and the voltage difference of the first reference voltage signal of setting according to described output feedback signal are converted to the 4th current signal,
Described the 4th current signal charges to the 4th building-out capacitor, on described the 4th building-out capacitor, obtains described output feedback error signal,
More described output feedback error signal and audio threshold voltage, determine that according to comparative result current the first driving signal frequency that inputs to described power stage circuit is whether in the scope of audio frequency,
Described audio threshold voltage is set as current described the first driving signal frequency and enters the reference voltage of the output feedback error signal of described audiorange critical moment,
If described output feedback error signal greater than described audio threshold voltage, judges that current the first driving signal frequency that inputs to described power stage circuit is in the scope of audio frequency, otherwise,
Judge that current the first driving signal frequency of described power stage circuit that inputs to is not in the scope of audio frequency.
19. a noise canceller circuit, is characterized in that, comprising:
The sampling feedback circuit, for the output voltage signal of sampled power level circuit, obtain current output feedback signal;
Testing circuit, be connected with the output of described sampling feedback circuit, for determining that according to current described output feedback signal current the first driving signal frequency that inputs to described power stage circuit is whether in the scope of audio frequency;
Audio-frequency noise is eliminated circuit, with described testing circuit, is connected, and described audio-frequency noise is eliminated circuit and comprised:
Switch switching circuit, in determining the current scope of the first driving signal frequency at audio frequency that inputs to described power stage circuit the time, cuts off described power stage circuit and is connected with the circuit of described the first driving signal,
The low frequency driving input circuit, for when in the definite current scope of the first driving signal frequency at audio frequency that inputs to described power stage circuit, to described power stage circuit output the first low frequency drive signal, the frequency of described the first low frequency drive signal is lower than described audio frequency lower limit
The high-frequency drive input circuit, for when in the definite current scope of the first driving signal frequency at audio frequency that inputs to described power stage circuit, to described power stage circuit output the first high-frequency driving signal, the frequency of described the first high-frequency driving signal is higher than the described audio frequency upper limit.
20. a kind of noise canceller circuit according to claim 19, is characterized in that,
Described low frequency driving input circuit comprises:
The first comparator, be connected with described sampling feedback circuit, and for relatively exporting feedback error signal and low frequency reference ramp voltage, output frequency is lower than the first level signal of described audio frequency lower limit,
Described low frequency reference ramp voltage is predefined for: the output feedback voltage fiducial value when the frequency of the driving signal of described power stage circuit during for the predeterminated frequency lower than described audio frequency lower limit;
The first trigger, described first level signal of reset terminal access of described the first trigger, the set termination enters the first default clock signal, and described the first trigger is under the triggering in described the first level signal, the first default clock signal, in described the first low frequency drive signal of output output.
21. according to claim 19 or 20 described a kind of noise canceller circuits, is characterized in that,
Described high-frequency drive input circuit comprises:
The second comparator, be connected with described sampling feedback circuit, for more current described output feedback signal and the first low frequency output feedback lower limit, and output the first comparison signal,
Under described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is the first low frequency, the output feedback voltage lower limit within the cycle of a described driving signal;
The 3rd comparator, be connected with described sampling feedback circuit, for more current described output feedback signal and the first low frequency output feedback upper limit, and output the second comparison signal,
On described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is described the first low frequency, the output feedback voltage higher limit within the cycle of a described driving signal;
The second trigger, the set termination of described the second trigger enters described the first comparison signal, described the second comparison signal of reset terminal access, described the second trigger are under the triggering of described the first comparison signal, the second comparison signal, at the described second electrical level signal of output output;
The first AND circuit, the first input end of described AND circuit, the second input access respectively described second electrical level signal, higher than second of the described audio frequency upper limit, preset high-frequency signal, described AND circuit, for according to described second electrical level signal and the second default high-frequency signal, is exported described the first high-frequency driving signal at output.
22. according to claim 19 or 20 described a kind of noise canceller circuits, is characterized in that,
Described high-frequency drive input circuit comprises:
The 4th comparator, be connected with described sampling feedback circuit, for more described output signal and the first low frequency output feedback lower limit, and output the 3rd comparison signal,
Under described the first low frequency output feedback, be limited to: when the frequency of the driving signal of described power stage circuit is the first low frequency, the output feedback voltage lower limit within the cycle of a described driving signal;
The RC filter circuit, be connected with the output of described the 4th comparator, for the level signal by described the 3rd comparison signal, is converted to the first voltage signal,
The first mutual conductance amplifying circuit, with described RC filter circuit, be connected, for the voltage difference according to described the first voltage signal and output voltage lower limit preset value, generate the first current signal, described the first current signal charges to the first building-out capacitor, at described the first building-out capacitor two ends, obtain output feedback upper limit floating voltage signal, described output voltage lower limit preset value is greater than described the first low frequency output feedback lower limit;
The 5th comparator, be connected respectively with the output of described sampling feedback circuit, mutual conductance amplifying circuit, for more current described output feedback signal and described output feedback upper limit floating voltage signal, and output the 4th comparison signal,
The 3rd trigger, the set termination of described the 3rd trigger enters described the 3rd comparison signal, described the 4th comparison signal of reset terminal access, described the 3rd trigger are under the triggering of described the 3rd comparison signal, the 4th comparison signal, at output output three level signal;
The second AND circuit, the first input end of described AND circuit, the second input access respectively described three level signal and the second default high-frequency signal, described AND circuit, for according to described three level signal and the second default high-frequency signal, is exported described the first high-frequency driving signal at output;
The frequency of the described second default high-frequency signal is higher than the described audio frequency upper limit.
23. according to claim 19 or 20 described a kind of noise canceller circuits, is characterized in that,
Described high-frequency drive input circuit comprises:
The second mutual conductance amplifying circuit, with described sampling feedback circuit, be connected, be used for according to the current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the first low-frequency cycle, the voltage difference of described initial value and described end value is converted into to the second current signal, described the second current signal charges to the second building-out capacitor, at described the second building-out capacitor two ends, obtains the second building-out capacitor voltage signal
The first oscillating circuit, with the output of described mutual conductance amplifying circuit, be connected, for described the second building-out capacitor voltage signal is converted into to the first high-frequency signal through voltage controlled oscillator, the frequency of wherein said the first low frequency is lower than described audio frequency lower limit, and the frequency of described the first high frequency is higher than the described audio frequency upper limit;
The first counter, be connected with the output of described oscillating circuit, for the pulse number according to the second default clock signal counting described first high-frequency signal within described first low-frequency cycle, output the first high-frequency count pulse;
The 6th comparator, be connected with the output of described the first counter, for more described the first high-frequency count pulse and described the first high-frequency signal, and output the 5th comparison signal;
The second counter, for the pulse number according to the described second default clock signal counting described first low frequency signal within described first low-frequency cycle, output the first low frequency count pulse;
The 7th comparator, be connected with the output of described the second counter, for more described the first low frequency count pulse and described the first low frequency signal, and output the 6th comparison signal;
The 4th trigger, the reset terminal of described the 4th trigger, set end are connected with the output of described the 6th comparator, the 7th comparator respectively, under the triggering at described the 5th comparison signal, the 6th comparison signal, in output output the 4th level signal;
The 3rd AND circuit, the first input end of described the 3rd AND circuit, the second input access respectively described the 4th level signal and the second default high-frequency signal, described the 3rd AND circuit, for according to described the 4th level signal and the second default high-frequency signal, is exported described the first high-frequency driving signal at output.
24. according to claim 19 or 20 described a kind of noise canceller circuits, is characterized in that,
Described high-frequency drive input circuit comprises:
The 3rd mutual conductance amplifying circuit, with described sampling feedback circuit, be connected, be used for according to the current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the second low-frequency cycle, the voltage difference of described initial value and described end value is converted into to the 3rd current signal, described the 3rd current signal charges to the 3rd building-out capacitor, at described the 3rd building-out capacitor two ends, obtains the 3rd building-out capacitor voltage signal
The second oscillating circuit, be connected with the output of described mutual conductance amplifying circuit, and for described the 3rd building-out capacitor voltage signal is converted into to described the second low frequency signal through voltage controlled oscillator, the frequency of wherein said the second low frequency signal is lower than described audio frequency lower limit;
The 3rd counter, be connected with the output of described oscillating circuit, for according to the second default clock signal, counts the pulse number of described the second low frequency signal within described second low-frequency cycle, output the second low frequency count pulse;
The 8th comparator, be connected with the output of described the 3rd counter, for more described the second low frequency count pulse and described the second low frequency signal, and output the 7th comparison signal;
Four-counter, for according to the described second default clock signal, count the pulse number of described the second high-frequency signal, output the second high-frequency count pulse, and the frequency of wherein said the second high frequency is higher than the described audio frequency upper limit;
The 9th comparator, be connected with the output of described four-counter, for more described the second high-frequency count pulse and described the second high-frequency signal, and output the 8th comparison signal;
The 5th trigger, the set end of described the 5th trigger, reset terminal are connected with the output of described the 8th comparator, the 9th comparator respectively, under the triggering at described the 7th comparison signal, the 8th comparison signal, in output output the 5th level signal;
The 4th AND circuit, the first input end of described AND circuit, the second input access respectively described the 5th level signal and the second default high-frequency signal, described AND circuit, for according to described the 5th level signal and the second default high-frequency signal, is exported described the first high-frequency driving signal at output.
25. according to claim 19 or 20 described a kind of noise canceller circuits, is characterized in that,
Described testing circuit comprises:
Error amplifying circuit, with described sampling feedback circuit, be connected, for current output feedback signal and the voltage difference of the first reference voltage signal of setting according to described output feedback signal are converted to the 4th current signal, described the 4th current signal charges to the 4th building-out capacitor, on described the 4th building-out capacitor, obtain described output feedback error signal
The tenth comparator, with the output of described error amplifying circuit, be connected, for more described output feedback error signal and audio threshold voltage, to described audio-frequency noise, eliminate the Enable Pin output enable control signal of circuit, if described output feedback error signal is greater than described audio threshold voltage, to described audio-frequency noise, eliminate the Enable Pin output enable control signal of circuit, to drive described audio-frequency noise, eliminate circuit working
Described audio threshold voltage is set as current described the first driving signal frequency and enters the reference voltage of the output feedback error signal of described audiorange critical moment.
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