CN103401404B

CN103401404B - Noise cancellation method and noise canceller circuit

Info

Publication number: CN103401404B
Application number: CN201310330899.9A
Authority: CN
Inventors: 曹何金生; 余峰
Original assignee: Hangzhou Silergy Semiconductor Technology Ltd
Current assignee: Hangzhou Silergy Semiconductor Technology Ltd
Priority date: 2013-07-31
Filing date: 2013-07-31
Publication date: 2015-10-14
Anticipated expiration: 2033-07-31
Also published as: CN103401404A

Abstract

The present invention relates to electronic applications, disclose a kind of noise cancellation method and noise canceller circuit.Method, comprising: the output voltage signal of sampled power level circuit, obtains current output feedback signal; Current the first driving signal frequency inputing to described power stage circuit is determined whether in the scope of audio frequency according to current described output feedback signal, if, then: cut off described power stage circuit and be connected with the circuit of described first drive singal, the first low frequency drive signal, the first high-frequency driving signal is exported to described power stage circuit, the frequency of wherein said first low frequency drive signal is lower than described audio frequency lower limit, and the frequency of described first high-frequency driving signal is higher than described upper audio limit.Apply this technical scheme to be conducive to reducing circuit noise and avoiding circuit loss.

Description

Noise cancellation method and noise canceller circuit

Technical field

The present invention relates to electronic applications, particularly relate to a kind of noise cancellation method and noise canceller circuit.

Background technology

Power supply is generally made up of power stage circuit and control circuit, and when power stage circuit is in underloading operating state, the output feedback signal of the sign output voltage that control circuit detects can reduce.In control circuit, generally can set one for characterizing the threshold value of load light condition, when the size of output feedback signal is lower than this threshold value, power stage circuit enters underloading operating state and burst mode.Now, control circuit can intermittently work, and the frequency namely inputing to the drive singal of power stage circuit reduces, and lightens along with load, and the frequency of drive singal also can reduce.

In circuit, when the frequency of drive singal is low to when entering audiorange (namely the earshot of people's ear is about 20Hz-20kHz), circuit produces audio-frequency noise.

In order to reduce audio-frequency noise, the mode that prior art generally makes load increase by increasing by a dummy load improves the frequency of the drive singal inputing to power stage circuit, to avoid driving frequency to drop in audiorange, namely avoids the appearance of circuit audio noise.

But carrying out in research process of the present invention, inventor finds prior art, and at least there are the following problems:

The technical scheme of prior art, for adopting the mode and stress release treatment that increase dummy load, the application of this technical scheme can cause circuit loss to increase.

Summary of the invention

One of embodiment of the present invention object is: provide a kind of noise cancellation method, applies this technical scheme and is conducive to reducing circuit noise and avoiding circuit loss.

Two of embodiment of the present invention object is: provide a kind of noise canceller circuit, applies this technical scheme and is conducive to reducing circuit noise and avoiding circuit loss.

A kind of noise cancellation method that the embodiment of the present invention provides, comprising:

The output voltage signal of sampled power level circuit, obtains current output feedback signal;

Current the first driving signal frequency inputing to described power stage circuit is determined whether in the scope of audio frequency according to current described output feedback signal, if so, then:

Cut off described power stage circuit to be connected with the circuit of described first drive singal,

Export the first low frequency drive signal and the first high-frequency driving signal to described power stage circuit, the frequency of wherein said first low frequency drive signal is lower than audio frequency lower limit, and the frequency of described first high-frequency driving signal is higher than upper audio limit.

Alternatively, export the first low frequency drive signal to described power stage circuit, comprising:

More current described output feedback signal and lower frequency reference ramp voltage, output frequency is lower than the first level signal of described audio frequency lower limit, and described lower frequency reference ramp voltage is predefined for: the output feedack voltage reference value when the frequency of the drive singal of described power stage circuit is the predeterminated frequency lower than described audio frequency lower limit;

Preset clock signal according to described first level signal and first, generate described first low frequency drive signal.

Alternatively, preset clock signal according to described first level signal and first, generate described first low frequency drive signal, comprising:

To described first level signal of reset terminal input of the first trigger,

Clock signal is preset in set end input described first to described first trigger,

Described first trigger, under described first level signal, first presets the triggering of clock signal, exports described first low frequency drive signal at output.

Alternatively, the described first predetermined frequency presetting clock signal is described upper audio limit.

Alternatively, export the first high-frequency driving signal to described power stage circuit, comprising:

More current described output feedback signal and the first low frequency output feedack lower limit, export the first comparison signal,

Described first low frequency output feedack lower limit is: when the frequency of the drive singal of described power stage circuit is the first low frequency, the output feedack voltage lower limit value within the cycle of drive singal described in;

More current described output feedback signal and the first low frequency output feedack upper limit, export the second comparison signal,

The described first low frequency output feedack upper limit is: when the frequency of the drive singal of described power stage circuit is described first low frequency, the output feedack upper voltage limit value within the cycle of drive singal described in;

According to described first comparison signal, the second comparison signal, generate second electrical level signal;

Preset high-frequency signal according to described second electrical level signal and second, generate described first high-frequency driving signal,

Described second frequency presetting high-frequency signal is greater than described upper audio limit.

Alternatively, according to described first comparison signal, the second comparison signal, generate second electrical level signal, comprising:

To described first comparison signal of set end input of the second trigger;

To described second comparison signal of reset terminal input of described second trigger;

Described second trigger, under the triggering of described first comparison signal, the second comparison signal, exports described second electrical level signal at output.

Alternatively, preset high-frequency signal according to described second electrical level signal and second, generate described first high-frequency driving signal, specifically:

Input described second electrical level signal and second respectively preset high-frequency signal to the first input end of AND circuit, the second input,

Described AND circuit presets high-frequency signal according to described second electrical level signal, second, exports described first high-frequency driving signal at output.

More current described output feedback signal and the first low frequency output feedack lower limit, export the 3rd comparison signal,

According to described 3rd comparison signal, generate and export output feedack upper limit floating voltage signal, described output feedack upper limit floating voltage signal is greater than described first low frequency output feedack lower limit;

More current described output feedback signal and described output feedack upper limit floating voltage signal, export the 4th comparison signal,

According to described 3rd comparison signal, the 4th comparison signal, generate three level signal;

Preset high-frequency signal according to described three level signal and second, generate described first high-frequency driving signal,

Alternatively, according to described 3rd comparison signal, generate and export output feedack upper limit floating voltage signal, comprising:

The level signal of described 3rd comparison signal is converted to the first voltage signal,

According to the voltage difference of described first voltage signal and output voltage lower limit preset value, generate the first current signal,

Described output voltage lower limit preset value is greater than described first low frequency output feedack lower limit;

Described first current signal charges to the first building-out capacitor, and the charging voltage signal of described first building-out capacitor is described output feedack upper limit floating voltage signal.

Alternatively, according to described 3rd comparison signal, the 4th comparison signal, generate three level signal, comprising:

To described 3rd comparison signal of set end input of the 3rd trigger;

To described 4th comparison signal of reset terminal input of described 3rd trigger;

Described 3rd trigger, under the triggering of described 3rd comparison signal, the 4th comparison signal, exports described three level signal at output.

Alternatively, preset high-frequency signal according to described three level signal and second, generate described first high-frequency driving signal, specifically:

Input described three level signal and second respectively preset high-frequency signal to the first input end of AND circuit, the second input,

Described AND circuit presets high-frequency signal according to described three level signal and second, exports described first high-frequency driving signal at output.

The current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the first low-frequency cycle, the voltage difference of described initial value and described end value is converted into the second current signal, described second current signal charges to the second building-out capacitor, the second building-out capacitor voltage signal is obtained at described second building-out capacitor two ends, described second building-out capacitor voltage signal is converted into the first high-frequency signal through voltage controlled oscillator

The frequency of wherein said first low frequency lower than described audio frequency lower limit, the frequency of described first high frequency higher than described upper audio limit,

Preset the pulse number of clock signal counting described first high-frequency signal within the first low-frequency cycle described in one according to second, export the first high-frequency count pulse;

More described first high-frequency count pulse and described first high-frequency signal, export the 5th comparison signal;

Preset the pulse number of clock signal counting first low frequency signal within the first low-frequency cycle described in one according to described second, export the first low frequency count pulse;

More described first low frequency count pulse and described first low frequency signal, export the 6th comparison signal;

According to described 5th comparison signal, the 6th comparison signal, generate the 4th level signal;

Preset high-frequency signal according to described 4th level signal and second, generate described first high-frequency driving signal,

Alternatively, preset the pulse number of clock signal counting described first high-frequency signal within the first low-frequency cycle described in one according to second, export the first high-frequency count pulse, specifically:

Preset the pulse number of described first high-frequency signal of clock signal counting according to described second, export described first high-frequency count pulse, until when the voltage difference of described initial value and described end value is zero, counting zero counts again.

According to described 5th comparison signal, the 6th comparison signal, generate the 4th level signal, comprising:

To described 5th comparison signal of reset terminal input of the 4th trigger;

To described 6th comparison signal of set end input of described 4th trigger;

Described 4th level signal is exported at the output of described 4th trigger.

The current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the second low-frequency cycle, the voltage difference of described initial value and described end value is converted into the 3rd current signal, described 3rd current signal charges to the 3rd building-out capacitor, the 3rd building-out capacitor voltage signal is obtained at described 3rd building-out capacitor two ends, described 3rd building-out capacitor voltage signal is converted into the second low frequency signal through voltage controlled oscillator, and the frequency of wherein said second low frequency is lower than described audio frequency lower limit;

Preset the pulse number of clock signal counting described second low frequency signal within the second low-frequency cycle described in one according to second, export the second low frequency count pulse;

More described second low frequency count pulse and described second low frequency signal, export the 7th comparison signal;

Preset the pulse number of clock signal counting second high-frequency signal within the second low-frequency cycle described in one according to described second, export the second high-frequency count pulse;

More described second high-frequency count pulse and described second high-frequency signal, export the 8th comparison signal;

According to described 7th comparison signal, the 8th comparison signal, generate the 5th level signal;

Preset high-frequency signal according to described 5th level signal and second, generate described first high-frequency driving signal,

Alternatively, preset the pulse number of clock signal counting described second low frequency signal within the second low-frequency cycle described in one according to second, specifically:

Preset the pulse number of described second low frequency signal of clock signal counting according to described second, export described second low frequency count pulse, until when the voltage difference of described initial value and described end value is zero, counting zero counts again.

Alternatively, according to described 7th comparison signal, the 8th comparison signal, generate the 5th level signal, comprising:

To described 7th comparison signal of set end input of the 5th trigger;

To described 8th comparison signal of reset terminal input of described 5th trigger;

Described 5th level signal is exported at the output of described 5th trigger.

Alternatively, determine current the first driving signal frequency inputing to described power stage circuit whether in the scope of audio frequency according to current described output feedback signal, comprising:

Current output feedback signal and the voltage difference of the first reference voltage signal set according to described output feedback signal are converted to the 4th current signal,

Described 4th current signal charges to the 4th building-out capacitor, and described 4th building-out capacitor obtains output feedack error signal,

More described output feedack error signal and audio threshold voltage, determine current the first driving signal frequency inputing to described power stage circuit whether in the scope of audio frequency according to comparative result,

Described audio threshold voltage sets is the reference voltage that current described first driving signal frequency enters the output feedack error signal of the scope critical moment of described audio frequency,

If described output feedack error signal is greater than described audio threshold voltage, then judge that current the first driving signal frequency inputing to described power stage circuit is in the scope of audio frequency, otherwise,

Judge that current the first driving signal frequency inputing to described power stage circuit is not in the scope of audio frequency.

A kind of noise canceller circuit that the embodiment of the present invention provides, comprising:

Sampling feedback circuit, for the output voltage signal of sampled power level circuit, obtains current output feedback signal;

Testing circuit, is connected with the output of described sampling feedback circuit, for determining current the first driving signal frequency inputing to described power stage circuit according to current described output feedback signal whether in the scope of audio frequency;

Audio-frequency noise eliminates circuit, is connected with described testing circuit, and described audio-frequency noise is eliminated circuit and comprised:

Switch switching circuit, for when determining that current the first driving signal frequency inputing to described power stage circuit is in the scope of audio frequency, cutting off described power stage circuit and being connected with the circuit of described first drive singal,

Low frequency driving input circuit, for when determining that current the first driving signal frequency inputing to described power stage circuit is in the scope of audio frequency, export the first low frequency drive signal to described power stage circuit, the frequency of described first low frequency drive signal is lower than audio frequency lower limit, and

High-frequency drive input circuit, for when determining that current the first driving signal frequency inputing to described power stage circuit is in the scope of audio frequency, export the first high-frequency driving signal to described power stage circuit, the frequency of described first high-frequency driving signal is higher than upper audio limit.

Alternatively, described low frequency driving input circuit comprises:

First comparator, is connected with described sampling feedback circuit, for comparing output feedack error signal and lower frequency reference ramp voltage, output frequency lower than the first level signal of described audio frequency lower limit,

Described lower frequency reference ramp voltage is predefined for: the output feedack voltage reference value when the frequency of the drive singal of described power stage circuit is the predeterminated frequency lower than described audio frequency lower limit;

First trigger, described first level signal of reset terminal access of described first trigger, set termination enters first and presets clock signal, and described first trigger is used for, under described first level signal, first presets the triggering of clock signal, exporting described first low frequency drive signal at output.

Alternatively, described high-frequency drive input circuit comprises:

Second comparator, is connected with described sampling feedback circuit, for more current described output feedback signal and the first low frequency output feedack lower limit, exports the first comparison signal,

3rd comparator, is connected with described sampling feedback circuit, for more current described output feedback signal and the first low frequency output feedack upper limit, exports the second comparison signal,

Second trigger, the set termination of described second trigger enters described first comparison signal, described second comparison signal of reset terminal access, described second trigger is used under the triggering of described first comparison signal, the second comparison signal, exports second electrical level signal at output;

First AND circuit, the first input end of described first AND circuit, the second input access described second electrical level signal respectively, preset high-frequency signal higher than second of described upper audio limit, described first AND circuit is used for presetting high-frequency signal according to described second electrical level signal and second, exports described first high-frequency driving signal at output.

Alternatively, described high-frequency drive input circuit comprises:

4th comparator, is connected with described sampling feedback circuit, for more described output feedback signal and the first low frequency output feedack lower limit, exports the 3rd comparison signal,

RC filter circuit, is connected with the output of described 4th comparator, for the level signal of described 3rd comparison signal is converted to the first voltage signal,

First mutual conductance amplifying circuit, be connected with described RC filter circuit, for the voltage difference according to described first voltage signal and output voltage lower limit preset value, generate the first current signal, described first current signal charges to the first building-out capacitor, obtain output feedack upper limit floating voltage signal at described first building-out capacitor two ends, described output voltage lower limit preset value is greater than described first low frequency output feedack lower limit;

5th comparator, is connected respectively with the output of described sampling feedback circuit, the first mutual conductance amplifying circuit, for more current described output feedback signal and described output feedack upper limit floating voltage signal, exports the 4th comparison signal,

3rd trigger, the set termination of described 3rd trigger enters described 3rd comparison signal, described 4th comparison signal of reset terminal access, described 3rd trigger is used under the triggering of described 3rd comparison signal, the 4th comparison signal, exports three level signal at output;

Second AND circuit, the first input end of described second AND circuit, the second input access described three level signal and second respectively and preset high-frequency signal, described second AND circuit is used for presetting high-frequency signal according to described three level signal and second, exports described first high-frequency driving signal at output;

Described second presets the frequency of high-frequency signal higher than described upper audio limit.

Alternatively, described high-frequency drive input circuit comprises:

Second mutual conductance amplifying circuit, be connected with described sampling feedback circuit, for according to the current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the first low-frequency cycle, the voltage difference of described initial value and described end value is converted into the second current signal, described second current signal charges to the second building-out capacitor, obtains the second building-out capacitor voltage signal at described second building-out capacitor two ends

First oscillating circuit, be connected with the output of described mutual conductance amplifying circuit, for described second building-out capacitor voltage signal is converted into the first high-frequency signal through voltage controlled oscillator, the frequency of wherein said first low frequency is lower than described audio frequency lower limit, and the frequency of described first high frequency is higher than described upper audio limit;

First counter, is connected with the output of described first oscillating circuit, for presetting the pulse number of clock signal counting described first high-frequency signal within the first low-frequency cycle described in one according to second, exports the first high-frequency count pulse;

6th comparator, is connected with the output of described first counter, for more described first high-frequency count pulse and described first high-frequency signal, exports the 5th comparison signal;

Second counter, for presetting the pulse number of clock signal counting first low frequency signal within the first low-frequency cycle described in one according to described second, exports the first low frequency count pulse;

7th comparator, is connected with the output of described second counter, for more described first low frequency count pulse and described first low frequency signal, exports the 6th comparison signal;

4th trigger, reset terminal, the set end of described 4th trigger are connected with the output of described 6th comparator, the 7th comparator respectively, under the triggering of described 5th comparison signal, the 6th comparison signal, export the 4th level signal at output;

3rd AND circuit, the first input end of described 3rd AND circuit, the second input access described 4th level signal and second respectively and preset high-frequency signal, described 3rd AND circuit is used for presetting high-frequency signal according to described 4th level signal and second, exports described first high-frequency driving signal at output.

Alternatively, described high-frequency drive input circuit comprises:

3rd mutual conductance amplifying circuit, be connected with described sampling feedback circuit, for according to the current described output feedback signal of Real-Time Monitoring, obtain initial value, the end value of the sampled voltage within the second low-frequency cycle, the voltage difference of described initial value and described end value is converted into the 3rd current signal, described 3rd current signal charges to the 3rd building-out capacitor, obtains the 3rd building-out capacitor voltage signal at described 3rd building-out capacitor two ends

Second oscillating circuit, is connected with the output of described mutual conductance amplifying circuit, and for described 3rd building-out capacitor voltage signal is converted into described second low frequency signal through voltage controlled oscillator, the frequency of wherein said second low frequency signal is lower than described audio frequency lower limit;

3rd counter, is connected with the output of described oscillating circuit, for presetting clock signal according to second, counting the pulse number of described second low frequency signal within the second low-frequency cycle described in one, exporting the second low frequency count pulse;

8th comparator, is connected with the output of described 3rd counter, for more described second low frequency count pulse and described second low frequency signal, exports the 7th comparison signal;

Four-counter, for presetting clock signal according to described second, count the pulse number of the second high-frequency signal, export the second high-frequency count pulse, the frequency of wherein said second high frequency is higher than described upper audio limit;

9th comparator, is connected with the output of described four-counter, for more described second high-frequency count pulse and described second high-frequency signal, exports the 8th comparison signal;

5th trigger, set end, the reset terminal of described 5th trigger are connected with the output of described 8th comparator, the 9th comparator respectively, under the triggering of described 7th comparison signal, the 8th comparison signal, export the 5th level signal at output;

4th AND circuit, the first input end of described 4th AND circuit, the second input access described 5th level signal and second respectively and preset high-frequency signal, described 4th AND circuit is used for presetting high-frequency signal according to described 5th level signal and second, exports described first high-frequency driving signal at output.

Alternatively, described testing circuit comprises:

Error amplifying circuit, be connected with described sampling feedback circuit, for current output feedback signal and the voltage difference of the first reference voltage signal set according to described output feedback signal are converted to the 4th current signal, described 4th current signal charges to the 4th building-out capacitor, described 4th building-out capacitor obtains output feedack error signal

Tenth comparator, be connected with the output of described error amplifying circuit, for more described output feedack error signal and audio threshold voltage, the Enable Pin output enable control signal of circuit is eliminated to described audio-frequency noise, if described output feedack error signal is greater than described audio threshold voltage, then eliminate the Enable Pin output enable control signal of circuit to described audio-frequency noise, eliminate circuit working to drive described audio-frequency noise

Described audio threshold voltage sets is the reference voltage that current described first driving signal frequency enters the output feedack error signal of the scope critical moment of described audio frequency.

Therefore, application the present embodiment technical scheme, can be determined by the Real-Time Monitoring of output feedack voltage that whether the current frequency inputing to the drive singal of power stage circuit is in audiorange, once it enters in audiorange, then cut off the input of this drive singal in audiorange (being designated as the first drive singal), replace to power stage circuit input not in the low frequency drive signal of audiorange, high-frequency driving signal, by this low frequency drive signal, the common combination of high-frequency driving signal, and simulate former first drive singal to the driving of power stage circuit and input, the driving of power stage circuit produces and inputs substantially constant effect with former driving.And because the frequency of the drive singal that now inputs to power stage circuit is not all in audiorange, therefore can not audio-frequency noise be produced on circuit, be conducive to eliminating circuit audio noise.

Relative to the technical scheme that prior art improves driving signal frequency by adding dummy load and avoids audio-frequency noise to produce, adopt the present embodiment technical scheme, without the need to increasing dummy load, without the need to increasing the loss of circuit.

Accompanying drawing explanation

Accompanying drawing described herein is used to provide a further understanding of the present invention, forms a application's part, does not form inappropriate limitation of the present invention, in the accompanying drawings:

The noise cancellation method schematic flow sheet that Fig. 1 provides for the embodiment of the present invention 1;

The noise canceller circuit theory structure schematic diagram that Fig. 2 provides for embodiment of the present invention 1-6;

The first low frequency drive signal input circuit theory structure schematic diagram that Fig. 3 provides for the embodiment of the present invention 2;

The employing that Fig. 4 provides for the embodiment of the present invention 3 is stagnant around-Francely realizes the first high-frequency driving signal input circuit theory structure schematic diagram;

Fig. 5 realizes the first high-frequency driving signal input circuit theory structure schematic diagram for the employing penalty method that the embodiment of the present invention 4 provides;

Fig. 6 realizes the first high-frequency driving signal input circuit theory structure schematic diagram for the employing high frequency frequency variation method that the embodiment of the present invention 5 provides;

Fig. 7 realizes the first high-frequency driving signal input circuit theory structure schematic diagram for the employing low frequency frequency variation method that the embodiment of the present invention 6 provides;

Fig. 8 is the output feedback signal waveform schematic diagram of prior art first drive singal when entering audiorange;

Fig. 9 is when the first drive singal enters audiorange, the output feedback signal waveform schematic diagram that the technical scheme that application embodiment of the present invention 1-6 provides obtains.

Embodiment

Describe the present invention in detail below in conjunction with accompanying drawing and specific embodiment, be used for explaining the present invention in this illustrative examples of the present invention and explanation, but not as a limitation of the invention.

Embodiment 1:

Shown in Figure 1, present embodiments provide a kind of noise cancellation method, the method mainly comprises the following steps:

Step S101: the output voltage signal of sampled power level circuit, obtains current output feedback signal.

Pass through sampling feedback circuit 202 sampling and outputting voltage signal at the output of power stage circuit, obtain current output feedback signal by sampling feedback circuit 202, this output feedback signal changes with current output voltage signal intensity.For example:

Be connected to power stage circuit output by electric resistance partial pressure sample circuit as sampling feedback circuit 202 in Fig. 2, obtain output feedback signal Vs, this output feedback signal Vs and the proportional relation of output voltage signal Vo, Vs=Vo*R2/ (R1+R2).

Step S102: determine current the first driving signal frequency inputing to power stage circuit whether in the scope of audio frequency according to current output feedback signal.

In circuit, when power stage circuit is in underloading operating state, input to the corresponding reduction of frequency of the drive singal of power stage circuit, output feedback signal can corresponding reduction.Therefore the frequency range of the drive singal inputing to power stage circuit can be judged in practice by the real-time change of detection output feedback signal.

In circuit, when the frequency of the drive singal inputing to power stage circuit enters audiorange, circuit can produce audio-frequency noise.And the Real-Time Monitoring of output feedback signal can be utilized in the present embodiment and monitor and determine whether the current frequency inputing to the drive singal of power stage circuit falls into audiorange, and carry out corresponding audio-frequency noise elimination, inhibitory control process.

The frequency range that audiorange behaviour ear described in the present embodiment can be heard, is generally set as 20Hz to 20kHz.

In the present embodiment, the former external drive signal inputing to power stage circuit is designated as f_q1.

Shown in Figure 2, determine the current f_q1 frequency inputing to power stage circuit 201 whether in the scope of audio frequency according to current described output feedback signal, can be, but not limited to realize by the following technical solutions.

Can be, but not limited to adopt error amplifying circuit 203 that the voltage difference of current output feedback signal Vs and the first reference voltage signal Vref1 (its reference signal preset according to Vs) is converted to the 4th current signal, 4th current signal charges to the 4th building-out capacitor C4, and the 4th building-out capacitor C4 obtains output feedack error signal Vc.

Then output feedack error signal Vc is inputed to the tenth comparator COMP10, tenth comparator COMP10 compares output feedack error signal Vc and audio threshold voltage Vc-th compares, now can according to the Output rusults of the tenth comparator COMP10, determine the current f_q1 frequency inputing to power stage circuit whether in the scope of audio frequency: if output feedack error signal Vc is less than audio threshold voltage Vc-th, then determine that the current f_q1 frequency inputing to power stage circuit is not in the scope of audio frequency, disable control signal is exported to noise canceller circuit 204, noise canceller circuit 204 does not carry out work, perform the process of step S106, , otherwise the current f_q1 frequency inputing to described power stage circuit is in the scope of audio frequency, and to noise canceller circuit 204 output enable control signal, noise canceller circuit 204 works under this enable control signal controls, and performs the process of step S104-S105.

Wherein, audio threshold voltage Vc-th is people according to the threshold limit value preset during circuit actual motion, is specially: current f_q1 frequency enters the reference voltage of the output feedack error signal of described audiorange critical moment.

Step S103: if the first driving signal frequency inputing to power stage circuit is in the scope of audio frequency, then perform step S104, otherwise redirect performs step S106.

If the frequency of former f_q1 is when audiorange, then perform step S104, otherwise, conventionally perform, continue to input this f_q1 to this power stage circuit, realize power drive.

Step S104: rupturing duty level circuit is connected with the circuit of described first drive singal.

In this step, cut off ongoing frequency and input to the driving of power stage circuit at the f_q1 of audiorange, and the low-and high-frequency drive singal driving switching to the present embodiment inputs.

Shown in Figure 2, switch switching circuit can be arranged between the low-and high-frequency drive singal of power stage circuit 201 and f_q1, the present embodiment to work to make the switching tube Qb of power stage circuit, for when the f_q1 frequency inputing to power stage circuit 201 is in the scope of audio frequency, cut off ongoing frequency input to the driving of power stage circuit 201 at the f_q1 of audiorange, and the low-and high-frequency drive singal driving switching to the present embodiment inputs.

Step S105: export the first low frequency drive signal f_Lq, the first high-frequency driving signal f_Hq to power stage circuit.

To power stage circuit output frequency lower than the first low frequency drive signal f_Lq of audio frequency lower limit and frequency the first high-frequency driving signal f_Hq higher than upper audio limit.

The further input circuit about the first low frequency signal, the first high-frequency signal specifically can be, but not limited to the detailed description that vide infra, and also can conventionally generate and input in the power stage circuit of the present embodiment.

Step S106: the driving input keeping f_q1.

In the present embodiment, this audio frequency lower limit set is 20Hz, and upper audio limit is set as 20kHz.

Therefore, application the present embodiment technical scheme, can be determined by the Real-Time Monitoring of output feedack voltage that whether the current frequency inputing to the drive singal of power stage circuit is in audiorange, once it enters in audiorange, then cut off the input of this drive singal in audiorange (being designated as f_q1), replace to power stage circuit input not in the low frequency drive signal of audiorange, high-frequency driving signal, by this low frequency drive signal, the common combination of high-frequency driving signal, and simulate former f_q1 to the driving of power stage circuit and input, the driving of power stage circuit produces and inputs substantially constant effect with former driving.And because the frequency of the drive singal that now inputs to power stage circuit is not all in audiorange, therefore can not audio-frequency noise be produced on circuit, be conducive to eliminating circuit audio noise.

Shown in Fig. 8,9, visible, adopt the present embodiment technical scheme without the need to increasing dummy load, without the need to increasing on the basis of the loss of circuit, the frequency of drive singal can be changed and realize inputting substantially constant effect with former driving.

Embodiment 2:

The present embodiment and embodiment 1 difference are only:

As the signal of the present embodiment, can be, but not limited to obtain by the following technical solutions as the first low frequency drive signal f_Lq lower than audio frequency lower limit inputing to power stage circuit, it mainly comprises the following steps:

Step S1051: compare output feedack error signal and lower frequency reference ramp voltage, output frequency is lower than the first level signal of audio frequency lower limit.

In the present embodiment lower frequency reference ramp voltage can be predefined for: the output feedack voltage when the frequency of the drive singal of power stage circuit is the predeterminated frequency lower than audio frequency lower limit, is designated as Vramp.When for example to can be, but not limited to driving frequency be 10Hz, corresponding output voltage signal is set as lower frequency reference ramp voltage Vramp, and wherein, Vramp is a ramp voltage.

In this step, can be, but not limited to employing first comparator COMP1 and compare output feedack error signal Vc and lower frequency reference ramp voltage Vramp, thus export the level signal of a frequency lower than audio frequency lower limit at output, be designated as the first level signal, because the first level signal is relevant to output feedack error signal, and output feedack error signal is relevant to the output voltage signal of power stage circuit, therefore the first level signal obtained is relevant to the output voltage signal of power stage circuit, the characteristic of the output voltage signal of current power level circuit can be reflected.

In the present embodiment, can also but be not limited to before relatively output feedack error signal and lower frequency reference ramp voltage, adopt error amplifying circuit 203 that the voltage difference of current output feedback signal Vs and the first reference voltage signal Vref1 (its reference signal preset according to Vs) is converted to the 4th current signal as shown in Figure 2, 4th current signal charges to the 4th building-out capacitor C4, 4th building-out capacitor C4 obtains output feedack error signal Vc, then as shown in Figure 3, the lower frequency reference ramp voltage Vramp corresponding to this signal to the output feedack error signal Vc after error amplification by the first comparator COMP1 compares, obtain the first above-mentioned level signal.

Step S1052: preset clock signal according to the first level signal, first, generate the first low frequency drive signal f_Lq.

In the present embodiment this first preset clock signal clk 1 for by user according to preset during circuit actual motion, frequency is not more than the clock signal of upper audio limit.Can be, but not limited in the present embodiment set it to the clock signal that frequency is clock upper limit 20kHz, can also but be not limited to set it to the clock signal that frequency is 18kHZ.

This step does not preset clock signal clk 1 higher than first of upper audio limit according to frequency lower than the first level signal of audio frequency lower limit and frequency, generate the first low frequency drive signal f_Lq of audio frequency lower than audio frequency lower limit, output it to power stage circuit, jointly to drive this power stage circuit with the first high-frequency driving signal f_Hq.

Can be, but not limited to adopt trigger at the present embodiment, be designated as the first trigger 301 and generate this first low frequency drive signal f_Lq, specifically shown in Figure 3.

Reset terminal " R " to the first trigger 301 inputs the first level signal d1, set end " S " to the first trigger 301 inputs first and presets clock signal clk 1, first trigger 301, under the first level signal d1, first presets the triggering of clock signal clk 1, exports described first low frequency drive signal f_Lq at output " Q ".When set end " S " is high level " 1 ", when reset terminal " R " is for low level " 0 ", the output " Q " of the first trigger 301 exports high level " 1 "; When set end " S " is low level " 0 ", when reset terminal " R " is for high level " 1 ", output " Q " output low level " 0 " of the first trigger 301; Other input states, then the output " Q " of the first trigger 301 keeps former output state.

Embodiment 3:

The present embodiment and embodiment 1 difference are only:

As the signal of the present embodiment, can be, but not limited to adopt stagnant around-France realization as the first high-frequency driving signal f_Hq higher than upper audio limit inputing to power stage circuit.Mainly comprise the following steps according to stagnant around-France acquisition first high-frequency driving signal f_Hq technical scheme:

Step S301: compare current output feedback signal and the first low frequency output feedack lower limit, export the first comparison signal f1.

Wherein, the first low frequency output feedack lower limit is predetermined to be and can characterizes output feedback signal minimum value.

First low frequency output feedack lower limit can but do not limit and be set to: when the frequency of the drive singal of power stage circuit is the first low frequency lower than audio frequency, the output feedack voltage lower limit value within the cycle of a drive singal.

First low frequency output feedack lower limit can also but be not limited to be set to: the mean value adding up acquisition according at least two frequencies lower than the output feedback signal lower limit of the drive singal of audio frequency lower limit.

Relatively current output feedback signal, the first low frequency output feedack lower limit, exports the level signal of comparative result, is designated as the first comparison signal f1.

Step S302: compare current output feedback signal and the first low frequency output feedack upper limit, export the second comparison signal f2,

Wherein, the first low frequency output feedack upper limit is predetermined to be and can characterizes output feedback signal maximum.

The first low frequency output feedack upper limit can but do not limit and be set to: when the frequency of the drive singal of power stage circuit is above-mentioned first low frequency, the output feedack upper voltage limit value within the cycle of a drive singal.

The first low frequency output feedack upper limit can also but be not limited to be set to: the mean value adding up acquisition according at least two frequencies lower than the output feedback signal higher limit of the drive singal of audio frequency lower limit.

Relatively current output feedback signal, the first low frequency output feedack upper limit, exports the level signal of comparative result, is designated as the second comparison signal f2.

Step S303: according to the first comparison signal f1, the second comparison signal f2, generates second electrical level signal fd2.

In the present embodiment, by comparing current output feedback signal and the first low frequency output feedack lower limit and the size comparing current output feedback signal and the first low frequency output feedack upper limit respectively, and determine the state at current output feedback signal place, to export the level signal meeting current power level circuit working state according to comparative result, be designated as second electrical level signal fd2, to generate the first high-frequency driving signal f_Hq further according to this second electrical level signal fd2.

Step S304: preset high-frequency signal f_h2 according to second electrical level signal fd2 and second, generate the first high-frequency driving signal f_Hq.

In the present embodiment, can be, but not limited to AND circuit first input end, the second input inputs above-mentioned second electrical level signal fd2 respectively, frequency is greater than upper audio limit second presets high-frequency signal f_h2, AND circuit presets high-frequency signal f_h2 according to second electrical level signal fd2 and second, exports the first high-frequency driving signal f_Hq of this frequency higher than upper audio limit at output.

Stagnant around-France circuit is implemented technical scheme and be can be, but not limited to shown in Figure 4, such as:

Can be, but not limited to input respectively at the in-phase input end of the second comparator COMP2, inverting input: the first low frequency output feedack lower limit (being designated as Vs_L), current output feedback signal Vs, the output of the second comparator COMP2 exports this first comparison signal f1 to the set end " S " of the second trigger 402.

Input current output feedback signal Vs, the first low frequency output feedack upper limit (being designated as Vs-H) respectively at the in-phase input end of the 3rd comparator COMP3, inverting input, the output of the 3rd comparator COMP3 exports this second comparison signal f2 to the reset terminal " R " of the second trigger 402.Second trigger 402 is under the triggering of the first comparison signal f1, the second comparison signal f2, second electrical level signal fd2 is exported at output " Q ", the first input end of the first AND circuit 401 receives second electrical level signal fd2, second input of the first AND circuit 401 receives second and presets high-frequency signal f_h2, first AND circuit 401 pairs second electrical level signal fd2, second presets high-frequency signal f_h2 and carries out and computing, obtains the first above-mentioned high-frequency driving signal f_Hq.

In Fig. 4 circuit, if Vs<Vs_L, the current underfrequency inputing to the f_q1 of power stage circuit can be determined, fall into audiorange, the signal that the set end " S " then now inputing to the second trigger 402 is held is high level " 1 ", the signal that the reset terminal " R " inputing to the second trigger 402 is held is low level " 0 ", and the second electrical level signal that now output " Q " of the second trigger 402 exports is high level " 1 ".

If Vs>Vs_H, can determine that the current frequency inputing to the f_q1 of power stage circuit is higher and higher than upper audio limit, set end " S " end then now inputing to the second trigger 402 is low level " 0 ", reset terminal " R " end inputing to the second trigger 402 is high level " 1 ", and the second electrical level signal that now output " Q " of the second trigger 402 exports is low level " 0 ".

If Vs_L<Vs<Vs_H, can determine that the current frequency inputing to the f_q1 of power stage circuit is lower, but can not determine whether it fall into audiorange, the signal that the set end " S " then now inputing to the second trigger 402 is held is low level " 0 ", the signal that the reset terminal " R " inputing to the second trigger 402 is held is low level " 0 ", the second electrical level signal that now output " Q " of the second trigger 402 exports is remained stationary state, namely identical with the state in a upper moment.

Embodiment 4:

The present embodiment and embodiment 1 difference are only:

As the signal of the present embodiment, can be, but not limited to adopt penalty method to realize as the first high-frequency driving signal f_Hq higher than upper audio limit inputing to power stage circuit.Obtain the first high-frequency driving signal f_Hq technical scheme according to penalty method mainly to comprise the following steps:

Step S401: compare current output feedback signal and the first low frequency output feedack lower limit, exports the 3rd comparison signal f3.

With above-mentioned steps S301 in like manner, the first low frequency output feedack lower limit in this penalty method is predetermined to be and can characterizes output feedback signal minimum value.First low frequency output feedack lower limit can but do not limit and be set to: when the frequency of the drive singal of power stage circuit is the first low frequency lower than audio frequency, the output feedack voltage lower limit value within the cycle of a drive singal.

Can be, but not limited to compare current output feedback signal and the first low frequency output feedack lower limit by the 4th comparator, export the level signal of comparative result, be designated as the 3rd comparison signal f3.

Step S402: according to the 3rd comparison signal f3, generates output feedack upper limit floating voltage signal.

In the present embodiment, because the 3rd comparison signal f3 is relevant to current output feedback signal, therefore it can reflect state and the characteristic of current output feedback signal.In the present embodiment, according to the 3rd comparison signal f3, generate and export the output feedack upper limit floating voltage signal that is greater than the first low frequency output feedack lower limit, be designated as Vs-H2, then this output feedack upper limit floating voltage signal Vs-H2 can be used as the parameter characterizing output feedback signal maximum.

In the present embodiment, change because output feedack upper limit floating voltage signal Vs-H2 follows the tracks of the change of current output feedback signal, therefore apply its to noise eliminate control more to reflect the current state inputing to the drive singal of power stage circuit, make its suppression to circuit audio noise, eliminate the more realistic circuit state of control, make control more accurate.

Step S403: compare current output feedback signal and output feedack upper limit floating voltage signal, exports the 4th comparison signal f4.

Relatively current output feedback signal and output feedack upper limit floating voltage signal, exports the level signal of comparative result, is designated as the 4th comparison signal f4.

Step S404: according to the 3rd comparison signal f3, the 4th comparison signal f4, generate three level signal fd3.

In the present embodiment, by comparing current output feedback signal and the first low frequency output feedack lower limit respectively, and compare the size of current output feedback signal and output feedack upper limit floating voltage signal, and determine the state at current output feedback signal place, to export the level signal meeting current power level circuit working state according to comparative result, be designated as three level signal fd3, to generate the first high-frequency driving signal f_Hq further according to this three level signal fd3.

Step S405: preset high-frequency signal f_h2 according to three level signal fd3 and second, generate the first high-frequency driving signal f_Hq.

With step S304 in like manner, the present embodiment second preset high-frequency signal f_h2 be the frequency signal that frequency is greater than upper audio limit.

In the present embodiment, can be, but not limited to the second AND circuit 502 first input end, the second input inputs above-mentioned three level signal fd3 respectively, frequency is greater than upper audio limit second presets high-frequency signal f_h2, AND circuit presets high-frequency signal f_h2 according to three level signal fd3 and second, exports the first high-frequency driving signal f_Hq of this frequency higher than upper audio limit at output.

The circuit of penalty method is implemented technical scheme and be can be, but not limited to shown in Figure 5:

Can be, but not limited to input the first low frequency output feedack lower limit (being designated as Vs_L), current output feedback signal Vs respectively at the in-phase input end of the 4th comparator COMP4, inverting input, the output of the 4th comparator COMP4 exports the level signal of comparative result to the set end " S " of the 3rd trigger 503, is designated as the 3rd comparison signal f3.

And the 3rd comparison signal f3 is passed through by filter resistance Rf, and the RC filter circuit 501 that filter capacitor Cf forms, 3rd comparison signal f3 is converted to voltage signal, be designated as V1, this voltage signal V1 is inputed to the first mutual conductance amplifying circuit Gm1, voltage signal V1 and the voltage difference being used for the reference signal Vref2 (i.e. output voltage lower limit preset value) characterizing output voltage minimum value are converted into current signal by the first mutual conductance amplifying circuit Gm1, be designated as the first current signal, first current signal charges to the first building-out capacitor C1, obtain output feedack upper limit floating voltage signal Vs-H2.

Input current output feedback signal Vs respectively at the in-phase input end of the 5th comparator COMP5, inverting input, the output of output feedack upper limit floating voltage signal Vs-H2, the 5th comparator COMP5 exports comparative result level signal to the reset terminal " R " of the 3rd trigger 503: the 4th comparison signal f4.3rd trigger 503 is under the triggering of the 3rd comparison signal f3, the 4th comparison signal f4, three level signal fd3 is exported to the first input end of the second AND circuit 502 at output " Q ", second AND circuit 502 to three level signal fd3, higher than described upper audio limit second preset high-frequency signal f_h2 carry out and computing, obtain the first above-mentioned high-frequency driving signal f_Hq.

With Fig. 4 in like manner, in Figure 5, if Vs<Vs-L, the current underfrequency inputing to the f_q1 of power stage circuit can be determined, fall into audiorange, the signal that the set end " S " then now inputing to the 3rd trigger 503 is held is high level " 1 ", and the signal that the reset terminal " R " inputing to the 3rd trigger 503 is held is low level " 0 ", and the three level signal fd3 that now output " Q " of the 3rd trigger 503 exports is high level " 1 ".

If Vs>Vs-H2, can determine that the current frequency inputing to the f_q1 of power stage circuit is higher and higher than upper audio limit, the signal that the set end " S " then now inputing to the 3rd trigger 503 is held is low level " 0 ", the signal that the reset terminal " R " inputing to the 3rd trigger 503 is held is high level " 1 ", and the three level signal fd3 that now output " Q " of the 3rd trigger 503 exports is low level " 0 ".

If Vs-L<Vs<Vs-H2, can determine that the current frequency inputing to the f_q1 of power stage circuit is lower, but can not determine whether it fall into audiorange, the signal that the set end " S " then now inputing to the 3rd trigger 503 is held is low level " 0 ", the signal that the reset terminal " R " inputing to the 3rd trigger 503 is held is low level " 0 ", the three level signal fd3 that now output " Q " of the 3rd trigger 503 exports remains stationary state, namely identical with the state in a upper moment.

Embodiment 5:

The present embodiment and embodiment 1 difference are only:

As the signal of the present embodiment, can be, but not limited to adopt high frequency frequency variation method to realize as the first low frequency drive signal f_Hq higher than upper audio limit inputing to power stage circuit.Obtain the first high-frequency driving signal f_Hq technical scheme according to high frequency frequency variation method mainly to comprise the following steps:

Step S501: Real-Time Monitoring current output feedback signal, obtain the voltage initial value Vs_s at the first low frequency (the being designated as fL1) output feedback signal in the cycle lower than audio frequency lower limit preset, end value Vs_e, the voltage difference of the initial value Vs_s of Real-time Obtaining and the end value Vs_e of Real-time Obtaining is converted into the second current signal by the second transconductance circuit Gm2, second current signal charges to the second building-out capacitor C2, the second building-out capacitor voltage signal V2 is obtained at the second building-out capacitor C2 two ends, second building-out capacitor voltage signal V2 is converted into the first high-frequency signal fH1 of frequency higher than described upper audio limit through voltage controlled oscillator 600, wherein the frequency of the first high-frequency signal fH1 can be determined by the setting parameter of voltage controlled oscillator 600.

Step S502: preset clock signal clk 2 according to second, count the pulse number of the first high-frequency signal fH1 within the first low frequency signal fL1 cycle, export the first high-frequency count pulse f_hm1.

In the present embodiment, as the signal of the present embodiment, can be, but not limited to the voltage initial value Vs_s of the output feedback signal according to Real-Time Monitoring, the voltage difference of end value Vs_e and determine the time range at fL1 cycle place, namely this step specifically, the pulse number that clock signal clk 2 counts the first high-frequency signal fH1 is preset according to second, export the first high-frequency count pulse f_hm1, until when the output feedback signal initial value Vs_s of current acquisition and the voltage difference of end value Vs_e are zero, counting zero counts again.

On circuit realiration, can be, but not limited to shown in Figure 6ly, under presetting the driving of clock signal clk 2 by the first counter 601 second, calculate the pulse number of the first high-frequency signal fH1, export the first high-frequency count pulse f_hm1.

Step S503: compare the first high-frequency count pulse f_hm1 and the first high-frequency signal fH1, exports the 5th comparison signal f5.

On circuit realiration, can be, but not limited to shown in Figure 6ly, input the first high-frequency signal fH1, the first high-frequency count pulse f_hm1 respectively respectively to the in-phase input end of the 6th comparator COMP6, inverting input, export the level signal of comparative result, be designated as the 5th comparison signal f5.

Step S504: preset clock signal clk 2 according to above-mentioned second, count the pulse number of the first low frequency signal fL1 within the first low frequency signal fL1 cycle, export the first low frequency count pulse f_lm1.

On circuit realiration, can be, but not limited to shown in Figure 6ly, under presetting the driving of clock signal clk 2 by the second counter 602 second, according to the pulse number of the frequency counting first low frequency signal fL1 of CLK2, export the first low frequency count pulse f_lm1.

Step S505: compare the first low frequency count pulse f_lm1 and the first low frequency signal fL1, exports the 6th comparison signal f6.

On circuit realiration, can be, but not limited to shown in Figure 6ly, input the first low frequency signal fL1, the first low frequency count pulse f_lm1 respectively respectively to the in-phase input end of the 7th comparator COMP7, inverting input, export the level signal of comparative result, be designated as the 6th comparison signal f6.

Step S506: according to the 5th comparison signal f5, the 6th comparison signal f6, generates the 4th level signal fd4.

On circuit realiration, can be, but not limited to shown in Figure 6ly, input respectively respectively to the reset terminal " R " of the 4th trigger 604, set end " S ": the 5th comparison signal f5, the 6th comparison signal f6, export the 4th level signal fd4 at the output " Q " of the 4th trigger 604.

Step S507: preset high-frequency signal f_h2 according to the 4th level signal fd4 and second, generate described first high-frequency driving signal f_Hq.

On circuit realiration, can be, but not limited to shown in Figure 6ly, with above-mentioned stagnant around-France, penalty method in like manner, in the present embodiment, can be, but not limited to the 3rd AND circuit 603 first input end, the second input inputs above-mentioned second electrical level signal fd2 respectively, frequency is greater than upper audio limit second presets high-frequency signal f_h2,3rd AND circuit 603 presets high-frequency signal f_h2 according to second electrical level signal fd2 and second, exports the first low frequency drive signal f_Hq of this frequency higher than upper audio limit at output.

Embodiment 6

The present embodiment and embodiment 1 difference are only:

As the signal of the present embodiment, can be, but not limited to adopt low frequency frequency variation method to realize as the first low frequency drive signal f_Hq higher than upper audio limit inputing to power stage circuit.Obtain the first high-frequency driving signal f_Hq technical scheme according to low frequency frequency variation method mainly to comprise the following steps:

Step S601: Real-Time Monitoring current output feedback signal, obtain the voltage initial value Vs_s at the second low frequency signal (the being designated as fL2) output feedback signal in the cycle lower than audio frequency lower limit preset, end value Vs_e, the voltage difference of the initial value Vs_s of Real-time Obtaining and the end value Vs_e of Real-time Obtaining is converted into the 3rd current signal by the 3rd transconductance circuit Gm3, 3rd current signal charges to the 3rd building-out capacitor C3, the 3rd building-out capacitor voltage signal V3 is obtained at the 3rd building-out capacitor C3 two ends, 3rd building-out capacitor voltage signal V3 is converted into the second low frequency signal fL2 of frequency lower than audio frequency lower limit through voltage controlled oscillator 700, wherein the frequency of the second low frequency signal fL2 can be determined by the setting parameter of voltage controlled oscillator 700.

Step S602: preset clock signal clk 2 according to second, count the pulse number of the second low frequency signal fL2 within the cycle of the second low frequency signal fL2, export the second low frequency count pulse f_lm2.

In the present embodiment, as the signal of the present embodiment, can be, but not limited to the voltage initial value Vs_s of the output feedback signal according to Real-Time Monitoring, the voltage difference of end value Vs_e and determine the time range at the second low frequency signal fL2 cycle place.Namely this step specifically, 3rd counter 703 presets according to second the pulse number that clock signal counts the second low frequency signal fL2, export the second low frequency count pulse f_lm2, until when the output feedback signal initial value Vs_s of current acquisition and the voltage difference of end value Vs_e are zero, counting zero counts again.

Step S603: compare the second low frequency count pulse f_lm2 and the second low frequency signal fL2, exports the 7th comparison signal f7.

On circuit realiration, can be, but not limited to shown in Figure 7ly, input the second low frequency signal fL2, the second low frequency count pulse f_lm2 respectively respectively to the in-phase input end of the 8th comparator COMP8, inverting input, export the level signal of comparative result, be designated as the 7th comparison signal f7.

Step S604: preset clock signal clk 2 according to above-mentioned second, count the pulse number of the second high-frequency signal fH2, export the second high-frequency count pulse f_hm2.

On circuit realiration, can be, but not limited to shown in Figure 7ly, under presetting the driving of clock signal clk 2 by four-counter 704 second, according to the pulse number of the frequency counting second high-frequency signal fH2 of CLK2, export the second high-frequency count pulse f_hm2.

Step S605: compare the second high-frequency count pulse f_hm2 and the second high-frequency signal fH2, exports the 8th comparison signal f8.

On circuit realiration, can be, but not limited to shown in Figure 7ly, input the second high-frequency signal fH2, the second high-frequency count pulse f_hm2 respectively respectively to the in-phase input end of the 9th comparator COMP9, inverting input, export the level signal of comparative result, be designated as the 8th comparison signal f8.

Step S606: according to the 7th comparison signal f7, the 8th comparison signal f8, generates the 5th level signal fd5.

On circuit realiration, can be, but not limited to shown in Figure 7ly, input respectively respectively to the set end " S " of the 5th trigger 705, reset terminal " R ": the 7th comparison signal f7, the 8th comparison signal f8, export the 5th level signal fd5 at the output " Q " of the 5th trigger 705.

Step S607: preset high-frequency signal f_h2 according to the 5th level signal fd5 and second, generate the first high-frequency driving signal f_Hq.

On circuit realiration, can be, but not limited to shown in Figure 7ly, with above-mentioned stagnant around-France, penalty method, low frequency frequency variation method in like manner, in the present embodiment, can be, but not limited to the 4th AND circuit 706 first input end, the second input inputs above-mentioned second electrical level signal fd2 respectively, frequency is greater than upper audio limit second presets high-frequency signal f_h2,4th AND circuit 706 presets high-frequency signal f_h2 according to second electrical level signal fd2 and second, exports the first high-frequency driving signal f_Hq of this frequency higher than upper audio limit at output.

Above-described execution mode, does not form the restriction to this technical scheme protection range.The amendment done within any spirit at above-mentioned execution mode and principle, equivalently to replace and improvement etc., within the protection range that all should be included in this technical scheme.

Claims

1. a noise cancellation method, is characterized in that, comprising:

2. noise cancellation method according to claim 1, is characterized in that,

Export the first low frequency drive signal to described power stage circuit, comprising:

3. noise cancellation method according to claim 2, is characterized in that,

Preset clock signal according to described first level signal and first, generate described first low frequency drive signal, comprising:

To described first level signal of reset terminal input of the first trigger,

4. noise cancellation method according to claim 3, is characterized in that,

Described first predetermined frequency presetting clock signal is described upper audio limit.

5., according to arbitrary described noise cancellation method of Claims 1-4, it is characterized in that,

Export the first high-frequency driving signal to described power stage circuit, comprising:

6. noise cancellation method according to claim 5, is characterized in that,

According to described first comparison signal, the second comparison signal, generate second electrical level signal, comprising:

To described first comparison signal of set end input of the second trigger;

7. noise cancellation method according to claim 5, is characterized in that,

Preset high-frequency signal according to described second electrical level signal and second, generate described first high-frequency driving signal, specifically:

8., according to arbitrary described noise cancellation method of Claims 1-4, it is characterized in that,

9. noise cancellation method according to claim 8, is characterized in that,

According to described 3rd comparison signal, generate and export output feedack upper limit floating voltage signal, comprising:

10. noise cancellation method according to claim 8, is characterized in that,

According to described 3rd comparison signal, the 4th comparison signal, generate three level signal, comprising:

To described 3rd comparison signal of set end input of the 3rd trigger;

11. noise cancellation methods according to claim 8, is characterized in that,

Preset high-frequency signal according to described three level signal and second, generate described first high-frequency driving signal, specifically:

12., according to the arbitrary described noise cancellation method of Claims 1-4, is characterized in that,

13. noise cancellation methods according to claim 12, is characterized in that,

Preset the pulse number of clock signal counting described first high-frequency signal within the first low-frequency cycle described in one according to second, export the first high-frequency count pulse, specifically:

14. noise cancellation methods according to claim 12, is characterized in that,

To described 5th comparison signal of reset terminal input of the 4th trigger;

To described 6th comparison signal of set end input of described 4th trigger;

Described 4th level signal is exported at the output of described 4th trigger.

15., according to the arbitrary described noise cancellation method of Claims 1-4, is characterized in that,

16. noise cancellation methods according to claim 15, is characterized in that,

The pulse number of clock signal counting described second low frequency signal within the second low-frequency cycle described in one is preset according to second, specifically:

17. noise cancellation methods according to claim 15, is characterized in that,

According to described 7th comparison signal, the 8th comparison signal, generate the 5th level signal, comprising:

To described 7th comparison signal of set end input of the 5th trigger;

Described 5th level signal is exported at the output of described 5th trigger.

18., according to the arbitrary described noise cancellation method of Claims 1-4, is characterized in that,

Determine current the first driving signal frequency inputing to described power stage circuit whether in the scope of audio frequency according to current described output feedback signal, comprising:

Current described output feedback signal and the voltage difference of the first reference voltage signal set according to described output feedback signal are converted to the 4th current signal,

19. 1 kinds of noise canceller circuits, is characterized in that, comprising:

20. a kind of noise canceller circuits according to claim 19, is characterized in that,

Described low frequency driving input circuit comprises:

21. a kind of noise canceller circuits according to claim 19 or 20, is characterized in that,

Described high-frequency drive input circuit comprises:

22. a kind of noise canceller circuits according to claim 19 or 20, is characterized in that,

Described high-frequency drive input circuit comprises:

23. a kind of noise canceller circuits according to claim 19 or 20, is characterized in that,

Described high-frequency drive input circuit comprises:

24. a kind of noise canceller circuits according to claim 19 or 20, is characterized in that,

Described high-frequency drive input circuit comprises:

25. a kind of noise canceller circuits according to claim 19 or 20, is characterized in that,

Described testing circuit comprises: