CN103066827B - Power factor correcting circuit and input feedforward compensating circuit thereof - Google Patents
Power factor correcting circuit and input feedforward compensating circuit thereof Download PDFInfo
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- CN103066827B CN103066827B CN201210591036.2A CN201210591036A CN103066827B CN 103066827 B CN103066827 B CN 103066827B CN 201210591036 A CN201210591036 A CN 201210591036A CN 103066827 B CN103066827 B CN 103066827B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a power factor correcting circuit and an input feedforward compensating circuit thereof. The input feedforward compensating circuit comprises a peak acquisition module, an inverse circuit which is connected with the peak acquisition module and a superposed circuit which is connected with the inverse circuit. The peak acquisition module acquires a peak of an input voltage or reflects signal of the peak of the input voltage. The inverse circuit generates direct current signals which are opposite to the variation trend of the peak of the input voltage. The superposed circuit superposes the direct current signals and output signals of an error-amplifying network in a control circuit of the power factor correcting circuit. The power factor correcting circuit and the input feedforward compensating circuit thereof is capable of superposing change information of the input voltage on the output signals of a regulating ring of the control circuit when the input voltage suddenly changes, and therefore slow loop regulating is avoided, and the problem that larger fluctuations of an output voltage or current are caused by a sudden change of the input voltage is avoided.
Description
Technical field
The present invention relates to switch power technology, particularly relate to a kind of circuit of power factor correction and input feedforward compensation circuit thereof.
Background technology
Owing to there is non-linear element and energy-storage travelling wave tube in current most of power consumption equipment, therefore can make input AC current waveform generation Severe distortion, cause net side input power factor very low.In order to meet the harmonic requirement of international standard IEC61000-3-2, power factor correction (PFC) device must be added in these power consumption equipments.
In order to suppress working frequency ripple wave thus obtain higher power factor, it is lower that the bandwidth of the control loop of conventional P FC circuit is arranged usually, and lower loop bandwidth can cause the dynamic responding speed of pfc circuit slower.For LED driver with high power factor (constant current output), when input voltage has larger fluctuation, the output level Vcomp due to regulation loop changes comparatively slow, makes output current Io have larger overshoot or fall, as shown in Figure 1, thus the LED lamplight that human eye is seen has obvious flicker.
Some pfc circuits with power limitation control function often adopt the method for input voltage feed forward to realize power limitation control, and dynamic response when input voltage changes relatively has some improvement, as shown in Figure 2.Mainly comprise: alternating-current voltage source 201, rectifier bridge 202, power circuit 203, ratio circuit 204, low pass filter 205, ratio circuit 206, ratio circuit 207, PWM device 208, electric current loop 209, multiplier 210, ratio circuit 211, Voltage loop 212.Wherein, power circuit 203 comprises inductance L, diode D, switching tube M and electric capacity C, and electric capacity C is configured to and load R
lin parallel.
But in the control circuit shown in Fig. 2, its input voltage feed forward is realized by the mean value of Gather and input voltage, the low pass filter 205 of the mean value introducing of Gather and input voltage Vin reduces the response speed of loop, therefore, improves limited to the dynamic response of input.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of circuit of power factor correction and input feedforward compensation circuit thereof, can solve the problem that input voltage mutation causes output voltage or electric current larger fluctuation.
For solving the problems of the technologies described above, the invention provides a kind of input feedforward compensation circuit of circuit of power factor correction, comprising:
Peak value acquisition module, the signal of the peak value obtaining input voltage or the peak value reflecting described input voltage;
The negate circuit be connected with described peak value acquisition module, produces the direct current signal contrary with the peak change trend of described input voltage;
The supercircuit be connected with described negate circuit, superposes the output signal that described direct current signal and the error in the control circuit of circuit of power factor correction amplify network.
According to one embodiment of present invention, described input voltage be via rectifier bridge rectification in circuit of power factor correction after voltage signal.
According to one embodiment of present invention, described peak value acquisition module comprises:
Ratio circuit, receives described input voltage and regulates its amplitude;
The peak value acquisition cuicuit be connected with described ratio circuit, obtains the peak value of the input voltage after amplitude adjustment.
According to one embodiment of present invention, described peak value acquisition cuicuit comprises:
Bias voltage source;
Operational amplifier, its positive input terminal connects the output of described ratio circuit;
Comparator, its positive input terminal connects the positive input terminal of described bias voltage source, and its negative input end connects the positive input terminal of described operational amplifier;
Diode, its anode connects the output of described operational amplifier, and its negative electrode connects the negative input end of described operational amplifier;
First electric capacity, its first end connects the negative input end of described operational amplifier, its second end ground connection;
Inverter, its input connects the output of described operational amplifier;
Forward position acquisition cuicuit, its input connects the output of described inverter;
First switch, its first end connects the first end of described first electric capacity, and its second end connects the second end of described second electric capacity, and its control end connects the output of described comparator;
Second switch, its first end connects the positive input terminal of described operational amplifier, and its control end connects the output of described forward position acquisition cuicuit;
Second electric capacity, its first end connects the second end of described second switch, its second end ground connection, and the first end of described second electric capacity is as the output of described peak value acquisition cuicuit.
According to one embodiment of present invention, described forward position acquisition cuicuit adopts RC circuit and logical circuit to realize.
According to one embodiment of present invention, described peak value acquisition cuicuit comprises:
The lowest point time detection circuit, its input connects the output of described ratio circuit, for detecting the lowest point time of described input voltage, produces pulse signal to locate the lowest point time of described input voltage;
Delay circuit, its input connects the output of described the lowest point time detection circuit, carries out time delay to described pulse signal;
Sampling hold circuit, is connected with the output of delay circuit with described ratio circuit, samples under pulse signal after the delay controls to the input voltage after amplitude adjustment;
Scaling circuit, its input is connected with the output of described sampling hold circuit, and its output is as the output of described peak value acquisition cuicuit.
According to one embodiment of present invention, described sampling hold circuit comprises:
3rd switch, its control end connects the output of described delay circuit, and its first end connects the output of described ratio circuit, and its second end connects the input of described scaling circuit;
3rd electric capacity, its first end connects the second end of described 3rd switch, its second end ground connection.
According to one embodiment of present invention, described negate circuit comprises: subtracter, and its positive input terminal receives the direct voltage preset, and its negative input end connects the output of described peak value acquisition module, and its output exports described direct current signal.
According to one embodiment of present invention, described supercircuit comprises: adder, and its first input end connects the output of described negate circuit, and its second input error received in described control circuit amplifies the output signal of network.
Present invention also offers a kind of circuit of power factor correction and comprise input feedforward compensation circuit described in above any one.
Compared with prior art, the present invention has the following advantages:
The input feedforward compensation circuit of the embodiment of the present invention, the electrical quantity of input voltage peak change amount maybe can be embodied by the variable quantity obtaining input voltage peak value, the direct current signal contrary with input voltage peak change trend is obtained after in addition anti-phase, the error this direct current signal being directly superimposed upon control loop amplifies the output of network, thus avoid control loop adjustment process slowly, achieve output voltage or output current ground quick adjustment, when input voltage mutation, output voltage or current fluctuation is less or ripple disable.Especially when output loading is LED, when input voltage fluctuation, LED flicker free problem.
Accompanying drawing explanation
Fig. 1 is the output current of a kind of pfc circuit of the prior art when input voltage is undergone mutation and the dynamic waveform of control ring output;
Fig. 2 is the circuit theory diagrams of a kind of pfc circuit adopting conventional feed forward to control in prior art;
Fig. 3 is the circuit theory diagrams of the input feedforward compensation circuit of the embodiment of the present invention;
Fig. 4 is the working waveform figure of the input feedforward compensation circuit shown in Fig. 3;
Fig. 5 is the circuit diagram of the first specific embodiment of peak value acquisition cuicuit in Fig. 3;
Fig. 6 is the working waveform figure of the peak value acquisition cuicuit shown in Fig. 5;
Fig. 7 is the circuit diagram of the second specific embodiment of peak value acquisition cuicuit in Fig. 3;
Fig. 8 is the working waveform figure of the peak value acquisition cuicuit shown in Fig. 7;
Fig. 9 shows the circuit diagram of the circuit of power factor correction of the embodiment of the present invention;
Figure 10 is the working waveform figure of circuit of power factor correction shown in Fig. 9.
Embodiment
Below in conjunction with specific embodiments and the drawings, the invention will be further described, but should not limit the scope of the invention with this.
The work wave of the input feedforward compensation circuit in Fig. 3 is shown with reference to figure 3 and Fig. 4, Fig. 4.The input feedforward compensation main circuit of the present embodiment will comprise: peak value acquisition module 31, negate circuit 304, supercircuit 305.
Wherein, peak value acquisition module 31 connects the output of the rectifier bridge in circuit of power factor correction, obtains the peak value of input voltage.It will be appreciated by those skilled in the art that peak value acquisition module 31 can also obtain the signal of the peak value of reflection input voltage, or obtain the electrical quantity of reflection input voltage peak change amount.
It should be noted that, " peak value of input voltage " not refers to the voltage signal of the peak point of proper input voltage herein, also comprise the voltage signal of input voltage in the preset range of peak point both sides, the i.e. voltage signal of peak value vicinity, such as, voltage signal within the scope of peak point preset in advance, or the voltage signal in the delayed preset range of peak point.
Negate circuit 304 is connected with peak value acquisition module 31, produces the direct current signal contrary with the peak change trend of input voltage.Supercircuit 305 is connected with negate circuit 304, the output signal Vcomp that the direct current signal exported by negate circuit 304 and the error in the control circuit of circuit of power factor correction amplify network 300 superposes, and the output of this supercircuit 305 can connect rear class control circuit.
Wherein, error amplifies the part that network 300 is control circuits (or control loop) of pfc circuit, it can comprise comparator Ua, reference voltage source Vref and electric capacity C1, the negative input end of comparator Ua receives feedback voltage FB, the positive input terminal of comparator Ua connects the anode of reference voltage source Vref, the positive ending grounding of reference voltage source Vref, the first end of electric capacity C1 connects the output of comparator U, the second end ground connection.
Furthermore, as a nonrestrictive example, peak value acquisition module 31 can comprise ratio circuit 301 and peak value acquisition cuicuit 302.Wherein, ratio circuit 301 receives input voltage | and Vac| also regulates its amplitude.Such as, ratio circuit 301 can by main circuit rectifier bridge export voltage | Vac| carries out scale smaller, to meet the requirement of the voltage magnitude of control circuit.Peak value acquisition cuicuit 302 is connected with ratio circuit 301, obtain amplitude regulate after input voltage peak K × | Vac_pk|.
Negate circuit 304 can adopt subtracter to realize, its positive input terminal receives the direct voltage Vdc preset, its negative input end connects the output of peak value acquisition cuicuit 302, its output output direct current signal Vdc-K × | Vac_pk|, the variation tendency of this direct current signal is contrary with the peak change trend of input voltage.Such as this direct voltage Vdc can be provided by direct voltage source 303, and the anode of DC power supply 303 connects the positive input terminal of subtracter 304, the negativing ending grounding of DC power supply 303.Certainly, it will be appreciated by those skilled in the art that and other suitable circuit can also be adopted to realize negate circuit 304, only need the signal of output contrary with input signal variation tendency.
Supercircuit 305 can adopt adder to realize, its first end connects the output of subtracter 304, second termination receives the output signal Vcomp that error amplifies network 300, its output connects rear class control circuit, export revised error amplification signal Vcomp ', to realize the compensation of the dynamic response to input voltage change.The error amplification signal Vcomp ' revised can be expressed as:
Vcomp'=Vcomp+Vdc-K×|Vac_pk|。
Certainly, it will be appreciated by those skilled in the art that other circuit with overlaying function can be adopted to realize supercircuit 305.
With reference to figure 5, directly obtain the nonrestrictive example of input voltage peak value as one, peak value acquisition cuicuit 302 can comprise: bias voltage source Vbias, operational amplifier Ub, comparator Uc, diode Dx1, the first electric capacity Cx1, inverter Ud, forward position acquisition cuicuit 51, first switch S x1, second switch Sx2, the second electric capacity Cx2.
Ratio circuit 301(Fig. 3) the positive input terminal of output concatenation operation amplifier Ub; The negative electrode of the negative input terminating diode Dx1 of operational amplifier Ub, the first end of the first electric capacity Cx1 and the first end of the first switch S x1, the anode of the output terminating diode Dx1 of operational amplifier Ub, the second end ground connection of the first electric capacity Cx1, the second end ground connection of the first switch S x1; The negative input end of positive termination comparator Uc; The anode of the positive input termination bias voltage source Vbias of comparator Uc, the negativing ending grounding of bias voltage source Vbias, the positive input terminal of the negative input termination operational amplifier Ub of comparator Uc, the control end of the output termination first switch S x1 of comparator Uc; The output of the input termination operational amplifier Ub of inverter Ud, the input of the output termination forward position acquisition cuicuit 51 of inverter Ud, the control end of the output termination second switch Sx2 of forward position acquisition cuicuit 51, the positive input terminal of the first termination operational amplifier Ub of second switch Sx2, the first end of the second termination second electric capacity Cx2 of second switch Sx2, and as the output of peak value acquisition cuicuit 302, the other end ground connection of the second electric capacity Cx2.
Wherein, forward position acquisition cuicuit 52 can adopt RC circuit and logical circuit to realize.
As shown in Figure 6, its main working process is as follows for the work wave of the peak value acquisition cuicuit 302 shown in Fig. 5: operational amplifier Ub and diode Dx1 forms peak-detector circuit, for detecting the peak value of input signal A; Comparator Uc is for generation of reset signal, and within each cycle, the input peak signal B that peak-detector circuit detects in the lowest point of input signal A by the reset signal that comparator Uc produces resets, so that detect the input signal peak value in next cycle; Interval at t0 ~ t1, because input signal A amplitude is monotone increasing, the signal B that the peak-detector circuit that operational amplifier Ub and diode Dx1 is formed exports follows input signal A and changes; In the t1 moment, input signal A reaches peak value, input signal A starts to decline afterwards, the positive input terminal signal of operational amplifier Ub is less than its negative input end signal, operational amplifier Ub plays the effect of comparator, output level produces one by high level to low level saltus step, and this skip signal reflects the peak of input voltage signal A; Therefore only the output signal E of operational amplifier Ub need be carried out anti-phasely obtaining signal F, obtain the control signal G of second switch Sx2 through the forward position that forward position acquisition cuicuit 51 takes out signal F; As seen from Figure 6, the high level forward position of control signal G is consistent with the peak of input voltage signal A, utilize control signal G by a bit of interval of second switch Sx2 conducting, second electric capacity Cx2 obtains the level signal of input signal A peak value, and have no progeny in second switch Sx2 pass, this level signal is kept; Bias voltage source Vbias is the level signal of a setting, for comparing with input signal A, at the lowest point place of input signal A, when input signal A is lower than bias voltage source Vbias amplitude, comparator Uc exports high level and makes the first switch S x1 conducting, the voltage B that first electric capacity Cx1 keeps is discharged into zero, thus achieves the reset to voltage B.
From the course of work of the specific embodiment of above-mentioned peak value acquisition cuicuit 302, the main operational principle of peak value acquisition cuicuit 302 is: operational amplifier Ub, diode Dx1, the first switch S x1 and the first electric capacity Cx1 form front stage circuits, second switch Sx2 and the second electric capacity Cx2 forms late-class circuit, inverter Ud and forward position acquisition cuicuit are used for producing the sampled signal of late-class circuit at input signal peak value place, and comparator Uc is used for producing the reset signal of prime output signal; Front stage circuits obtains the peak value of input signal, and by input signal peak value place switch the peak value of the input signal of acquisition being passed to late-class circuit and keeping, the output signal of front stage circuits is reset afterwards, waits the peak value of input signal next cycle to be obtained.
With reference to figure 7, indirectly obtain the nonrestrictive example of input voltage peak value as one, peak value acquisition cuicuit 302 can comprise: the lowest point time detection circuit 701, delay circuit 702, sampling hold circuit 703 and scaling circuit 704.
Ratio circuit 301(Fig. 3) output connect the input of the lowest point time detection circuit 701, the input of the output termination delay circuit 702 of the lowest point time detection circuit 701, the control end of the 3rd switch S x3 in the output termination sampling hold circuit 703 of delay circuit 702, first termination ratio circuit 301(Fig. 3 of 3rd switch S x3) output, the first end of the 3rd electric capacity Cx3 of the second termination sampling hold circuit 703 of the 3rd switch S x3 and the input of scaling circuit 704, the second end ground connection of the 3rd electric capacity Cx3, the output of scaling circuit 704 is the output of peak value acquisition cuicuit 302.
As shown in Figure 8, its main working process is as follows for the work wave of the peak value acquisition cuicuit 302 shown in Fig. 7:
The lowest point time detection circuit 701 detects the lowest point time of input voltage, and exports a pulse signal H for locating the lowest point time of detected input voltage; The pulse signal H that the lowest point time detection circuit 701 exports by delay circuit 702 carries out angle Td that time delay presets thus obtains the sampled signal I of sampling hold circuit 703, under the control of this sampled signal I, sampling hold circuit 703 is also sampled to the input signal of the 3rd switch S x3 first end.
Assuming that the input signal of the 3rd switch S x3 first end is purer half-sinusoid, the cycle is T, and input peak value is k|Vac_pk|, then can obtain:
VJ=VC·sin(Td/T·π)=k|Vac_pk|·sin(Td/T·π)
Wherein VJ is the voltage magnitude at J place, and VC is the voltage magnitude at C place.If make the multiplication factor K2 of scaling circuit 704 be 1/sin (Td/T π), then the voltage magnitude that can obtain C place is:
VC=VJ·K2=k|Vac_pk|
From above-mentioned analysis, by detecting the voltage magnitude at input voltage waveform special angle place, the peak value of input voltage indirectly can be obtained.
In the embodiment of the acquisition cuicuit of peak value shown in Fig. 7 302, the lowest point time detection circuit 601 compares realization by comparator to the input voltage signal of peak value acquisition cuicuit 302 and the reference voltage of setting, and the analog circuit of other substantial equivalence or digital circuit also can be adopted to realize described function.Delay circuit 602 can adopt function described in the substantial equivalence circuit realiration such as RC time delay or counter.
Certainly; those skilled in the art are known; except the method that above-mentioned two kinds of embodiments characterize, peak value acquisition cuicuit 302 also can adopt the analog circuit of other substantial equivalence or digital circuit to realize above-mentioned functions, and the mode taked and circuit all should be encompassed within protection scope of the present invention.
Fig. 9 shows the circuit of power factor correction of the present embodiment, which employs the input feed forward circuit shown in Fig. 3.This circuit of power factor correction mainly comprises: alternating-current voltage source 201, rectifier bridge 202, power circuit 203, ratio circuit 206, ratio circuit 207, peak value acquisition module (comprising ratio circuit 301 and peak value acquisition cuicuit 302), negate circuit 304, supercircuit 305, error amplification network 300, ratio circuit 211, multiplier 210, electric current loop 209, PWM produce circuit 208.
Wherein, power circuit 203 comprises inductance L, diode D, switching tube M and electric capacity C, and electric capacity C is configured to load LEDs in parallel.Ratio circuit 301 in peak value acquisition module connects the positive output end of rectifier bridge 202, ratio circuit 211 is connected with output current sampling end Io, the output of supercircuit 305 connects the first input end of multiplier 210, the positive output end of the input termination rectifier bridge 202 of ratio circuit 206, second input of the output termination multiplier 210 of ratio circuit 206, the input termination input current sampling end Iin of ratio circuit 207, the first input end of the output termination electric current loop 209 of ratio circuit 207, second input of the output termination electric current loop 209 of multiplier 210, the output termination PWM of electric current loop 209 produces the input of circuit 208, PWM produces the gate pole of the switching tube M in the output termination power circuit 203 of circuit 208.
Compared with the traditional circuit of power factor correction shown in Fig. 2, the output of the feedforward compensation circuit in Fig. 9 directly amplifies network 300 output with error superposes, thus avoid slower loop adjustment (being Voltage loop 212 in Fig. 2), therefore when fluctuation occurs input voltage, load can obtain and regulate quickly, the basic ripple disable of output current, as shown in Figure 10.
Be only a specific embodiment of the present invention shown in Fig. 9, the present invention also can be applicable to other main circuit structure circuit of power factor correction, as buck-boost PFC, buck PFC and f1yback PFC etc.Power Factor Correction Control part in Fig. 9 have employed the power factor correction control circuit of band multiplier, in the middle of practical application, the present invention also can in conjunction with the power factor correction control circuit of other structure, as constant turn-on time control etc., enforcement of the present invention does not limit by the concrete structure of main circuit and control circuit.
To sum up, adopt the input feedforward compensation circuit of the present embodiment, the fluctuation problem of output voltage or electric current when can improve input voltage mutation, when especially output loading is LED, when input voltage fluctuation, the technical scheme of the present embodiment can ensure LED flicker free problem.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.
Claims (10)
1. an input feedforward compensation circuit for circuit of power factor correction, is characterized in that, comprising:
Peak value acquisition module, the signal of the peak value obtaining input voltage or the peak value reflecting described input voltage;
The negate circuit be connected with described peak value acquisition module, produces the direct current signal contrary with the peak change trend of described input voltage;
The supercircuit be connected with described negate circuit, superposes the output signal that described direct current signal and the error in the control circuit of circuit of power factor correction amplify network.
2. input feedforward compensation circuit according to claim 1, is characterized in that, described input voltage be via rectifier bridge rectification in circuit of power factor correction after voltage signal.
3. input feedforward compensation circuit according to claim 1, is characterized in that, described peak value acquisition module comprises:
Ratio circuit, receives described input voltage and regulates its amplitude;
The peak value acquisition cuicuit be connected with described ratio circuit, obtains the peak value of the input voltage after amplitude adjustment.
4. input feedforward compensation circuit according to claim 3, is characterized in that, described peak value acquisition cuicuit comprises:
Bias voltage source;
Operational amplifier, its positive input terminal connects the output of described ratio circuit;
Comparator, its positive input terminal connects the positive input terminal of described bias voltage source, and its negative input end connects the positive input terminal of described operational amplifier;
Diode, its anode connects the output of described operational amplifier, and its negative electrode connects the negative input end of described operational amplifier;
First electric capacity, its first end connects the negative input end of described operational amplifier, its second end ground connection;
Inverter, its input connects the output of described operational amplifier;
Forward position acquisition cuicuit, its input connects the output of described inverter;
First switch, its first end connects the first end of described first electric capacity, and its second end connects the second end of described first electric capacity, and its control end connects the output of described comparator;
Second switch, its first end connects the positive input terminal of described operational amplifier, and its control end connects the output of described forward position acquisition cuicuit;
Second electric capacity, its first end connects the second end of described second switch, its second end ground connection, and the first end of described second electric capacity is as the output of described peak value acquisition cuicuit.
5. input feedforward compensation circuit according to claim 4, is characterized in that, described forward position acquisition cuicuit adopts RC circuit and logical circuit to realize.
6. input feedforward compensation circuit according to claim 3, is characterized in that, described peak value acquisition cuicuit comprises:
The lowest point time detection circuit, its input connects the output of described ratio circuit, for detecting the lowest point time of described input voltage, produces pulse signal to locate the lowest point time of described input voltage;
Delay circuit, its input connects the output of described the lowest point time detection circuit, carries out time delay to described pulse signal;
Sampling hold circuit, is connected with the output of delay circuit with described ratio circuit, samples under pulse signal after the delay controls to the input voltage after amplitude adjustment;
Scaling circuit, its input is connected with the output of described sampling hold circuit, and its output is as the output of described peak value acquisition cuicuit.
7. input feedforward compensation circuit according to claim 6, it is characterized in that, described sampling hold circuit comprises:
3rd switch, its control end connects the output of described delay circuit, and its first end connects the output of described ratio circuit, and its second end connects the input of described scaling circuit;
3rd electric capacity, its first end connects the second end of described 3rd switch, its second end ground connection.
8. input feedforward compensation circuit according to claim 1, is characterized in that, described negate circuit comprises:
Subtracter, its positive input terminal receives the direct voltage preset, and its negative input end connects the output of described peak value acquisition module, and its output exports described direct current signal.
9. input feedforward compensation circuit according to claim 1, it is characterized in that, described supercircuit comprises:
Adder, its first input end connects the output of described negate circuit, and its second input error received in described control circuit amplifies the output signal of network.
10. a circuit of power factor correction, is characterized in that, comprises the input feedforward compensation circuit according to any one of claim 1 to 9.
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| WO2022056512A1 (en) * | 2020-09-14 | 2022-03-17 | Vitesco Technologies USA, LLC | Method and apparatus for adaptive feedforward correction of output current ripple in an on-board charging system |
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| CN103066827A (en) | 2013-04-24 |
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