CN103048733A - Conical multilayer ridge waveguide structure and production method thereof - Google Patents
Conical multilayer ridge waveguide structure and production method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 110
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 110
- 239000010703 silicon Substances 0.000 claims abstract description 110
- 239000000463 material Substances 0.000 claims abstract description 65
- 238000005530 etching Methods 0.000 claims abstract description 44
- 230000006835 compression Effects 0.000 claims abstract description 43
- 238000007906 compression Methods 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 36
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 230000000694 effects Effects 0.000 claims abstract description 20
- 238000011049 filling Methods 0.000 claims description 30
- 238000001020 plasma etching Methods 0.000 claims description 28
- 238000011068 loading method Methods 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 7
- 238000002360 preparation method Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 230000008878 coupling Effects 0.000 abstract description 9
- 238000010168 coupling process Methods 0.000 abstract description 9
- 238000005859 coupling reaction Methods 0.000 abstract description 9
- 230000005540 biological transmission Effects 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 238000010586 diagram Methods 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 11
- 235000012239 silicon dioxide Nutrition 0.000 description 10
- 230000003287 optical effect Effects 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000013307 optical fiber Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000000452 restraining effect Effects 0.000 description 3
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- XUIMIQQOPSSXEZ-AKLPVKDBSA-N silicon-31 atom Chemical compound [31Si] XUIMIQQOPSSXEZ-AKLPVKDBSA-N 0.000 description 1
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Abstract
The invention discloses a conical multilayer ridge waveguide structure and a production method thereof. The layer quantity of the conical multilayer ridge waveguide structure is at least three, the conical multilayer ridge waveguide structure comprises a coupling end and a compression end, and the height of steps on non-bottom layers and non-top layers is gradually reduced from the coupling end to the compression end. The technical sequence of the production method is as follows: the etching is carried out firstly, then monocrystalline silicon is carried out through epitaxial growth, and finally the epitaxial grown monocrystalline silicon is etched and formed. Firstly a silicon groove is formed on a silicon chip through an etching way, and a target device area is defined; the silicon groove is filled, and a selective epitaxial mask material is deposited on the silicon chip after the surface of the silicon chip is flattened; the monocrystalline silicon is selectively epitaxially grown on the target device area; and finally the selective epitaxial grown monocrystalline silicon is etched and formed. The multilayer ridge waveguide structure can effectively reduce the transmission loss of the ridge waveguide and also can improve the coupling efficiency of the ridge waveguide; and the production method can simplify the working procedures without need of overcoming the micro load effect.
Description
Technical field
The present invention relates to a kind of optical waveguide structure and preparation method thereof, especially a kind of taper multilayer ridge waveguide structure and preparation method thereof.
Background technology
In traditional multilayer ridge waveguide structure, it is constant along the waveguide longitudinal stability to pursue each bench height, and namely the gash depth of different etching live width is consistent.And because the micro loading effect in the plasma etch process, very large difference appears in the etching depth at different etching live width place, and the requirement of etching groove deep equality is runed counter in this and the traditional multilayer ridge waveguide device architecture.For realizing traditional multilayer ridge waveguide structure, just must overcome this micro loading effect, thereby increase technology difficulty.The etching depth difference that the micro loading effect of plasma etching causes becomes the reason that traditional multilayer ridge waveguide device performance descends.
A kind of taper multilayer ridge waveguide structure disclosed by the invention and preparation method thereof, need not to overcome micro loading effect, reasonably utilize on the contrary the micro loading effect in the plasma etching, produce a kind of taper multilayer ridge waveguide structure with low transmission loss and high coupling efficiency.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of taper multilayer ridge waveguide structure and preparation method thereof is provided.
The present invention is achieved by following technical proposals:
A kind of taper multilayer ridge waveguide structure, its number of plies is more than three layers, comprises coupled end and compression end, wherein, the height that is positioned at the step of non-bottom and non-top layer reduces from the coupled end to the compression end gradually.The height of described each layer of ridge waveguide step can be unequal or equal.Described ridge waveguide structure is to make at the high index of refraction single crystal silicon material that low-refraction substrate plate material adheres to, for example SOI.
A kind of method for making of above-mentioned taper multilayer ridge waveguide structure may further comprise the steps:
Step 1: using plasma etching technics, carry out etching at initial silicon chip surface, define the target devices district: namely remove a part of material of described silicon chip surface according to the first mask pattern, thereby obtain some silicon grooves and the target devices district between described silicon groove;
Step 2: use silicon groove described in the filling material filling step 1, and described silicon chip surface is carried out planarization;
Step 3: at described silicon chip surface deposition selective epitaxial mask material, and according to the part that is positioned in the second mask graph removal selective epitaxial mask material on the top, described target devices district;
Step 4: adopt selective epitaxial process, growing single-crystal silicon is to the required height of target devices on the surface, target devices district that exposes in step 3;
Step 5 a: part of removing the monocrystalline silicon of growth in the step 4 according to the 3rd mask pattern, described the 3rd mask pattern live width becomes large gradually from the ridge waveguide-coupled end to compression end, utilize the micro loading effect in the plasma etching, form the degree of depth and become gradually large silicon groove along the waveguide-coupled end to compression end;
Step 6: the silicon groove with forming in the filling material filling step 5, then carry out planarization to silicon chip surface;
Step 7: another part material of removing the monocrystalline silicon of growth in the step 4 according to the 4th mask pattern, described the 4th mask pattern live width becomes large gradually from the ridge waveguide-coupled end to compression end, utilize the micro loading effect in the plasma etching, again obtain the degree of depth and become gradually large silicon groove along the ridge waveguide-coupled end to compression end, described silicon groove is near the silicon groove that forms in the step 5;
Step 8: remove residual filling material, then in type taper multilayer silicon ridge waveguide seal coat.
In the above-mentioned method for making, the etching depth of described each layer of ridge waveguide structure step is by the etching depth definition of etch mask figure live width maximum.
A kind of taper multilayer ridge waveguide structure disclosed by the invention, its height that is positioned at the step of non-bottom and non-top layer reduces from the coupled end to the compression end gradually, with respect to traditional multilayer ridge waveguide structure, be conducive to the conversion of light wave pattern between wave guide ridge and flat board, can effectively reduce the loss of optical waveguide.Preparation technology disclosed by the invention need not to overcome the micro loading effect in the plasma etching industrial, is used on the contrary, has simplified operation.By the ramp control to the mask pattern live width, utilize the micro loading effect in the plasma etching industrial, form the silicon groove of etching depth along the waveguide-coupled end to the from shallow to deep gradual change of compression end direction.Because ridge waveguide-coupled end etching depth is shallow, face area is large, can accept to greatest extent the Optical Fiber Transmission energy, improves the coupling efficiency of optical waveguide; In addition, the etching in the technical scheme disclosed by the invention sequentially is deep etching after the erosion of first light engraving, can avoid carry out deep etching after, to the filling problem of formation silicon groove and the flattening surface problem of blocked up filling material, the saving manufacturing cost.
Technical scheme applicability disclosed by the invention is wider, and general CMOS factory can directly adopt.The selective epitaxial process growing single-crystal silicon that adopts in the technical scheme disclosed by the invention is little with the light carrier scattering to communication, is suitable for making the optical fiber communication optical waveguide.
Description of drawings
Fig. 1 is the stereographic map of a kind of taper multilayer ridge waveguide structure disclosed by the invention.
Fig. 2 is the floor map of a kind of taper multilayer ridge waveguide structure disclosed by the invention.
Fig. 3 is the initial silicon chip synoptic diagram that is used for making taper multilayer ridge waveguide structure among the present invention.
Fig. 4 is the silicon chip synoptic diagram after transferring to the first mask graph on the mask material in the method for making step 1 disclosed by the invention.
Fig. 5 is the silicon chip synoptic diagram behind the method for making step 1 applying plasma etching single crystal silicon disclosed by the invention.
Fig. 6 uses the silicon groove described in the filling material filling step 1 in the method for making step 2 disclosed by the invention, and to the silicon chip synoptic diagram after the described silicon chip surface planarization.
Fig. 7 is the silicon chip synoptic diagram of deposition selective epitaxial mask material behind the object height in the method for making step 3 disclosed by the invention.
Fig. 8 is according to the silicon chip synoptic diagram behind the selective epitaxial mask material that covers in the second mask graph version removal target devices district in the method for making step 3 disclosed by the invention.
Fig. 9 is at the silicon chip synoptic diagram of target devices regioselectivity epitaxial growth monocrystalline silicon to the target devices desired height in the method for making step 4 disclosed by the invention.
Figure 10 is the silicon chip synoptic diagram of in the method for making step 5 disclosed by the invention the 3rd mask graph being transferred on the mask material.
The silicon chip synoptic diagram that Figure 11 is method for making step 5 applying plasma Etch selectivity epitaxial monocrystalline silicon disclosed by the invention to the target depth.
Figure 12 be in the method for making step 6 disclosed by the invention with silicon groove described in the filling material filling step 5, then silicon chip surface is carried out silicon chip synoptic diagram after the planarization.
Figure 13 is the silicon chip synoptic diagram of in the method for making step 7 disclosed by the invention the 4th mask graph being transferred on the mask material.
The silicon chip synoptic diagram that Figure 14 is method for making step 7 applying plasma etching epitaxial growth monocrystalline silicon disclosed by the invention to the target depth.
Figure 15 is with the silicon chip synoptic diagram behind the filling material residue removal in the manufacture process in the method for making step 8 disclosed by the invention.
Figure 16 is the silicon chip synoptic diagram after ridge waveguide surface coverage coating in the method for making step 8 disclosed by the invention.
Embodiment
Below by specific embodiment, by reference to the accompanying drawings the present invention is described in detail simultaneously:
Fig. 1 and Fig. 2 are respectively stereographic map and the floor map of a kind of taper multilayer ridge waveguide structure disclosed by the invention, take four layers as example.As shown in Figure 1, ridge waveguide 20 comprises four layers of step 24,25,26 and 27.The height of each layer step can be unequal or equal.As shown in Figure 2, ridge waveguide 20 comprises coupled end 28 and compression end 29. Step 25,26 height 29 reduce gradually from coupled end 28 to compression end.
Taper multilayer ridge waveguide disclosed by the invention is to make at the high index of refraction single crystal silicon material that low-refraction substrate plate material adheres to, for example SOI.As shown in Figure 3, ridge waveguide 20 is produced on the initial silicon chip 30.Silicon chip 30 is a silicon chip that comprises surface single crystal silicon 31, buried regions 32 and substrate 33.Each layer bench height of the ridge waveguide 20 that the present invention is mentioned refers to the vertical height of 32 upper surfaces from the ledge surface to the buried regions.Buried regions 32 can be silicon dioxide, also can be and discrepant other the suitable buried regions of monocrystalline silicon refractive index.Substrate 33 can be monocrystalline silicon, also can be other suitable material.
The method for making of a kind of taper multilayer ridge waveguide disclosed by the invention is as follows:
Step 1: using plasma etching technics, carry out etching on initial silicon chip 30 surfaces, define the target devices district: namely remove a part of material on silicon chip 30 surfaces according to the first mask pattern, thereby obtain some silicon grooves and the target devices district between described silicon groove.
After silicon chip 30 carried out cleaning treatment, deposit the mask material 35 that one deck is used for the plasma etching restraining barrier thereon, the mask material can be silicon dioxide and silicon nitride, also can be other suitable material.According to the first mask graph, utilize photoetching technique that the first mask graph is transferred on the mask material 35, be formed for the mask graph 34 of plasma etching, as shown in Figure 4." A " among Fig. 4, " B ", " C ", " D " and " E " is respectively " A " among Fig. 2, " B ", and " C ", the schematic cross-section of " D " and " E " five positions, namely the ridge waveguide-coupled end is to vertical tangent plane of five positions of compression end direction.
Utilize plasma etching light engraving erosion monocrystalline silicon to target depth, obtain some silicon grooves 36, and the target devices district 37 between the silicon groove.Because this etching is light engraving erosion, it is not obvious that silicon groove depth-width ratio affects the micro loading effect of etch rate, and silicon groove 36 has identical etching depth.After step 1 finished, the structure of silicon chip 30 as shown in Figure 5.
Step 2: fill silicon groove 36 with filling material, and planarization is carried out on silicon chip 30 surfaces.
As shown in Figure 6, utilize 38 pairs of silicon grooves 36 of filling material to fill, filling material can be any suitable material.In certain embodiments, filling material 38 can be antireflecting coating (such as hydrocarbon), polymerization silicon, perhaps silicon dioxide.Use silicon dioxide as the filling material of silicon groove 36 in the present embodiment.Then utilize chemical mechanical milling method that silicon chip 30 is carried out planarization, until expose the upper surface in target devices district 37; Also can realize by other any applicable method the planarization of silicon chip surface.
Step 3: at silicon chip 30 surfaces deposition selective epitaxial mask material 39, and according to the part that is positioned in the second mask graph removal selective epitaxial mask material 39 on 37 tops, described target devices district.
At silicon chip 30 deposition selective epitaxial mask materials 39, use silicon dioxide as the mask material of selective epitaxial, as shown in Figure 7 in the present embodiment.The height of the epi-mask material 39 of deposition is not less than the required selective epitaxial monocrystalline silicon height of target devices.In certain embodiments, use silicon nitride or other suitable material as selective epitaxial mask material.
According to the second mask graph, remove the part that is positioned in the selective epitaxial mask material 39 on 37 tops, described target devices district, obtain the mask graph 40 for selective epitaxial, as shown in Figure 8.
Step 4: adopt selective epitaxial process, growing single-crystal silicon is to the required height of target devices on 37 surfaces, target devices district that expose in step 3.
Selective epitaxial growth monocrystalline silicon 41 is to the required height of target devices, as shown in Figure 9 on 37 surfaces, target devices district that expose.
Step 5 a: part of removing the monocrystalline silicon 41 of growth in the step 4 according to the 3rd mask pattern, described the 3rd mask pattern live width becomes large gradually from the ridge waveguide-coupled end to compression end, utilize the micro loading effect in the plasma etching, form the degree of depth and 29 become gradually large silicon groove along waveguide-coupled end 28 to compression end.
After silicon chip 30 carried out cleaning treatment, deposit the mask material 43 that one deck is used for the plasma etching restraining barrier thereon, the mask material can be silicon dioxide and silicon nitride, also can be other suitable material.The 3rd mask pattern live width 29 becomes large gradually from ridge waveguide-coupled end 28 to compression end.According to the 3rd mask graph, utilize photoetching technique that the 3rd mask graph is transferred on the mask material 43, be formed for the mask graph 42 of plasma etching.Live width at the mask graph 42 of ridge waveguide-coupled end 28 is less, and is larger in the live width of ridge waveguide compression end 29 mask graphs 42, and namely the mask graph live width 29 increases gradually from coupled end 28 to compression end, as shown in figure 10.
Utilize plasma anisotropic etching technology that monocrystalline silicon 41 is carried out etching, form the degree of depth and 29 become gradually large silicon groove 44 along waveguide-coupled end 28 to compression end.The width of silicon groove 44 depends on the live width of the 3rd mask pattern, and namely its width also 29 becomes large gradually from ridge waveguide-coupled end 28 to compression end.Because the micro loading effect of plasma etching, the speed of etching is subject to the impact of silicon groove depth-width ratio in the etching process, and high wide this large silicon groove etching speed is low, and etching depth is shallow, and then etch rate is high for the little silicon groove of depth-width ratio, and etching depth is darker.We are positioned at the etching depth at ridge waveguide compression end 29 places (being silicon groove 44 width maximums) as the reference depth of plasma dry etching with silicon groove 44, and the etching depth that silicon groove 44 is positioned at ridge waveguide-coupled end 28 places (being the minimum places of silicon groove 44 width) is significantly smaller than this reference depth.Figure after the etching as shown in figure 11, the direction along waveguide-coupled end 28 to compression end 29, the degree of depth of silicon groove 44 from shallow to deep.Because the micro loading effect of plasma etching, the figure that forms at last cause the area of coupled end 28 to increase, and are conducive to the more efficient energy of accepting Optical Fiber Transmission, improve the coupling efficiency of optical waveguide.29 directions have formed the pyramidal structure of a gradual change along waveguide-coupled end 28 to compression end, are conducive to reduce the loss of waveguide.
Step 6: the silicon groove 44 with forming in the filling material filling step 5, then carry out planarization to silicon chip surface.
After etching is finished, fill with 45 pairs of etching grooves of filling material, filling material can be any suitable material.In certain embodiments, filling material can be antireflecting coating (such as hydrocarbon), polymerization silicon, perhaps silicon dioxide.Use silicon dioxide as the filling material of groove in the present embodiment.Then utilize chemical mechanical milling method that silicon chip surface is carried out planarization, until expose the upper surface of monocrystalline silicon 41, as shown in figure 12.Also can realize by other any applicable methods the planarization of silicon chip surface.
Step 7: another part material of removing monocrystalline silicon 41 according to the 4th mask pattern, described the 4th mask pattern live width 29 becomes large gradually from ridge waveguide-coupled end 28 to compression end, utilize the micro loading effect in the plasma etching, again obtain the degree of depth and 29 become gradually large silicon groove 48 along ridge waveguide-coupled end 28 to compression end, silicon groove 48 is near the silicon groove 44 that forms in the step 5.
After the silicon chip surface planarization, silicon chip is carried out cleaning treatment, deposit the mask material 47 that one deck is used for the plasma etching restraining barrier thereon, the mask material can be silicon dioxide and silicon nitride, also can be other suitable material.The 4th mask pattern live width 29 becomes large gradually from ridge waveguide-coupled end 28 to compression end.According to the 4th mask graph, utilize photoetching technique that the 4th mask graph is transferred on the mask material 47, be formed for the mask graph 46 of plasma etching.Live width at the mask graph 46 of waveguide-coupled end 28 is less, and is larger in the live width of mode compression end 29 mask graphs 46.The mask graph live width is 29 gradually increases from coupled end 28 to compression end, specifically as shown in figure 13.
Utilize plasma etching technology that monocrystalline silicon 41 is carried out etching, again form the degree of depth and 29 become gradually large silicon groove 48 along waveguide-coupled end 28 to compression end.The width of silicon groove 48 depends on the live width of the 4th mask pattern, and namely its width also 29 becomes large gradually from ridge waveguide-coupled end 28 to compression end.Because the micro loading effect of plasma etching, the speed of etching is subject to the impact of silicon groove depth-width ratio in the etching process, and the silicon groove etching speed that depth-width ratio is large is low, and etching depth is shallow, and then etch rate is high for the little silicon groove of depth-width ratio, and etching depth is darker.We are positioned at the etching depth at ridge waveguide compression end 29 places (being silicon groove 48 width maximums) as the reference depth of plasma etching with silicon groove 48, and the etching depth that silicon groove 48 is positioned at ridge waveguide-coupled end 28 places (being the minimum places of silicon groove 48 width) is significantly smaller than this reference depth.The structure of silicon chip as shown in figure 14 after the etching.Direction along waveguide-coupled end 28 to compression end 29, etching depth from shallow to deep.Because the micro loading effect of plasma etching, the figure that forms at last cause the area of coupled end 28 to increase, and are conducive to the more efficient energy of accepting Optical Fiber Transmission, improve the coupling efficiency of optical waveguide.Form the pyramidal structure of a gradual change along the waveguide-coupled end to the compression end direction, be conducive to reduce the loss of waveguide.
Step 8: remove residual filling material, then in type taper multilayer silicon ridge waveguide seal coat.
Taper multilayer ridge waveguide structure has four layers of step in the present embodiment, is followed successively by from top to bottom step 24,25,26,27.Step 24 respectively has identical bench height from the waveguide-coupled end to the compression end direction with 27.And the bench height of step 25 and 26 respectively from waveguide-coupled end 28 to compression end 29 gradually from large to small.This special construction can be effectively the light wave pattern that is coupled into optical waveguide level and smooth be transferred to compression end, reduce the loss of optical waveguide; The Area comparison of coupled end 28 is large, can accept to greatest extent the Optical Fiber Transmission energy, improves the coupling efficiency of optical waveguide; Everything all will have benefited from utilizing the pyramidal structure of multilayer ridge waveguide along coupled end to the compression end direction of this kind method manufacturing, and the generation of this pyramidal structure is owing in plasma etch process, reasonably utilized the etching micro loading effect.The taper multilayer ridge waveguide of this kind method manufacturing has low loss and high coupling efficiency.
Above embodiment has been described in detail the present invention, but not limit.Those skilled in the art can make the many variations example to the present invention according to the above description.Thereby some details in the embodiment should not consist of limitation of the invention, and the scope that the present invention will define with appended claims is as protection scope of the present invention.
Claims (5)
1. taper multilayer ridge waveguide structure, its number of plies is more than three layers, comprises coupled end and compression end, it is characterized in that, the height that is positioned at the step of non-bottom and non-top layer reduces from the coupled end to the compression end gradually.
2. taper multilayer ridge waveguide structure according to claim 1 is characterized in that, the height of each layer step can be unequal or equal.
3. taper multilayer ridge waveguide structure according to claim 1 is characterized in that, described ridge waveguide structure is to make at the high index of refraction single crystal silicon material that low-refraction substrate plate material adheres to, for example SOI.
4. the method for making of a taper multilayer ridge waveguide structure claimed in claim 1 may further comprise the steps:
Step 1: using plasma etching technics, carry out etching at initial silicon chip surface, define the target devices district: namely remove a part of material of described silicon chip surface according to the first mask pattern, thereby obtain some silicon grooves and the target devices district between described silicon groove;
Step 2: use silicon groove described in the filling material filling step 1, and described silicon chip surface is carried out planarization;
Step 3: at described silicon chip surface deposition selective epitaxial mask material, and according to the part that is positioned in the second mask graph removal selective epitaxial mask material on the top, described target devices district;
Step 4: adopt selective epitaxial process, growing single-crystal silicon is to the required height of target devices on the surface, target devices district that exposes in step 3;
Step 5 a: part of removing the monocrystalline silicon of growth in the step 4 according to the 3rd mask pattern, described the 3rd mask pattern live width becomes large gradually from the ridge waveguide-coupled end to compression end, utilize the micro loading effect in the plasma etching, form the degree of depth and become gradually large silicon groove along the waveguide-coupled end to compression end;
Step 6: the silicon groove with forming in the filling material filling step 5, then carry out planarization to silicon chip surface;
Step 7: another part material of removing the monocrystalline silicon of growth in the step 4 according to the 4th mask pattern, described the 4th mask pattern live width becomes large gradually from the ridge waveguide-coupled end to compression end, utilize the micro loading effect in the plasma etching, again obtain the degree of depth and become gradually large silicon groove along the ridge waveguide-coupled end to compression end, described silicon groove is near the silicon groove that forms in the step 5;
Step 8: remove residual filling material, then in type taper multilayer silicon ridge waveguide seal coat.
5. the preparation method of taper multilayer ridge waveguide structure according to claim 4 is characterized in that, the etching depth of described each layer of ridge waveguide structure step is by the etching depth definition of etch mask figure live width maximum.
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| CN112612078A (en) * | 2020-12-18 | 2021-04-06 | 海南师范大学 | High-efficiency coupling waveguide based on GOI or SOI and preparation method thereof |
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| US11940707B2 (en) | 2020-02-24 | 2024-03-26 | Shanghai Jiao Tong University | High-speed and low-voltage electro-optical modulator based on lithium niobate-silicon wafer |
| CN111624710A (en) * | 2020-04-27 | 2020-09-04 | 联合微电子中心有限责任公司 | Waveguide device and method of forming the same |
| CN111624710B (en) * | 2020-04-27 | 2022-06-10 | 联合微电子中心有限责任公司 | Waveguide device and method of forming the same |
| CN112612078A (en) * | 2020-12-18 | 2021-04-06 | 海南师范大学 | High-efficiency coupling waveguide based on GOI or SOI and preparation method thereof |
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