CN114895401A - Silicon photonic chip optical coupling structure and manufacturing method thereof - Google Patents
Silicon photonic chip optical coupling structure and manufacturing method thereof Download PDFInfo
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/12002—Three-dimensional structures
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4287—Optical modules with tapping or launching means through the surface of the waveguide
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4296—Coupling light guides with opto-electronic elements coupling with sources of high radiant energy, e.g. high power lasers, high temperature light sources
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12133—Functions
- G02B2006/12147—Coupler
Abstract
The invention discloses a silicon photonic chip optical coupling structure and a manufacturing method thereof, wherein the silicon photonic chip optical coupling structure comprises a silicon substrate; a device layer of the silicon substrate is provided with a silicon photonic chip functional structure area, and the silicon photonic chip functional structure area is provided with an optical waveguide area and an optical coupling area; the optical coupling area is provided with an inverted ridge-shaped groove and extends from the end face of the silicon substrate to the optical waveguide area; the edge the ridge groove inner wall that falls is provided with the one deck isolation layer, the ridge optical waveguide that just is located the top of isolation layer in falling the ridge ditch groove is provided with the ridge optical waveguide that falls, the terminal surface and the optic fibre butt joint on ridge optical waveguide layer that falls, the other end and the regional butt joint of device layer optical waveguide. The optical coupling structure of the silicon photonic chip obtained by the structure and the method can realize low-loss, distortion-free and high-efficiency coupling of the silicon photonic chip and a single-mode optical fiber or a laser chip, and has low transmission loss.
Description
Technical Field
The invention relates to the technical field of optical devices, in particular to a silicon photonic chip optical coupling structure and a manufacturing method thereof.
Background
The silicon photonic technology is based on the same material as the microelectronic integration technology, namely a silicon material, and utilizes the existing new technology compatible with CMOS (complementary metal oxide semiconductor) to develop and integrate a photonic device, and can be integrated with an electronic device simultaneously to realize the integration of the photonic device, so that the silicon photonic technology integrates the advantages of the microelectronic technology such as ultra-large scale integration and the like and the advantages of the silicon photonic technology such as ultra-high speed, ultra-low power consumption and the like, and is one of the hotspots of the current research and development. Besides telecommunication and data communication, the application of silicon photonics technology also includes biosensing, non-linear optics, laser radar systems, optical gyroscopes, radio frequency integrated optoelectronics, integrated radio transceivers, novel light sources, laser noise reduction, gas sensors, high-speed microwave signal processing, and the like.
The alignment coupling of the silicon photonic chip and the single-mode optical fiber is inevitably realized in the application process of the silicon photonic device. The optical coupling method and structure of the silicon photonic chip commonly used at present mainly comprise vertical grating coupling and end face coupling. The vertical grating coupling is based on a Bragg grating, and the silicon photonic chip and the optical fiber are coupled at an angle of approximately 90 degrees; the end face coupling is to manufacture a spot adapter at the coupling position of the silicon photonic chip to realize optical coupling of the spot adapter and the silicon photonic chip. The vertical coupling optical loss is at least about 3dB, the optical loss is further reduced, the technical difficulty is high, and the space structure required by the vertical coupling is large and is polarization sensitive. Regardless of whether the optical fiber is vertically or horizontally placed or the vertical grating coupling is reflected, the optical coupling efficiency is difficult to be improved to more than 50%, and the requirement on the photoetching precision is high. End face coupling and discrete optical lens group coupling are adopted, so that the coupling efficiency is relatively high, but the packaging volume is large, the integration of an optical chip is inconvenient, and the reliability is reduced; the spot adapter is made of a heterogeneous material, a tip optical waveguide needs to be manufactured, the requirement on the photoetching precision is high, and the coupling efficiency is difficult to improve; multilayer ridge waveguides or 3D waveguides can improve coupling efficiency, but the existing structures are formed by etching in a large area, the large area almost occupies 99% of the area of a wafer, the manufacturing time is long, and the roughness of the etched surface and the etched side wall is difficult to control, so that the optical transmission loss is large. For example, chinese patent application No. 2009801361983 entitled method and apparatus for efficient coupling of silicon photonics chips to optical fibers, is a 3D waveguide structure.
Disclosure of Invention
The invention aims to provide a silicon photonic chip optical coupling structure and a manufacturing method thereof, which solve the problems of high manufacturing cost and large optical transmission loss of the existing optical coupling structure.
The technical scheme adopted by the invention for solving the technical problems is as follows: the technical scheme adopted by the invention for solving the technical problems is as follows: a silicon photonic chip optical coupling structure for transmitting continuous light comprises a silicon substrate; a device layer of the silicon substrate is provided with a silicon photonic chip functional structure area, and the silicon photonic chip functional structure area is provided with an optical waveguide area and an optical coupling area; the optical coupling area is provided with an inverted ridge-shaped groove and extends from the end face of the silicon substrate to the optical waveguide area; the edge the ridge groove inner wall that falls is provided with the one deck isolation layer, the ridge optical waveguide layer that just is located the top of isolation layer in falling the ridge groove is provided with the ridge optical waveguide layer that falls, the terminal surface and the butt joint of optic fibre on the ridge optical waveguide layer that falls are used for receiving the optical waveguide, and the regional butt joint of other one end and device layer optical waveguide is used for transmitting the optical waveguide.
Preferably, the isolation layer is made of low-stress silicon oxide, and the inverted ridge optical waveguide layer is made of polysilicon.
Specifically, the inverted ridge-shaped groove is at least provided with two layers of grooves from the surface of the silicon substrate to the bottom, the grooves are a first groove and a second groove from top to bottom in sequence, the end face widths of the first groove and the second groove are not smaller than the core diameter of the optical fiber, the other end of the first groove is in butt joint with the device layer optical waveguide area, and the width of the joint of the first groove and the device layer optical waveguide area is equal to the width of the device layer optical waveguide; the length of the second groove is not more than that of the first groove, and the width of one end, close to the optical waveguide area, of the second groove is larger than that of one end, close to the optical waveguide area, of the first groove.
Preferably, the inverted ridge-shaped trench is provided with more than three layers of trenches from the surface of the silicon substrate to the bottom, and is a first trench and an nth trench … … from top to bottom in sequence, wherein the length of the next trench is not greater than that of the previous trench, and the widths of the second trench to the nth trench near one end of the optical waveguide region of the device layer gradually increase from one layer to the next.
Furthermore, the inverted ridge-shaped groove is 1-1.5 times of the core diameter of the optical fiber.
The silicon substrate is also provided with an upper cladding which covers the surfaces of the inverted ridge-shaped optical waveguide layer and the functional structure region of the silicon photonic chip, and the upper cladding and the lower cladding are used for limiting the light wave in the inverted ridge-shaped waveguide layer for propagation.
Preferably, the material of the upper cladding is low-stress silicon oxide.
Preferably, the width of the inverted ridge trench is gradually narrowed from the end surface of the silicon substrate toward the device layer optical waveguide region.
The invention also discloses a manufacturing method of the silicon photonic chip optical coupling structure, which comprises the following steps:
1) forming a silicon oxide layer on the silicon substrate by dry oxidation;
2) depositing a low-stress silicon oxide layer on the silicon oxide layer in the step 1) by a plasma chemical vapor deposition method;
3) defining the shape of an upper ridge region of the inverted ridge optical waveguide in the optical coupling region by mask lithography, and then etching downwards by a dry plasma etching process to form a first groove of the inverted ridge optical waveguide;
4) defining the shape of a second layer of ridge region of the inverted ridge optical waveguide in the optical coupling region by mask photoetching, and then etching downwards by a dry plasma etching process to form a second groove of the inverted ridge optical waveguide; etching the third trench to the Nth trench in the same way as the second trench;
5) dry oxidation to smooth the inverted ridge trench formed by the above process; then depositing a layer of low-stress silicon oxide layer on the surface of the silicon substrate and in the inverted ridge-shaped groove by a plasma deposition method;
6) removing the low-stress silicon oxide layer at the butt joint position of the first groove step and the optical waveguide region of the device layer by mask photoetching;
7) growing polysilicon on the surface of the silicon substrate by an epitaxial process until the whole inverted ridge-shaped groove is filled;
8) high-temperature annealing is carried out, the properties of the epitaxial polysilicon are adjusted, and the defects are reduced so as to achieve low transmission loss;
9) planarizing the silicon substrate by Chemical Mechanical Polishing (CMP) to expose a clean device layer after CMP;
10) and manufacturing a silicon optical functional structure, finally forming a multilayer inverted ridge optical coupling structure in the optical coupling area, and depositing a low-stress silicon oxide layer on the surface of the functional structure area of the silicon photonic chip by a plasma deposition method to form an upper cladding.
In order to improve the smoothness of the side wall of the inverted ridge-shaped groove, the step 5) further comprises removing the dry-process oxide layer of the groove by diluted hydrofluoric acid HF after dry oxidation, and then performing dry oxidation until the side wall of the formed inverted ridge-shaped groove is smooth.
In order to improve the surface flatness of the wafer, in step 9), the epitaxial polysilicon in the optical coupling region is protected by mask lithography, then the polysilicon is etched by isotropic chemical etching to achieve the uniform height of each region on the surface of the wafer, and then the silicon substrate is flattened by CMP.
The invention has the beneficial effects that: the optical coupling structure adopts the design of an inverted ridge structure, then a layer of silicon oxide is deposited through oxidation and plasma to be used as an isolating layer, and then polysilicon is epitaxially grown in a plurality of layers of inverted ridge grooves to be filled to be used as a mode spot adapting structure aligned and coupled with a silicon photonic chip, so that the low-loss, distortion-free and high-efficiency coupling of the silicon photonic chip and a single-mode optical fiber or a laser chip can be realized, and the transmission loss is low.
The invention will be explained in more detail below with reference to the drawings and examples.
Drawings
FIG. 1 is a schematic perspective view of the present invention with two layers of grooves.
Fig. 2 is a schematic perspective view of the present invention with three layers of trenches.
Fig. 3 is a partial longitudinal cross-sectional view of the invention with a three layer groove.
Fig. 4 is a cross-sectional view a-a of fig. 3.
Fig. 5 is a sectional view of B-B in fig. 3.
Fig. 6 is a cross-sectional view of C-C in fig. 3.
Fig. 7 is a cross-sectional view of D-D in fig. 3.
Fig. 8 is a schematic structural view of a silicon oxide layer formed on a silicon substrate in the present invention.
Fig. 9 is a schematic structural view of a low stress silicon oxide layer deposited on a silicon oxide layer 8 according to the present invention.
Fig. 10 is a schematic structural view of coating a photoresist on a low stress silicon oxide layer.
Fig. 11 is a schematic diagram of a structure of forming a photoresist mask on a low stress silicon oxide layer.
Fig. 12 is a schematic structural view of a silicon oxide hard mask formed by a mask lithography process.
Fig. 13 is a schematic view of the structure after the photoresist is removed.
Fig. 14 is a structural diagram illustrating the formation of a first trench.
FIG. 15 is a schematic structural diagram of a low stress silicon oxide layer deposited on the first trench and the functional structure region of the silicon photonic chip.
Fig. 16 is a schematic structural view of coating a photoresist on a low stress silicon oxide layer.
Fig. 17 is a schematic diagram of a structure in which a photoresist mask is formed on a low stress silicon oxide layer.
Fig. 18 is a schematic structural view of forming a silicon oxide hard mask.
FIG. 19 is a schematic diagram of a structure for removing photoresist.
Fig. 20 is a structural diagram illustrating the formation of a second trench.
Fig. 21 is a schematic structural view of a silicon oxide layer formed on the surface of the silicon substrate and in the inverted ridge trench.
Fig. 22 is a schematic structural view of a low stress silicon oxide layer formed on a silicon oxide layer.
Fig. 23 is a schematic structural view showing the removal of the silicon oxide layer at the position where the first trench step interfaces with the optical waveguide region of the device layer.
Fig. 24 is a schematic structural view of growing polysilicon on the surface of a silicon substrate.
Fig. 25 is a schematic diagram showing a structure of an inverted ridge optical waveguide layer in which a two-layer structure is formed in a light coupling region.
FIG. 26 is a schematic diagram of a structure for forming an upper cladding layer.
Fig. 27 is a structural diagram illustrating formation of a third trench.
Fig. 28 is a schematic structural view of a silicon oxide layer deposited on the surface of a silicon substrate and in an inverted ridge trench.
Fig. 29 is a schematic structural view showing the removal of the silicon oxide layer at the position where the first trench step interfaces with the optical waveguide region of the device layer.
Fig. 30 is a schematic structural view of growing polysilicon on the surface of a silicon substrate.
Fig. 31 is a schematic structural view of an inverted ridge optical waveguide layer formed in the optical coupling region.
Detailed Description
The silicon substrate of this embodiment is, for example, silicon-on-insulator (SOI) with a device layer having a certain thickness, and the device layer thickness may be selected from currently common thicknesses of 220nm, 340nm, and 3 μm. And the optical fiber is coupled with the optical fiber for example, the optical fiber for coupling refers to standard single mode optical fiber, namely the optical fiber with the core diameter of 8-9 μm, and the end surface is processed by flat cutting or inclined by 8 degrees.
The reverse ridge-shaped groove 2 is provided with two layers of grooves from the surface of the silicon substrate 1 to the bottom, the grooves are a first groove 21 and a second groove 22 from top to bottom, the end face widths of the first groove 21 and the second groove 22 are not less than the core diameter of an optical fiber, namely not less than 9 μm, the other end of the first groove 21 is butted with the device layer optical waveguide region 11, and the width of the joint of the device layer optical waveguide region 11 and the device layer optical waveguide region is equal to the width of the device layer optical waveguide; for a 220nm thin device layer, the common width of an O wave band (light wave wavelength 1260nm-1360nm) is 500nm, and the common width of a C wave band (light wave wavelength 1530nm-1565nm) is 450 nm; for a thick device layer of 3 μm, the width is 3 μm; the width of the inverted ridge trench 2 gradually narrows from the end face of the silicon substrate 1 toward the device layer optical waveguide region 11. The length of the first trench 21 is not less than 1000 μm, the length of the second trench 22 is not more than the length of the first trench 21, and the width of the second trench 22 at the end close to the device layer optical waveguide region 11 is larger than the width of the first trench 21 at the end close to the optical waveguide region 13. The depth of the inverted ridge-shaped trench 2 is not less than 9 μm and not more than 15 μm, and the depth of the first trench 21 is not less than 3 μm and not more than 6 μm.
The manufacturing method of the silicon photonic chip optical coupling structure comprises the following steps:
1) forming a silicon oxide layer 100 having a thickness of not more than 100nm on the device layer of the silicon substrate 1 by dry oxidation, as shown in fig. 8;
2) depositing silicon oxide on the silicon oxide layer 100 of step 1) by a plasma chemical vapor deposition method to form a low stress silicon oxide layer 200 having a thickness of not more than 500nm, as shown in fig. 9; the silicon oxide in the low-stress silicon oxide layer 200 is prepared by a plasma chemical vapor deposition method, so that the silicon oxide layer obtained by deposition has smaller internal stress compared with the silicon oxide obtained by dry oxidation, and is called as a low-stress silicon oxide layer. The low stress silicon oxide layer is used as an etching hard mask in the optical coupling area; in other areas, the device layer is protected from the subsequent epitaxial polysilicon.
3) Coating a layer of photoresist 300 on the low-stress silicon oxide layer 200 as a mask, wherein the thickness of the photoresist 300 is 1.2um-1.3um, as shown in fig. 10, and then forming a photoresist mask through exposure and development, as shown in fig. 11; the photoresist 300 may be a positive photoresist or a negative photoresist, and different shapes of masks may be selected according to different photoresists, which is a conventional process and will not be described in detail herein.
Removing the low stress silicon oxide layer 200 and the silicon oxide layer 100 exposed outside the mask by a mask photolithography process using a photoresist as a mask to define an upper ridge region shape 400 of the inverted ridge optical waveguide of the optical coupling region, as shown in fig. 12; removing the photoresist 300 on the surface by using SPM (sulfuric acid and hydrogen peroxide), as shown in fig. 13; then, a first groove 21 of the inverted ridge optical waveguide is formed by etching downwards through a dry plasma etching process and by using the low-stress silicon oxide layer 200 as a mask, as shown in fig. 14;
4) depositing a low stress silicon oxide layer 200 with a thickness of not more than 500nm on the first trench by plasma chemical vapor deposition, as shown in fig. 15; then coating a layer of photoresist 300 on the low stress silicon oxide layer 200, as shown in fig. 16, forming a photoresist mask through an exposure and development process, as shown in fig. 17, and removing the low stress silicon oxide layer 200 and the silicon oxide layer 100 exposed outside the mask through a mask photolithography process to define the shape of the second ridge region 500 of the inverted ridge optical waveguide of the optical coupling region, as shown in fig. 18; then, removing the photoresist on the surface by using SPM (sulfuric acid and hydrogen peroxide), as shown in fig. 19, and then etching downward by using the low-stress silicon oxide layer 200 as a mask through a dry plasma etching process to form a second trench 22 of the inverted ridge optical waveguide, as shown in fig. 20;
5) the reverse ridge trench 2 formed by the above process is leveled and smoothed by dry oxidation, and if the surface of the reverse ridge trench is not leveled and smooth enough by the primary dry oxidation, the dry oxidation layer in the reverse ridge trench may be removed by diluted hydrofluoric acid HF, and then the dry oxidation layer may be removed by diluted hydrofluoric acid HF, and the dry oxidation layer in the reverse ridge trench may be again removed by diluted hydrofluoric acid HF, and the dry oxidation may be performed again until the sidewall of the formed ridge trench 1 is smooth, as shown in fig. 21, the concentration of the diluted hydrofluoric acid HF is 30% to 50%; depositing a low-stress silicon oxide layer 200 with a thickness of no more than 500nm on the surface of the silicon substrate and in the inverted ridge trench by plasma deposition, as shown in FIG. 22; the ridge trench formed by the above etching functions as an under-cladding to isolate the subsequent epitaxial polysilicon from the silicon of the substrate wafer. The other area protects the device layer from the influence of the subsequent epitaxial polysilicon and also serves as a removal stop layer of the subsequent epitaxial polysilicon.
6) Removing the silicon oxide layer 100 at the butt joint position of the first trench 21 step and the device layer optical waveguide region by mask lithography, as shown in fig. 23; the mask lithography can refer to step 3).
7) Growing polysilicon 600 on the surface of the silicon substrate by an epitaxial process until the entire inverted ridge trench is filled, as shown in fig. 24;
8) high-temperature annealing is carried out, the properties of the epitaxial polysilicon are adjusted, and the defects are reduced so as to achieve low transmission loss; specifically, the chinese patent application No. CN201710254026.2 is referred to as an annealing condition parameter mentioned in the annealing process for increasing the crystallization rate of polysilicon ingot.
9) Planarizing the silicon substrate by Chemical Mechanical Polishing (CMP) to expose a clean device layer and finally forming an inverted ridge optical waveguide layer 4 in the optical coupling region 12, as shown in fig. 25; or mask photoetching is carried out to protect the epitaxial polysilicon in the optical coupling area by a mask, then the polysilicon is chemically etched by isotropy to realize the consistent height of each area on the surface of the wafer, and then the silicon substrate is flattened by CMP.
10) And manufacturing a silicon photofunctional structure on the device layer, and depositing a low-stress silicon oxide layer 200 with the thickness not more than 500nm on the surface of the functional structure area of the silicon photonics chip by a plasma deposition method to form an upper cladding layer 5, as shown in fig. 26. If the electrode is led out, an electrode window area needs to be etched, the specific process is not the core of the patent of the invention, and the specific process only refers to a semiconductor manufacturing process.
Example 2: a silicon photonic chip optical coupling structure is used for transmitting continuous light and comprises a silicon substrate 1, wherein a device layer of the silicon substrate 1 is provided with a silicon photonic chip functional structure area 11, and the silicon photonic chip functional structure area 11 is provided with an optical waveguide area 13 and an optical coupling area 12. The optical coupling region 12 is provided with an inverted ridge-shaped groove 2, and the optical coupling region 12 extends from the end face of the silicon substrate 1 to the optical waveguide region 13; follow 2 inner walls of ridge groove of falling are provided with the isolation layer 3 that the one deck is used for keeping apart the silicon of epitaxial polycrystalline silicon and substrate wafer, also regard as the lower cladding of falling ridge waveguide layer 4 simultaneously, the top that just is located isolation layer 3 in falling ridge groove 2 is provided with the ridge optical waveguide layer 4 of falling, the terminal surface and the optical fiber butt joint of the ridge optical waveguide layer 4 of falling, the other end and the regional 13 butt joints of device layer optical waveguide. The silicon substrate 1 is further provided with an upper cladding 5 covering the surfaces of the inverted ridge-shaped optical waveguide layer 4 and the silicon photonic chip functional structure region 11.
The inverted ridge-shaped groove 2 is provided with three layers of grooves from the surface of the silicon substrate 1 to the bottom, the grooves are a first groove 21, a second groove 22 and a third groove 23 from top to bottom in turn, the end face widths of the first groove 21, the second groove 22 and the third groove 23 are not less than the core diameter of an optical fiber, namely not less than 9 μm, the other end of the first groove 21 is butted with the device layer optical waveguide region 11, and the width of the joint with the device layer optical waveguide region 11 is equal to the width of the device layer optical waveguide region 13; the length of the first groove 21 is not less than 1000 μm, the length of the second groove 22 is not more than the length of the first groove 21, the length of the third groove 23 is not more than the length of the second groove 22, and the width of the end, close to the device layer optical waveguide region 11, of the second groove 22 is larger than the width of the end, close to the optical waveguide region 13, of the first groove 21; the width of the third trench 23 near the end of the device layer optical waveguide region 11 is greater than the width of the second trench 22 near the end of the optical waveguide region 13. The depth of the inverted ridge-shaped groove 2 is not less than 9 μm and not more than 15 μm, wherein the depth of the first groove 21 is not less than 3 μm and not more than 5 μm, and the depth of the second groove 22 is not less than 3 μm and not more than 5 μm.
The manufacturing method of the silicon photonic chip optical coupling structure comprises the following steps:
1) forming a silicon oxide layer 100 having a thickness of not more than 100nm on the device layer of the silicon substrate 1 by dry oxidation, as shown in fig. 8;
2) depositing a low stress silicon oxide layer 200 having a thickness of not more than 500nm on the silicon oxide layer 100 of step 1) by a plasma chemical vapor deposition method, as shown in fig. 9;
3) coating a layer of photoresist 300 as a mask on the low stress silicon oxide layer 200 as shown in fig. 10, and then forming a photoresist mask through an exposure and development process as shown in fig. 11;
removing the low stress silicon oxide layer 200 and the silicon oxide layer 100 exposed outside the mask by a mask photolithography process using a photoresist as a mask to define an upper ridge region shape 400 of the inverted ridge optical waveguide of the optical coupling region, as shown in fig. 12; removing the photoresist 300 on the surface using SPM (sulfuric acid and hydrogen peroxide), as shown in fig. 13; then, a first groove 21 of the inverted ridge optical waveguide is formed by etching downwards through a dry plasma etching process and by using the low-stress silicon oxide layer 200 as a mask, as shown in fig. 14;
4) depositing a low stress silicon oxide layer 200 with a thickness of not more than 500nm on the first trench by plasma chemical vapor deposition, as shown in fig. 15; then coating a layer of photoresist 300 on the low stress silicon oxide layer 200, as shown in fig. 16, forming a photoresist mask through an exposure and development process, as shown in fig. 17, and removing the low stress silicon oxide layer 200 and the silicon oxide layer 100 exposed outside the mask through a mask photolithography process to define the shape of the second ridge region 500 of the inverted ridge optical waveguide of the optical coupling region, as shown in fig. 18; then, removing the photoresist on the surface by using SPM (sulfuric acid and hydrogen peroxide), as shown in fig. 19, and then etching downward by using the low-stress silicon oxide layer 200 as a mask through a dry plasma etching process to form a second trench 22 of the inverted ridge optical waveguide, as shown in fig. 20; etching is performed in the same process as the second trench 22 to form a third trench 23 below the second trench 22, as shown in fig. 27;
5) dry oxidation to flatten and smooth the inverted ridge-shaped trench 2 formed by the above process; depositing a low-stress silicon oxide layer 200 with a thickness of no more than 500nm in the inverted ridge trench by plasma deposition, as shown in fig. 28;
6) removing the silicon oxide layer 100 and the low-stress silicon oxide layer 200 at the butt joint position of the first trench 21 step and the device layer optical waveguide region by mask lithography, as shown in fig. 29;
7) growing polysilicon 600 on the surface of the silicon substrate by an epitaxial process until the entire inverted ridge trench is filled, as shown in fig. 30;
8) high-temperature annealing is carried out, the properties of the epitaxial polysilicon are adjusted, and the defects are reduced so as to achieve low transmission loss;
9) planarizing the silicon substrate by Chemical Mechanical Polishing (CMP) to expose a clean device layer and finally forming an inverted ridge optical waveguide layer 4 in the optical coupling region 12, as shown in fig. 31;
10) and manufacturing a silicon photofunctional structure on the device layer, and depositing a low-stress silicon oxide layer 200 with the thickness not more than 500nm on the surface of the functional structure area of the silicon photonics chip by a plasma deposition method to form an upper cladding 5, as shown in FIG. 3. The rest is the same as example 1.
The invention is described above with reference to the accompanying drawings. It is to be understood that the specific implementations of the invention are not limited in this respect. Various insubstantial improvements are made by adopting the method conception and the technical scheme of the invention; the present invention is not limited to the above embodiments, and can be applied to other fields without modification.
Claims (10)
1. A silicon photonic chip optical coupling structure for alignment coupling of a silicon photonic chip and a single mode fiber or a laser chip comprises a silicon substrate (1); a silicon photonic chip functional structure region (11) is arranged on a device layer of the silicon substrate (1), and an optical waveguide region (13) and an optical coupling region (12) are arranged on the silicon photonic chip functional structure region (11); the method is characterized in that: the optical coupling region (12) is provided with an inverted ridge-shaped groove (2), and the optical coupling region (12) extends from the end face of the silicon substrate (1) to the optical waveguide region (13); follow the ridge groove (2) inner wall that falls is provided with one deck isolation layer (3), the top that just is located isolation layer (3) in the ridge groove (2) that falls is provided with ridge light wave guide layer (4), the terminal surface and the butt joint of optic fibre or laser chip of the ridge light wave guide layer (4) that fall, the other end and the regional (13) butt joint of optical waveguide.
2. The silicon photonics chip optical coupling structure of claim 1 wherein: the isolation layer (3) is made of low-stress silicon oxide, and the inverted ridge-shaped optical waveguide layer (4) is made of polycrystalline silicon.
3. The silicon photonics chip optical coupling structure of claim 1 wherein: the reverse ridge-shaped groove (2) is at least provided with two layers of grooves from the surface of the silicon substrate (1) to the bottom, a first groove (21) and a second groove (22) are sequentially arranged from top to bottom, the end face widths of the first groove (21) and the second groove (22) are not less than the core diameter of an optical fiber or the waveguide width of a laser chip, the other end of the first groove (21) is butted with the optical waveguide region (13), and the width of the joint of the first groove (21) and the optical waveguide region (13) is equal to the width of the optical waveguide of the device layer; the length of the second groove (22) is not more than that of the first groove (21), and the width of one end, close to the optical waveguide region (13), of the second groove (22) is larger than that of one end, close to the optical waveguide region (13), of the first groove (21).
4. The silicon photonics chip optical coupling structure of claim 1 wherein: the reverse ridge-shaped groove (2) is provided with more than three layers of grooves from the surface of a silicon substrate (1) to the bottom, a first groove (21) and a second groove (22) … … are sequentially formed from top to bottom, the length of the next layer of groove is not more than that of the last layer of groove, and the width of one end, close to a device layer optical waveguide region (11), of the second groove (22) to the Nth groove (2N) increases gradually layer by layer.
5. The silicon photonics chip optical coupling structure of claim 3 or 4 wherein: the depth of the inverted ridge-shaped groove (2) is 1-1.5 times of the core diameter of the optical fiber.
6. The silicon photonics chip optical coupling structure of claim 1 wherein: the silicon substrate (1) is also provided with an upper cladding (5) covering the surfaces of the inverted ridge-shaped optical waveguide layer (4) and the silicon photonic chip functional structure region (11);
the upper cladding (5) is made of low-stress silicon oxide.
7. The silicon photonics chip optical coupling structure of claim 1, wherein: the width of the inverted ridge trench (2) gradually narrows from the end surface of the silicon substrate (1) toward the optical waveguide region (13).
8. A manufacturing method of a silicon photonic chip optical coupling structure is characterized by comprising the following steps:
1) forming a silicon oxide layer on the silicon substrate by dry oxidation;
2) depositing a low-stress silicon oxide layer on the silicon oxide layer in the step 1) by a plasma chemical vapor deposition method;
3) defining the shape of an upper ridge region of the inverted ridge optical waveguide in the optical coupling region by mask photoetching, and then etching downwards by a dry plasma etching process to form a first groove of the inverted ridge optical waveguide;
4) defining the shape of a second layer of ridge region of the inverted ridge optical waveguide in the optical coupling region by mask photoetching, and then etching downwards by a dry plasma etching process to form a second groove of the inverted ridge optical waveguide; etching the third trench to the Nth trench in the same way as the second trench;
5) dry oxidation to smooth the inverted ridge trench formed by the above process; then depositing a layer of low-stress silicon oxide layer on the surface of the silicon substrate and in the inverted ridge-shaped groove by a plasma deposition method;
6) removing the low-stress silicon oxide layer at the butt joint position of the first groove step and the optical waveguide region of the device layer through mask photoetching; 7) growing polysilicon on the surface of the silicon substrate by an epitaxial process until the whole inverted ridge-shaped groove is filled;
8) high-temperature annealing is carried out, the properties of the epitaxial polysilicon are adjusted, and the defects are reduced so as to achieve low transmission loss;
9) planarizing the silicon substrate by Chemical Mechanical Polishing (CMP) to expose a clean device layer after CMP;
10) and manufacturing a silicon optical functional structure, finally forming a multilayer inverted ridge optical coupling structure in the optical coupling area, and depositing a low-stress silicon oxide layer on the surface of the functional structure area of the silicon photonic chip by a plasma deposition method to form an upper cladding.
9. The method of claim 8, wherein: and 5) removing the dry oxidation layer of the groove by diluted hydrofluoric acid HF after dry oxidation, and then performing dry oxidation until the side wall of the formed inverted ridge-shaped groove is smooth.
10. The method of claim 8, wherein: and 9) photoetching through a mask to protect the epitaxial polysilicon in the optical coupling area, then chemically etching the polysilicon through isotropy to realize the height consistency of all areas on the surface of the wafer, and then flattening the silicon substrate through CMP.
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