CN103035546A - Small-size bonding point double-line bonding method - Google Patents

Small-size bonding point double-line bonding method Download PDF

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Publication number
CN103035546A
CN103035546A CN2012105493580A CN201210549358A CN103035546A CN 103035546 A CN103035546 A CN 103035546A CN 2012105493580 A CN2012105493580 A CN 2012105493580A CN 201210549358 A CN201210549358 A CN 201210549358A CN 103035546 A CN103035546 A CN 103035546A
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China
Prior art keywords
line
bonding
size
chip
bonding point
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CN2012105493580A
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Chinese (zh)
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CN103035546B (en
Inventor
陈�光
孙永斌
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Kodenshi Corp
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Horizon Semiconductor (shenyang) Co Ltd
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Priority to CN201210549358.0A priority Critical patent/CN103035546B/en
Publication of CN103035546A publication Critical patent/CN103035546A/en
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Publication of CN103035546B publication Critical patent/CN103035546B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4941—Connecting portions the connecting portions being stacked
    • H01L2224/49429—Wedge and ball bonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector

Abstract

The invention belongs to the technical field of integrated circuit manufacture and particularly relates to a small-size bonding point double-line bonding method. The following steps can be carried out in sequence that a, bonding a first line (1), wherein a second bonding point (102) of the first bonding line (1) is arranged on a chip (3) and a line ball (101) of the first line is arranged on a substrate (4); b, bonding a second line (2), wherein a line ball (201) of the second line is arranged on the chip (3) and a second bonding point (202) of the second line (2) is arranged on the substrate (4) and the line ball (201) of the second line is bonded on the second bonding point (102) of the first bonding line. The small-size bonding point double-line bonding method is easy to operate, high in integrated circuit reliability, high in rate of finished products and capable of achieving small-size pad chip batch bonding.

Description

A kind of small size bonding point two-wire bonding method
Technical field
The invention belongs to the ic manufacturing technology field, relate in particular to a kind of small size bonding point two-wire bonding method.
Background technology
Progress along with integrated circuit technique, integrated level requirement to hybrid circuit is more and more high, and the function of chip constantly increases, and size is but more and more little, thereby cause pad shared area ratio in whole chip obviously to rise, this has brought difficulty just for normal two-wire bonding.Yet the key technology in the Bonding based semiconductor packaging technology, it directly affects reliability and the rate of finished products of integrated circuit.
Referring to shown in Figure 1, at present, the general side by side bonding pattern of two lines that adopts of conventional two-wire bonding technology, this just requires the pad size of thread ball position larger.Referring to Fig. 2, size P is exactly the minimum dimension of pad, considers the size of bonding tool (chopper among Fig. 2), and P is larger than 2 times of thread ball diameter.If pad size herein less than P, so just can't carry out the two-wire bonding.
Summary of the invention
The present invention is intended to overcome the deficiencies in the prior art part and provides a kind of simple to operate, and IC reliability and rate of finished products are high, can realize small size, the small size bonding point two-wire bonding method of pad chip batch bonding.
For achieving the above object, the present invention realizes like this.
A kind of small size bonding point two-wire bonding method can be implemented as follows successively.
A, bonding number one line; The second bonding point of number one line places on the chip; The thread ball of number one line places on the substrate.
B, No. second line of bonding; The thread ball of No. second line places on the chip, and the second bonding point of No. second line is placed on the substrate; The thread ball of No. second line is bonded on the second bonding point of number one line.
The present invention is simple to operate, and IC reliability and rate of finished products are high, can realize small size pad chip batch bonding.
Bonding position on the chip of the present invention, the second bonding point of the thread ball of No. second line and number one line stacks up and down, and the pad size that needs satisfies and is not less than the thread ball diameter and gets final product.Therefore, as long as pad size can carry out the single line bonding, just can carry out the two-wire bonding.Compare conventional two-wire bonding technology, the present invention can realize the two-wire bonding at less pad.As long as pad size can carry out the single line bonding, just can carry out the two-wire bonding.
Description of drawings
The invention will be further described below in conjunction with the drawings and specific embodiments.Protection scope of the present invention not only is confined to the statement of following content.
Fig. 1 is conventional two-wire bonding schematic diagram.
Fig. 2 is conventional two-wire bonding operation schematic diagram.
Fig. 3 is two-wire bonding operation vertical view of the present invention.
Fig. 4 is two-wire bonding operation end view of the present invention.
Among the figure: 1, number one line; 2, No. second line; 3, chip; 4, substrate; 5, thread ball; 6, the second bonding point of line; 7, chopper; 8, line; 102, the second bonding point of number one line; 101, the thread ball of number one line; 202, the second bonding point of No. second line; 201, the thread ball of No. second line.
Embodiment
As shown in the figure, suppose that the pad size on the chip is little, and the pad on the substrate is enough large, small size Pad two-wire bonding method can be implemented as follows successively.
A, bonding number one line 1; The second bonding point 102 of number one line places on the chip 3; The thread ball 101 of number one line places on the substrate 4.
B, No. second line 2 of bonding; The thread ball 201 of No. second line places on the chip 3, and the second bonding point 202 of No. second line is placed on the substrate 4; The thread ball 201 of No. second line is bonded on the second bonding point 102 of number one line.
The purpose of two-wire bonding is in order to improve the reliability of bonding, and is general for the product higher to reliability requirement.This is a kind of two-wire bonding method that is applicable to small size pad occasion, and the undersized pad of saying here generally refers to the pad bonding point on the chip namely on the chip.The present invention is applicable to gold ball bonding, copper ball bonding and similar bonding technology.
Be with being appreciated that, above about specific descriptions of the present invention, only for the present invention being described and being not to be subject to the described technical scheme of the embodiment of the invention, those of ordinary skill in the art is to be understood that, still can make amendment or be equal to replacement the present invention, to reach identical technique effect; Use needs as long as satisfy, all within protection scope of the present invention.

Claims (1)

1. a small size bonding point two-wire bonding method is characterized in that, implements successively as follows:
A, bonding number one line (1); Second bonding point (102) of number one line places on the chip (3); The thread ball of number one line (101) places on the substrate (4);
B, No. second line of bonding (2); The thread ball of No. second line (201) places on the chip (3), and second bonding point (202) of No. second line is placed on the substrate (4); The thread ball of No. second line (201) is bonded on second bonding point (102) of number one line.
CN201210549358.0A 2012-12-18 2012-12-18 A kind of small size bonding point two-wire bonding method Active CN103035546B (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
CN201210549358.0A CN103035546B (en) 2012-12-18 2012-12-18 A kind of small size bonding point two-wire bonding method

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CN103035546A true CN103035546A (en) 2013-04-10
CN103035546B CN103035546B (en) 2018-01-16

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105845655A (en) * 2016-03-24 2016-08-10 中国电子科技集团公司第二十九研究所 Method for performing ball welding on micro pad in superposing manner and micro pad superposed bonding structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0148883B1 (en) * 1995-05-17 1998-12-01 김광호 Semiconductor package using double wire bonding
US6189765B1 (en) * 1998-04-14 2001-02-20 Hyundai Electronics Industries Co., Ltd. Apparatus and method for detecting double wire bonding
KR20050048430A (en) * 2003-11-19 2005-05-24 앰코 테크놀로지 코리아 주식회사 Double wire bonding structure of semiconductor device
JP2008066370A (en) * 2006-09-05 2008-03-21 Yamaha Corp Wire bonding method
CN101552257A (en) * 2008-03-31 2009-10-07 恩益禧电子股份有限公司 Semiconductor device capable of switching operation modes
CN102437141A (en) * 2011-12-09 2012-05-02 天水华天科技股份有限公司 Dense-pitch small-pad copper-wire bonded single intelligent card (IC) chip packing piece and preparation method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0148883B1 (en) * 1995-05-17 1998-12-01 김광호 Semiconductor package using double wire bonding
US6189765B1 (en) * 1998-04-14 2001-02-20 Hyundai Electronics Industries Co., Ltd. Apparatus and method for detecting double wire bonding
KR20050048430A (en) * 2003-11-19 2005-05-24 앰코 테크놀로지 코리아 주식회사 Double wire bonding structure of semiconductor device
JP2008066370A (en) * 2006-09-05 2008-03-21 Yamaha Corp Wire bonding method
CN101552257A (en) * 2008-03-31 2009-10-07 恩益禧电子股份有限公司 Semiconductor device capable of switching operation modes
CN102437141A (en) * 2011-12-09 2012-05-02 天水华天科技股份有限公司 Dense-pitch small-pad copper-wire bonded single intelligent card (IC) chip packing piece and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105845655A (en) * 2016-03-24 2016-08-10 中国电子科技集团公司第二十九研究所 Method for performing ball welding on micro pad in superposing manner and micro pad superposed bonding structure
CN105845655B (en) * 2016-03-24 2018-05-04 中国电子科技集团公司第二十九研究所 Superposition carries out the method and microbonding disk superposition bonding structure of ball-shaped welded on microbonding disk

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Effective date of registration: 20180118

Address after: No. 16, No. four street, Shenyang economic and Technological Development Zone, Liaoning, Liaoning

Patentee after: Kodenshi Corp.

Address before: No. 16, No. 4 Street, Shenyang economic and Technological Development Zone, Liaoning, Liaoning

Patentee before: Horizon semiconductor (Shenyang) Co., Ltd.

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