CN103035523A - Transistor forming method - Google Patents
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- CN103035523A CN103035523A CN2011102980015A CN201110298001A CN103035523A CN 103035523 A CN103035523 A CN 103035523A CN 2011102980015 A CN2011102980015 A CN 2011102980015A CN 201110298001 A CN201110298001 A CN 201110298001A CN 103035523 A CN103035523 A CN 103035523A
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Abstract
A transistor forming method includes providing a substrate with surface material containing silicon and a grid electrode arranged on the surface, forming a lateral wall medium layer on the surface of the grid electrode and the exposed surface of the substrate, mingling carbon ions into the lateral wall medium layer, etching the lateral wall medium layer after mingling the carbon ions to form a carbon mingled lateral wall located on the lateral wall of the grid electrode, forming a source electrode and a drain electrode in the substrate on two sides of the grid, respectively forming a metal layer containing nickel on the surface of the source electrode, the drain electrode and the grid electrode and conducting annealing processing on the metal layers to enable the nickel, the silicon on the surface of the substrate and the silicon on the surface of the grid electrode to react to form a nickel silicide layer. By means of the transistor forming method, transistor reliability can be improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly a kind of Transistor forming method.
Background technology
The self-aligned silicide technology is that a kind of passing through forms metal silicide layer at gate electrode layer and source/drain surface, thereby reduces the technology of the resistance in gate electrode layer and source/drain region.Nickel, platinum, cobalt etc. all are the optional metal materials that forms described metal silicide layer.In being the patent of US 2010/0117238, publication number disclosed a kind of formation method of nickel silicide layer.
Fig. 1 to Fig. 3 is that prior art is passed through the cross-sectional view that nickel self-aligned silicide technology forms the process of nickel silicide layer.
At first as shown in Figure 1, substrate 001 is provided, described substrate 001 surface is formed with grid, described grid comprises grid oxic horizon 021 and the gate electrode layer 022 that is positioned at successively on the described substrate 001, and being positioned at the side wall 030 of described gate electrode layer 022 both sides, the material on described side wall 030 surface is silicon nitride.
As shown in Figure 2, in substrate 001 interior formation source, the drain electrode of described grid both sides.
As shown in Figure 3, form nickel dam at described substrate 001, described nickel dam covers surface and the grid of described source, drain electrode; Described nickel dam is annealed, and through described annealing, the silicon in the nickel in the nickel dam and the substrate 001 reacts and forms nickel silicide layer 051, and removes unreacted part in the nickel dam.
But find in practice, relatively poor by the transistorized reliability ratio that said method forms.
Summary of the invention
The problem that the present invention solves provides a kind of Transistor forming method, the poor problem of transistor reliability that forms to solve existing method.
For addressing the above problem, the invention provides a kind of Transistor forming method, comprising:
Substrate is provided, and described substrate surface has grid;
Sidewall at described grid forms the carbon dope side wall;
After forming described carbon dope side wall, formation source, drain electrode in the substrate of grid both sides;
In described source, drain surface, and gate surface forms nickel silicide layer.
Alternatively, the step that forms described carbon dope side wall comprises: form side wall medium layer, described side wall medium layer covers the surface of described grid and the exposure of described substrate; To described side wall medium layer Implantation ion, and carry out the first annealing in process and activate the carbon ion that mixes; After activating carbon ion, the described side wall medium layer of etching forms the side wall that is positioned at gate lateral wall.
Alternatively, the step that forms described carbon dope side wall comprises: form side wall medium layer, described side wall medium layer covers the surface of described grid and the exposure of described substrate; The described side wall medium layer of etching forms the side wall that is positioned at gate lateral wall; To described side wall Implantation ion, and carry out the first annealing in process and activate the carbon ion that mixes.
Alternatively, described side wall medium layer comprises silicon dioxide layer and the silicon nitride layer that forms successively.
Alternatively, the width of described side wall is the 150-400 dust.
Alternatively, described silicon nitride layer is to adopt disilicone hexachloride for the forerunner, forms by low-pressure chemical vapor deposition process.
Alternatively, the thickness of described silicon nitride layer is the 150-300 dust.
What alternatively, the Implantation ion adopted is ion implantation technology or plasma doping technique.
Alternatively, adopt the technological parameter of ion implantation technology Implantation ion to be: Implantation Energy is 1-5keV, and implantation dosage is the 5E14-5E15/ square centimeter.
Alternatively, described the first annealing in process adopts spike annealing technique, and annealing temperature is 800-1000 degree centigrade, and anneal gas is the mist of nitrogen or nitrogen and helium.
Alternatively, described the first annealing in process adopts Millisecond annealing technique, and annealing temperature is 1100-1300 degree centigrade, and the annealing duration is the 0.25-20 millisecond.
Alternatively, the formation technique of described nickel silicide layer comprises: at the forming metal layer on surface that described grid, side wall and substrate expose, described metal level is nickeliferous; Described metal level is carried out annealing in process, and the silicon materials in nickel and substrate and the grid react in annealing process, form nickel silicide layer.
Alternatively, described annealing in process comprises the second annealing in process and the 3rd annealing in process.
Alternatively, described the second annealing is immersion annealing, and annealing temperature is 220-320 degree centigrade, and the annealing duration is 30-90 second.
Alternatively, described the 3rd annealing is Millisecond annealing, and annealing temperature is 1100-1300 degree centigrade, and the annealing duration is the 0.25-20 millisecond.
Alternatively, described the second annealing is the low temperature spike annealing, and annealing temperature is 350-550 degree centigrade, and the annealing duration is 0-60 second.
Alternatively, immersion annealing is adopted in described the second annealing, and annealing temperature is 350-450 degree centigrade, and the annealing duration is 20-90 second.
Alternatively, the material of described metal level also comprises platinum.
Embodiments of the invention reduce to form after the side wall by mix carbon atom in side wall, form etching technics in the technical process before the nickel silicide layer to the etching speed of side wall, thereby reduce the loss amount of lateral wall width in the described etching technics.And the width of side wall is larger, and the nickel silicide layer of follow-up formation corrodes the impact of transistor reliability just less to channel region.
Further, in the embodiments of the invention, form described nickel silicide layer by twice annealing, the main component of described nickel silicide layer is NiSi, and the resistivity of NiSi material is little, Heat stability is good, thus be conducive to improve transistorized performance.
Description of drawings
Fig. 1 to Fig. 3 is the cross-sectional view of existing transistor forming process;
Fig. 4 (a) is the probability of occurrence schematic diagram of the different leakage currents of transistor with Fig. 4 (b);
Fig. 5 is the schematic flow sheet of the Transistor forming method that provides of first embodiment of the invention;
Fig. 6 to Figure 12 is the cross-sectional view of the transistor forming process that provides of the first embodiment of the present invention;
Figure 13 is the schematic flow sheet of the Transistor forming method that provides of second embodiment of the invention;
Figure 14 to Figure 16 is the cross-sectional view of the transistor forming process that provides of the second embodiment of the present invention.
Embodiment
By background technology as can be known, the transistorized reliability ratio of prior art formation is relatively poor.Please refer to Fig. 3, the inventor studies for the problems referred to above, discovery is in the process to nickel dam annealing formation nickel silicide layer 051, nickel in the nickel dam can spread to channel region, and react with the silicon materials of channel region, so that formed nickel silicide layer 051 corrodes to channel region in the annealing process, cause transistorized reliability to reduce.
Further research is found, the width of side wall is larger, and nickel silicide layer corrodes less on the impact of transistor reliability to channel region.Please refer to Fig. 4, the width of side wall is the 150-200 dust among Fig. 4 (a), abscissa is the leakage current between leak in the source among Fig. 4 (a), ordinate is in the measuring process repeatedly, measurement result is the probability of corresponding leakage current, wherein is corresponding is to adopt the immersion low temperature annealing process to form transistorized nickel silicide layer, zero correspondence be to adopt laser annealing technique to form nickel silicide layer in the transistor; The width of side wall is the 250-400 dust among Fig. 4 (b), abscissa is the leakage current between leak in the source among Fig. 4 (b), ordinate is in the measuring process repeatedly, measurement result is the probability of corresponding leakage current, wherein is corresponding is to adopt a step immersion low temperature annealing process and a step laser annealing technique to form transistorized nickel silicide layer, zero correspondence be to adopt two step laser annealing techniques to form nickel silicide layers in the transistor.Comparison diagram 4 (a) and Fig. 4 (b), in the situation that transistorized side wall is little, the probability that leakage current occurs more easily is subjected to nickel silicide layer to form the impact of technique, and namely transistorized side wall is less, and transistorized reliability is lower.
But in actual process, also need to carry out repeatedly wet etching and dry etch process at the formation side wall to forming between the nickel silicide layer.Such as, after forming side wall, adopt first dry etch process in the Semiconductor substrate of described side wall both sides, to form the U-shaped groove; Adopt again the whether sidewall of the described U-shaped groove of etching of hydrofluoric acid or phosphoric acid or potassium hydroxide, form the groove with sigma shape.And before forming nickel dam, adopt hydrofluoric acid to remove the oxide layer of substrate surface.In described etching technics, because the solution such as hydrofluoric acid are excessive to the etching speed of side wall, can cause the width of side wall obviously to reduce, affect the transistorized reliability of follow-up formation; Need to set according to arts demand because of the width of side wall again, so can not increase arbitrarily in order to improve transistorized reliability the width of side wall.
In order further to illustrate spirit of the present invention and essence, hereinafter in conjunction with the accompanying drawings and embodiments, the present invention will be described in detail.
The first embodiment
The schematic flow sheet of the Transistor forming method that Fig. 5 first embodiment of the present invention provides comprises:
Step S101 provides substrate, and the material of described substrate surface is siliceous, and described substrate surface has grid;
Step S102 forms side wall medium layer on the surface of described grid and the surface of substrate exposure;
Step S103 mixes carbon ion to described side wall medium layer;
Step S104, mix carbon ion after, the described side wall medium layer of etching forms the side wall of the carbon dope be positioned at gate lateral wall;
Step S105, form described carbon dope side wall after, formation source, drain electrode in the substrate of grid both sides;
Step S106, in described source, drain surface, and gate surface formation metal level, described metal level is nickeliferous;
Step S107 carries out annealing in process to described metal level, and the silicon of nickel and substrate surface and the silicon of gate surface react, and forms nickel silicide layer.
Fig. 6 to Figure 12 is the cross-sectional view of the transistor forming process that provides of first embodiment of the invention.
With reference to figure 6, substrate 100 is provided, the material on described substrate 100 surfaces is siliceous, and described substrate surface has grid, and described grid comprises gate dielectric layer 110 and the gate electrode layer 120 that is formed on successively substrate surface.
Described substrate 100 is silicon substrates, perhaps the SOI substrate.
The material of described gate dielectric layer 110 is silicon dioxide, and the material of described gate electrode layer 120 is polysilicons.
With reference to figure 7, form side wall medium layer 130 on the surface of described grid and the surface of substrate 100 exposures.
The thickness of described side wall medium layer 130 is 300-600 dusts, described side wall medium layer 130 comprises the silicon dioxide layer (not shown) on the surface that is formed on described grid and substrate 100 exposures, and the silicon nitride layer (not shown) that is formed on described silicon dioxide layer surface.
Described silicon nitride layer is to adopt disilicone hexachloride (HCD, Hexachlorodisilane) for the forerunner, forms by low-pressure chemical vapor deposition process.The thickness of described silicon nitride layer is the 150-300 dust.
Also be formed with take grid as mask in the described substrate 100, to the formed shallow doped source of substrate 100 doping, drain electrode.
With reference to figure 8, mix carbon ion to described side wall medium layer 130.
Adopt Implantation or plasma doping technique to described side wall medium layer 130 Implantation ions, behind the Implantation ion, also comprise described side wall medium layer is carried out the first annealing in process, activate the carbon ion that mixes, in described annealing process, the silicon nitride reaction in carbon ion and the silicon nitride layer forms new material.Described annealing process is spike annealing technique or Millisecond annealing technique.
In the present embodiment, adopt ion implantation technology to described side wall medium layer 130 Implantation ions, concrete technological parameter is: Implantation Energy is 1-5keV, and implantation dosage is the 5E14-5E15/ square centimeter.Described Implantation Energy is too small, and the degree of depth that carbon ion is injected in the silicon carbide layer may be dark not; Described Implantation Energy is excessive, and carbon ion injects the degree of depth may be excessively dark, breaks away from silicon nitride layer.Described implantation dosage is too small may to be not enough to be reduced in because the amount of carbon ion is too small in the subsequent etching technique etching speed to silicon nitride layer; The dosage that injects is excessive, can increase process costs, and can reduce process efficiency.
In one embodiment of the present of invention, described the first annealing in process adopts spike annealing technique, and annealing temperature is 800-1000 degree centigrade, and anneal gas is the mist of nitrogen or nitrogen and helium.
Among the another one embodiment of the present invention, described the first annealing in process adopts Millisecond annealing technique, and annealing temperature is 1100-1300 degree centigrade, and the annealing duration is the 0.25-20 millisecond.
Table 1 is forward and backward for carbon ion injects, and hydrofluoric acid is to the etch rate of silicon nitride layer
Table 1
In the table 1, the content of hydrofluoric acid refers to the volume ratio that water and mass concentration are 49% hydrofluoric acid, classify example as with secondary series and the 3rd, " 950 ℃ of spike annealings " refers to that the side wall medium layer of not mixing is carried out annealing temperature is 950 ℃ spike annealing, accordingly, content is that 100: 1 hydrofluoric acid is 5.44 A/mins of clocks to the etching speed through the side wall medium layer of 950 ℃ spike annealing, and content is that 500: 1 hydrofluoric acid is 21.44 A/mins of clocks to the etching speed through the side wall medium layer of 950 ℃ spike annealing." C
+, 3keV, 950 ℃ of spike annealings of 1E15 " refer to take implant energy as 3keV, dopant dose is that the technique of 1E15 is mixed carbon ion to side wall medium layer, and carries out spike annealing under 950 ℃ temperature.The implication of other projects by that analogy in the table 1.
Table 1 illustrates through carbon ion and injects exemplarily take hydrofluoric acid as example, and the first annealing in process, and wet-etching technology descends to the etching speed of described side wall medium layer 130.
Same reason, through described doping treatment and the first annealing in process, dry etch process also can descend to the etching speed of silicon nitride layer.
With reference to figure 9, mix carbon ion after, the described side wall medium layer of etching forms the side wall 140 be positioned at gate lateral wall, the width of described side wall 140 is d.
The scope of the width d of described side wall 140 is the 150-400 dust.
Because side wall 140 is identical with the material of side wall medium layer, so through after aforementioned doping treatment and the first annealing in process, follow-up wet-etching technology descends to the etching speed of described side wall medium layer.Thereby be conducive to reduce the loss of the width d of side wall 140 in the etching technics, further be conducive to improve the transistorized reliability of follow-up formation.
Described etching technics can adopt dry etch process, is well known to those skilled in the art because the etching side wall medium layer forms the technique of side wall, therefore be not described in detail in this.
With reference to Figure 10, form described carbon dope side wall 140 after, substrate 100 interior formation sources, drain electrode (not marking) in the grid both sides.
The step of formation source, drain electrode comprises:
Adopt dry etch process in the Semiconductor substrate of described grid both sides, to form the U-shaped groove;
Adopt wet-etching technology, such as take hydrofluoric acid as etching solution, the described U-shaped groove of etching forms the groove of sigma shape;
Form the epitaxial loayer of filling full described groove, under the transistorized situation of PMOS, the material of described epitaxial loayer is SiGe;
To described epitaxial loayer dopant implant ion, and anneal formation source, drain electrode.
In the etching technics of the groove of above-mentioned formation U-shaped groove and sigma shape, because side wall has mixed carbon ion, so described etching technics is slow to the etching speed of side wall, the consumption of side wall thicknesses is few.Thereby be conducive to improve formed transistorized reliability.
With reference to Figure 11, in described source, drain surface, and gate surface forms metal level 150, and described metal level 150 is nickeliferous.
Before forming metal level nickel, can adopt acid solution, such as the described substrate surface of hf etching, the oxide layer of removing substrate surface and forming because contact with gas in the process environments.Because side wall has mixed carbon ion, so in the etching technics of described removal substrate surface oxide layer, the decrease of side wall thicknesses can be ignored.
In the present embodiment, the material of described metal level 150 is nickel, and the formation technique of described metal level 150 is physical gas-phase deposition.
In other embodiments of the invention, the material of described metal level 150 can also comprise at least a material of selecting from Ta, Zr, Ti, Hf, W, Co, Pt, Mo, Pd, V and Nb.After adding other metals formation nickel alloy layers in the nickel, can improve the thermal stability of the nickel alloy silicide layer that in technique subsequently, will form.The material of described metal level 150 is that the benefit of nickel platinum alloy also comprises, platinum can stop the diffusion of nickel in described substrate.
In the present embodiment, the thickness range of described metal level 150 is the 100-200 dust.
Further, can form cap layer (not shown) at metal level 150, described cap layer can be made of titanium nitride.In this case, titanium nitride layer is used for preventing metal level 150 oxidations.Herein, the formation of cap layer is not given unnecessary details.
With reference to Figure 12, described metal level is carried out annealing in process, nickel and the silicon on substrate 100 surfaces and the silicon of gate surface react, and form nickel silicide layer 160, and adopt wet-etching technology to remove unreacted metal level.
In the present embodiment, described annealing in process comprises the second annealing in process and the 3rd annealing in process.
Described the second annealing is immersion annealing, and annealing temperature is 220-320 degree centigrade, and the annealing duration is 30-90 second.
In the second annealing process, the nickle atom in the metal level on source electrode surface and the reaction of the silicon atom in the source electrode; Silicon atom reaction in nickle atom in the metal level of drain surface and the drain electrode; Be arranged in the silicon atom reaction of nickle atom and the gate electrode layer 120 of the metal level on the described gate electrode layer 120, respectively the corresponding Ni that forms
2The Si layer.
Wherein, at described the second During Annealing, side wall 140 can with the reaction of described metal level, and the metal level that covers the major part at described substrate 100 surfaces and gate electrode layer 120 tops does not react with silicon atom.After carrying out described the second annealing, unreacted metal level still remains in the surface of substrate 100, gate electrode layer 120 tops and side wall 140.So after the second annealing, the unreacted metal level of selective removal.Described removal method is that wet method is removed.Described wet method is removed and is utilized the mixture of sulfuric acid and hydrogen peroxide to remove unreacted metal level, further, can also remove cap layer (not shown) when removing described unreacted metal level.
Then, to formed Ni
2The Si layer carries out the 3rd annealing, and described the 3rd annealing is Millisecond annealing, and annealing temperature is 1100-1300 degree centigrade, and the annealing duration is the 0.25-20 millisecond.
In another embodiment of the present invention, described the 3rd annealing is the low temperature spike annealing, and annealing temperature is 350-550 degree centigrade, and the annealing duration is 0-60 second.
In another embodiment of the present invention, immersion annealing is adopted in described the 3rd annealing, and annealing temperature is 350-450 degree centigrade, and the annealing duration is 20-90 second.
Through described the 3rd annealing process, the nickel in the described metal level and pasc reaction form the NiSi layer, and the resistivity of described NiSi layer is little, good stability.
The present embodiment reduces to form after the side wall by mix carbon atom in side wall, forms etching technics in the technical process before the nickel silicide layer to the etching speed of side wall, thereby reduces the loss amount of lateral wall width in the described etching technics.And the width of side wall is larger, and the nickel auride of follow-up formation corrodes the impact of transistor reliability just less to channel region.
Further, in the present embodiment, mix carbon ion to side wall medium layer first, the described side wall medium layer of etching forms side wall again.In the process of carbon dope ion, be positioned at the side wall medium layer of grid both sides substrate surface to the substrate formation protection of correspondence position, prevent that carbon ion is injected in the substrate of correspondence position.If carbon ion is injected in the substrate of correspondence position, can increase the subsequent etching substrate and form groove, and the difficulty of removing the substrate surface oxide.
The second embodiment
Figure 13 is the schematic flow sheet of the Transistor forming method that provides of second embodiment of the invention, comprising:
Step S201 provides substrate, and the material of described substrate surface is siliceous, and described substrate surface has grid;
Step S202 forms side wall medium layer on the surface of described grid and the surface of substrate exposure, and the described side wall medium layer of etching, forms the side wall that is positioned at gate lateral wall;
Step S203 is to described side wall Implantation ion;
Step S204, behind the Implantation ion, formation source, drain electrode in the substrate of grid both sides;
Step S205, in described source, drain surface, and gate surface formation metal level, described metal level is nickeliferous;
Step S206 carries out annealing in process to described metal level, and the silicon of nickel and substrate surface and the silicon of gate surface react, and forms nickel silicide layer.
Figure 14 to Figure 16 is the cross-sectional view of the transistor forming process that provides of second embodiment of the invention.
With reference to Figure 14, substrate 200 is provided, the material on described substrate 200 surfaces is siliceous, and described substrate surface has grid, and described grid comprises gate dielectric layer 210 and the gate electrode layer 220 that is formed on successively substrate surface.
Described substrate 200 is silicon substrates, perhaps the SOI substrate.
The material of described gate dielectric layer 210 is silicon dioxide, and the material of described gate electrode layer 220 is polysilicons.
With reference to Figure 15, form side wall medium layer on the surface of described grid and the surface of substrate 200 exposures, and the described side wall medium layer of etching, form the side wall 230 that is positioned at gate lateral wall.
The thickness of described side wall medium layer is the 300-600 dust, described side wall medium layer comprises the silicon dioxide layer (not shown) on the surface that is formed on described grid and substrate 200 exposures, and the silicon nitride layer (not shown) that is formed on described silicon dioxide layer surface.
Described silicon nitride layer is to adopt disilicone hexachloride for the forerunner, forms by low-pressure chemical vapor deposition process.The thickness of described silicon nitride layer is the 150-300 dust.
Also be formed with take grid as mask in the described substrate 200, to the formed shallow doped source of substrate 200 doping, drain electrode.
With reference to Figure 16, on the surface that described substrate 200 exposes, and form photoresist layer 240 on the surface of grid exposure, then take described photoresist layer 240 as mask, to described side wall 230 Implantation ions.
Adopt Implantation or plasma doping technique to described side wall 230 Implantation ions, behind the Implantation ion, also comprise described side wall 230 is carried out the first annealing in process, activate the carbon ion that mixes, in described annealing process, silicon nitride bonding in carbon ion and the silicon nitride layer forms new phase.Described annealing process is spike annealing technique or Millisecond annealing technique.
In the present embodiment, adopt ion implantation technology to described side wall 230 Implantation ions, concrete technological parameter is: Implantation Energy is 1-5keV, and implantation dosage is the 5E14-5E15/ square centimeter.Described Implantation Energy is too small, and the degree of depth that carbon ion is injected in the silicon carbide layer may be dark not; Described Implantation Energy is excessive, and carbon ion injects the degree of depth may be excessively dark, breaks away from silicon nitride layer.Described implantation dosage is too small may to be not enough to be reduced in because the amount of carbon ion is too small in the subsequent etching technique etching speed to silicon nitride layer; The dosage that injects is excessive, can increase process costs, and can reduce process efficiency.
In one embodiment of the present of invention, described the first annealing in process adopts spike annealing technique, and annealing temperature is 800-1000 degree centigrade, and anneal gas is nitrogen or nitrogen and helium.
Among the another one embodiment of the present invention, described the first annealing in process adopts Millisecond annealing technique, and annealing temperature is 1100-1300 degree centigrade, and the annealing duration is the 0.25-20 millisecond.
Table 2 is forward and backward for carbon ion injects, and hydrofluoric acid is to the etch rate of side wall 230
Table 2
In the table 2, the content of hydrofluoric acid refers to the volume ratio that water and concentration are 49% hydrofluoric acid, classify example as with secondary series and the 3rd, " 950 ℃ of spike annealings " refers to that side wall 230 is carried out annealing temperature is 950 ℃ spike annealing, but do not mix, accordingly, content is that 100: 1 hydrofluoric acid is 5.44 A/mins of clocks to the etching speed through the side wall 230 of 950 ℃ spike annealing, and content is that 500: 1 hydrofluoric acid is 21.44 A/mins of clocks to the etching speed through the side wall 230 of 950 ℃ spike annealing." C
+, 3keV, 950 ℃ of spike annealings of 1E15 " refer to take implant energy as 3keV, dopant dose is that the technique of 1E15 is mixed carbon ion to side wall 230, and carries out spike annealing under 950 ℃ temperature.The implication of other projects by that analogy in the table 1.
Table 2 illustrates through carbon ion and injects exemplarily take hydrofluoric acid as example, and the first annealing in process, and wet-etching technology descends to the etching speed of described side wall 230.
Same reason, through described doping treatment and the first annealing in process, dry etch process also can descend to the etching speed of described side wall 230.
So after aforementioned doping treatment and the first annealing in process, wet-etching technology descends to the etching speed of described side wall.Thereby be conducive to reduce the loss of the width of side wall 230 in the etching technics, further be conducive to improve the transistorized reliability of follow-up formation.
Follow-up take described side wall 230 as mask to substrate dopant implant ion, formation source, drain electrode, and the technique that forms nickel silicide layer on the surface of described source, drain and gate can be with reference to the step S105 of the first embodiment to step S107, and Figure 10 to Figure 12, no longer describe in detail in the present embodiment.
Embodiments of the invention reduce to form after the side wall by mix carbon atom in side wall, and the etching technics that forms in the nickel silicide layer technical process before is little to the etching speed of side wall, thereby reduce the loss amount of lateral wall width in the described etching technics.And the width of side wall is larger, and the nickel auride of follow-up formation corrodes the impact of transistor reliability just less to channel region.
Further, in the embodiments of the invention, form described nickel silicide layer by twice annealing, the main component of described nickel silicide layer is NiSi, and the resistivity of NiSi material is little, Heat stability is good, thus be conducive to improve transistorized performance.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (18)
1. a Transistor forming method is characterized in that, comprising:
Substrate is provided, and described substrate surface has grid;
Sidewall at described grid forms the carbon dope side wall;
After forming described carbon dope side wall, formation source, drain electrode in the substrate of grid both sides;
In described source, drain surface, and gate surface forms nickel silicide layer.
2. Transistor forming method as claimed in claim 1 is characterized in that, the step that forms described carbon dope side wall comprises: form side wall medium layer, described side wall medium layer covers the surface of described grid and the exposure of described substrate; To described side wall medium layer Implantation ion, and carry out the first annealing in process and activate the carbon ion that mixes; After activating carbon ion, the described side wall medium layer of etching forms the side wall that is positioned at gate lateral wall.
3. Transistor forming method as claimed in claim 1 is characterized in that, the step that forms described carbon dope side wall comprises: form side wall medium layer, described side wall medium layer covers the surface of described grid and the exposure of described substrate; The described side wall medium layer of etching forms the side wall that is positioned at gate lateral wall; To described side wall Implantation ion, and carry out the first annealing in process and activate the carbon ion that mixes.
4. Transistor forming method as claimed in claim 2 or claim 3 is characterized in that, described side wall medium layer comprises silicon dioxide layer and the silicon nitride layer that forms successively.
5. Transistor forming method as claimed in claim 1 is characterized in that, the width of described side wall is the 150A-400 dust.
6. Transistor forming method as claimed in claim 4 is characterized in that, described silicon nitride layer is to adopt disilicone hexachloride for the forerunner, forms by low-pressure chemical vapor deposition process.
7. Transistor forming method as claimed in claim 4 is characterized in that, the thickness of described silicon nitride layer is the 150-300 dust.
8. Transistor forming method as claimed in claim 2 or claim 3 is characterized in that, what the Implantation ion adopted is ion implantation technology or plasma doping technique.
9. Transistor forming method as claimed in claim 8 is characterized in that, adopt the technological parameter of ion implantation technology Implantation ion to be: Implantation Energy is 1-5keV, and implantation dosage is the 5E14-5E15/ square centimeter.
10. Transistor forming method as claimed in claim 2 or claim 3 is characterized in that, described the first annealing in process adopts spike annealing technique, and annealing temperature is 800-1000 degree centigrade, and anneal gas is the mist of nitrogen or nitrogen and helium.
11. Transistor forming method is characterized in that as claimed in claim 2 or claim 3, described the first annealing in process adopts Millisecond annealing technique, and annealing temperature is 1100-1300 degree centigrade, and the annealing duration is the 0.25-20 millisecond.
12. Transistor forming method as claimed in claim 1 is characterized in that, the formation technique of described nickel silicide layer comprises: at the forming metal layer on surface that described grid, side wall and substrate expose, described metal level is nickeliferous; Described metal level is carried out annealing in process, and the silicon materials of nickel and substrate and grid react in annealing process, form nickel silicide layer.
13. Transistor forming method as claimed in claim 12 is characterized in that, described annealing in process comprises the second annealing in process and the 3rd annealing in process.
14. Transistor forming method as claimed in claim 13 is characterized in that, described the second annealing is immersion annealing, and annealing temperature is 220-320 degree centigrade, and the annealing duration is 30-90 second.
15. Transistor forming method as claimed in claim 13 is characterized in that, described the 3rd annealing is Millisecond annealing, and annealing temperature is 700-950 degree centigrade, and the annealing duration is the 0.25-20 millisecond.
16. Transistor forming method as claimed in claim 13 is characterized in that, described the 3rd annealing is the low temperature spike annealing, and annealing temperature is 350-550 degree centigrade.
17. Transistor forming method as claimed in claim 13 is characterized in that, described the 3rd annealing is immersion annealing, and annealing temperature is 350-450 degree centigrade, and the annealing duration is 20-90 second.
18. Transistor forming method as claimed in claim 12 is characterized in that, the material of described metal level also comprises platinum.
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| CN104064521A (en) * | 2014-07-03 | 2014-09-24 | 上海华力微电子有限公司 | Semiconductor technology method and semiconductor structure |
| CN104409351A (en) * | 2014-11-25 | 2015-03-11 | 上海集成电路研发中心有限公司 | PMOS (P-channel metal oxide semiconductor) transistor forming method |
| CN104616979A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device |
| CN105448736A (en) * | 2014-09-26 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Formation method of transistor |
| CN105529265A (en) * | 2014-09-30 | 2016-04-27 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and MOS transistor manufacturing method |
| CN103996619B (en) * | 2014-06-09 | 2017-01-18 | 上海华力微电子有限公司 | Method for solving side wall deposition problem of germanium-silicon selective epitaxy through nitrogen implanting |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104616979A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device |
| CN104616979B (en) * | 2013-11-05 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN103996619B (en) * | 2014-06-09 | 2017-01-18 | 上海华力微电子有限公司 | Method for solving side wall deposition problem of germanium-silicon selective epitaxy through nitrogen implanting |
| CN104064521A (en) * | 2014-07-03 | 2014-09-24 | 上海华力微电子有限公司 | Semiconductor technology method and semiconductor structure |
| CN104064521B (en) * | 2014-07-03 | 2017-02-15 | 上海华力微电子有限公司 | Semiconductor technology method and semiconductor structure |
| CN105448736A (en) * | 2014-09-26 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Formation method of transistor |
| CN105448736B (en) * | 2014-09-26 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN105529265A (en) * | 2014-09-30 | 2016-04-27 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and MOS transistor manufacturing method |
| CN104409351A (en) * | 2014-11-25 | 2015-03-11 | 上海集成电路研发中心有限公司 | PMOS (P-channel metal oxide semiconductor) transistor forming method |
| CN104409351B (en) * | 2014-11-25 | 2018-04-06 | 上海集成电路研发中心有限公司 | The forming method of PMOS transistor |
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