CN103014656B - Nickel silicide layer forming method and semiconductor device forming method - Google Patents
Nickel silicide layer forming method and semiconductor device forming method Download PDFInfo
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- CN103014656B CN103014656B CN201110298403.5A CN201110298403A CN103014656B CN 103014656 B CN103014656 B CN 103014656B CN 201110298403 A CN201110298403 A CN 201110298403A CN 103014656 B CN103014656 B CN 103014656B
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Abstract
The invention discloses a nickel silicide layer forming method and a semiconductor device forming method, wherein the nickel silicide layer forming method comprises the following steps of: providing a substrate, and forming a dinickel silicide layer on the surface of the substrate; forming a hydrogen ion containing silicon nitride layer on the surface of the dinickel silicide layer; and carrying out secondary annealing treatment on the dinickel silicide layer so as to form a nickel silicide layer. Before the step of carrying out secondary annealing treatment on the dinickel silicide layer so as to form a nickel silicide layer, a hydrogen ion containing silicon nitride layer is formed on the surface of the dinickel silicide layer, and in the process of carrying out secondary annealing treatment, hydrogen ions in the silicon nitride layer are diffused into the dinickel silicide layer, so that the finally formed nickel silicide layer internally contains hydrogen ions, therefore, the resistance of the nickel silicide layer can be effectively decreased, and the RC delay of a circuit can be reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of nickel silicide layer formation method and method for forming semiconductor devices.
Background technology
Along with semiconducter device integrated level constantly increases, the critical size relevant to semiconducter device constantly reduces, the dead resistance of device and the impact of stray capacitance on device performance become more and more significant, RC (resistance, electric capacity) postpones to become increasing, therefore, the interconnection structure of low-resistivity becomes the key element manufacturing highly intergrated semiconductor device.Metal silicide and self-aligned metal silicate and formation process have been widely used in reducing the resistance of the grid of MOS transistor, source electrode, drain electrode, comprise sheet resistance and contact resistance, and then reduce RC time of lag.In existing self-aligned metal silicate technology, the normal nickel silicide that adopts is as metal silicide.Due to utilize described nickel silicide to be formed gate contact region, source contact area, drain contact region, owing to having less contact resistance and sheet resistance, less silicon consumption, easily reaching narrower live width, nickel silicide is regarded as a kind of ideal metal silicide.
But the size of semiconducter device is also constantly reducing, the resistance of nickel silicide layer is also more and more significant on the impact of device electric property, and the resistance how reducing nickel silicide layer becomes more and more important.In the prior art, form the technique of nickel silicide layer and comprise: provide substrate, be formed with ion doped region in described substrate, described ion doped region is the source electrode of MOS transistor, drain electrode and/or grid; Nickel metal layer is formed on surface, described ion doped region; Twice annealing process is carried out to described nickel metal layer, forms nickel silicide layer.Because described nickel metal layer surface is easy to oxidized formation nickel oxide layer, described nickel oxide layer can improve the sheet resistance of the final nickel silicide layer formed, those skilled in the art isolate described nickel metal layer and ambient atmos by forming titanium nitride/titanium on described nickel metal layer surface, prevent the oxidized formation nickel oxide layer in described nickel metal layer surface.
More formation methods about low-resistance nickel silicide layer please refer to the american documentation literature that publication number is US 2005/0176247A1.
But the method for prior art still can not reduce the resistance of nickel silicide layer effectively.
Summary of the invention
The problem that the present invention solves is to provide a kind of nickel silicide layer formation method and method for forming semiconductor devices, can effectively reduce the resistance of nickel silicide layer, and the RC reducing circuit postpones.
For solving the problem, technical solution of the present invention provides a kind of nickel silicide layer formation method, comprising:
Substrate is provided, forms silication two nickel dam at described substrate surface;
Formed containing hydrionic silicon nitride layer on described silication two nickel dam surface;
Second anneal is carried out to described silication two nickel dam, forms nickel silicide layer.
Optionally, described is 1E15atom/cm containing hydrionic content range in hydrionic silicon nitride layer
2~ 1E25atom/cm
2.
Optionally, form the described technique containing hydrionic silicon nitride layer and comprise: utilize chemical vapor deposition method to form silicon nitride layer on described silication two nickel dam surface, Hydrogen implantation is carried out to described silicon nitride layer and is formed containing hydrionic silicon nitride layer.
Optionally, forming the described technique containing hydrionic silicon nitride layer is plasma enhanced chemical vapor deposition.
Optionally, the concrete technology parameter utilizing plasma enhanced chemical vapor deposition to form described silicon nitride layer comprises: substrate temperature range is 300 DEG C ~ 500 DEG C, and air pressure range is 1torr ~ 10torr, and the power range of electrode is 50W ~ 400W.
Optionally, the reactant gases utilizing plasma enhanced chemical vapor deposition to form described silicon nitride layer comprises ammonia and silane or comprises nitrogen and silane or comprise ammonia, nitrogen and silane.
Optionally, when the reactant gases forming described silicon nitride layer comprises ammonia, nitrogen and silane, the flow rate of described silane is 50sccm ~ 200sccm, and the flow rate of described ammonia is 200sccm ~ 1000sccm, and the flow rate of described nitrogen is 500sccm ~ 2000sccm.Optionally, the described thickness range containing hydrionic silicon nitride layer is
Optionally, the method forming described silication two nickel dam comprises: formed containing nickel metal layer at described substrate surface, forms sealing coat at described nickeliferous layer on surface of metal; Carry out the first anneal to described containing nickel metal layer, remove described sealing coat and unreacted containing nickel metal layer, form silication two nickel dam at described substrate surface.
Optionally, the described nickel metal layer that contains comprises nickel and alloyed metal.
Optionally, described alloyed metal is wherein one or more the combination of tungsten, tantalum, zirconium, titanium, hafnium, platinum, palladium, vanadium, niobium, cobalt.
Optionally, described alloyed metal accounts for the scope containing the atomic percent of nickel metal layer is 0% ~ 10%.
Optionally, described alloyed metal is platinum, and the scope that described platinum accounts for containing the atomic percent of nickel metal layer is 5% ~ 10%.
Optionally, described sealing coat is titanium nitride layer.
Technical solution of the present invention additionally provides a kind of method for forming semiconductor devices, comprising:
Semiconducter substrate is provided, forms grid structure at described semiconductor substrate surface, in the semiconducter substrate of described grid structure both sides, form source/drain region;
Formed containing nickel metal layer on described grid structure, surface, source/drain region, form sealing coat at described nickeliferous layer on surface of metal;
To described containing after nickel metal layer carries out the first anneal, remove described sealing coat and unreacted containing nickel metal layer, form silication two nickel dam;
Formed containing hydrionic silicon nitride layer on described silication two nickel dam surface;
Second anneal is carried out to described silication two nickel dam, forms nickel silicide layer.
Optionally, when described semiconducter device is nmos pass transistor, also comprise, after carrying out the second anneal, carry out ultraviolet radiation to described containing hydrionic silicon nitride layer, form the silicon nitride layer with tensile stress.
Optionally, the processing parameter of described ultraviolet radiation comprises: temperature is 350 DEG C ~ 500 DEG C, and the time of radiation is 1min ~ 10min.
Optionally, the adjoint gas of described ultraviolet radiation is nitrogen, and the flow rate of described nitrogen is 5000sccm ~ 20000sccm, and air pressure is 1torr ~ 10torr.
Optionally, when described semiconducter device is PMOS transistor, also comprise, removing is described containing hydrionic silicon nitride layer, forms the silicon nitride layer with stress under compression on described nickel silicide layer surface.
Optionally, form the described technique containing hydrionic silicon nitride layer and comprise: utilize chemical vapor deposition method to form silicon nitride layer on described silication two nickel dam surface, Hydrogen implantation is carried out to described silicon nitride layer and is formed containing hydrionic silicon nitride layer.
Optionally, forming the described technique containing hydrionic silicon nitride layer is plasma enhanced chemical vapor deposition.
Optionally, described is 1E15atom/cm containing hydrionic content range in hydrionic silicon nitride layer
2~ 1E25atom/cm
2.
Optionally, the described thickness range containing hydrionic silicon nitride layer is
Optionally, the described nickel metal layer that contains comprises nickel and alloyed metal.
Optionally, described alloyed metal is wherein one or more the combination of tungsten, tantalum, zirconium, titanium, hafnium, platinum, palladium, vanadium, niobium, cobalt.
Optionally, described alloyed metal accounts for the scope containing the atomic percent of nickel metal layer is 0% ~ 10%.
Optionally, described sealing coat is titanium nitride layer.
Compared with prior art, the embodiment of the present invention has the following advantages:
Before second anneal formation nickel silicide layer is carried out to described silication two nickel dam, formed containing hydrionic silicon nitride layer on described silication two nickel dam surface, when carrying out the second anneal, hydrogen ion in described silicon nitride layer can be diffused in silication two nickel dam, the described interface roughness that can reduce nickel silicide layer and silicon substrate containing hydrionic nickel silicide layer, reduce the contact resistance of nickel silicide layer and silicon substrate, and the described quantity that also can reduce crystal boundary containing hydrionic nickel silicide layer, reduce the defect of crystal boundary, reduce the sheet resistance of nickel silicide layer, thus reduce the resistance of nickel silicide layer, the RC reducing circuit postpones.
Further, in embodiments of the present invention, utilize plasma enhanced chemical vapor deposition technique to be formed containing hydrionic silicon nitride layer, in silicon nitride layer, hydrionic content is very high, effectively can reduce the resistance of nickel silicide layer.
Further, the nickel metal layer that contains for the formation of nickel silicide layer has included alloyed metal, the annealing temperature contained needed for nickel metal layer annealing formation nickel silicide layer containing a small amount of alloyed metal is lower, annealing time is shorter, compared with the nickel metal layer not containing alloyed metal, described annealed containing nickel metal layer containing alloyed metal, is not easy to form the larger nickel disilicide of resistance, is also conducive to the sheet resistance reducing nickel silicide layer.
Further, described containing hydrionic silicon nitride layer through ultraviolet radiation, the silicon nitride layer with tensile stress can be formed, the travelling speed of the current carrier in nmos pass transistor channel region can be improved, improve the electric property of nmos pass transistor.The described silicon nitride layer with tensile stress can also as etching barrier layer during formation through hole.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the nickel silicide layer formation method of the embodiment of the present invention;
Fig. 2 to Fig. 6 is the cross-sectional view of the nickel silicide layer formation method of the embodiment of the present invention;
Fig. 7, Fig. 8 are doped with hydrionic nickel silicide layer with not doped with the test result comparison diagram of the sheet resistance of hydrionic nickel silicide layer;
Fig. 9 is the schematic flow sheet of the method for forming semiconductor devices of the embodiment of the present invention;
Figure 10 to Figure 16 is the cross-sectional view of the method for forming semiconductor devices of the embodiment of the present invention.
Embodiment
Because prior art effectively can not solve the resistance reducing nickel silicide layer, make the RC of circuit postpone to become large, contriver, through research, proposes a kind of nickel silicide layer formation method that effectively can reduce the resistance of nickel silicide layer, comprise: substrate is provided, form silication two nickel dam at described substrate surface; Formed containing hydrionic silicon nitride layer on described silication two nickel dam surface; Second anneal is carried out to described silication two nickel dam, forms nickel silicide layer.Because the hydrogen ion in described silicon nitride layer can be diffused in nickel silicide layer in the process of the second anneal, and the sheet resistance that the sheet resistance ratio containing hydrionic nickel silicide layer does not contain hydrionic nickel silicide layer is little, and the contact resistance of described nickel silicide layer and substrate also diminishes, the resistance of the nickel silicide layer making the resistance ratio of the final nickel silicide layer formed utilize prior art to be formed is little, and the RC reducing circuit postpones.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
The embodiment of the present invention provide firstly a kind of nickel silicide layer formation method, please refer to Fig. 1, is the schematic flow sheet of the nickel silicide layer formation method of the embodiment of the present invention, specifically comprises:
Step S101, provides substrate, forms silication two nickel dam at described substrate surface;
Step S102, is formed containing hydrionic silicon nitride layer on described silication two nickel dam surface;
Step S103, carries out the second anneal to described silication two nickel dam, forms nickel silicide layer.
Fig. 2 to Fig. 6 is the cross-sectional view of the nickel silicide layer formation method of the embodiment of the present invention.
Please refer to Fig. 2, substrate 100 is provided, formed containing nickel metal layer 110 on described substrate 100 surface, form sealing coat 120 described containing nickel metal layer 110 surface.
Described substrate 100 is monocrystalline substrate, multicrystalline silicon substrate, silicon-on-insulator substrate one wherein.Wherein, when nickel silicide layer is formed at surface, source/drain region, described substrate 100 is monocrystalline substrate, silicon-on-insulator substrate one wherein, and when nickel silicide layer is formed at grid structure surface, described substrate 100 is multicrystalline silicon substrate.
The described nickel metal layer 110 that contains at least comprises nickel, alloyed metal can also be comprised, wherein said alloyed metal is wherein one or more the combination of tungsten, tantalum, zirconium, titanium, hafnium, platinum, palladium, vanadium, niobium, cobalt, and the scope that described alloyed metal accounts for the whole atomic percent containing nickel metal layer was 0% ~ 10% (comprising 0%, 10%).Described alloyed metal can prevent nickel from spreading in the process of anneal too fast thus form nickel silicide, nickel disilicide spine, described nickel silicide, nickel disilicide spine easily produce the leakage current between source/drain region.And contain the lower containing the annealing temperature needed for nickel metal layer of described alloyed metal, annealing time is shorter, compared with the nickel metal layer not containing alloyed metal, described containing alloyed metal containing nickel metal layer annealed, be not easy to form the larger nickel disilicide of sheet resistance, be also conducive to the resistance reducing nickel silicide layer.
In the present embodiment, described alloyed metal is platinum, the scope that platinum accounts for the whole atomic percent containing nickel metal layer was 5% ~ 10% (comprising 5%, 10%), a certain amount of platinum can react with silicon, nickel formation nickel-platinum suicide in the process of anneal, it is too fast that described nickel-platinum suicide can prevent nickel from spreading in the semiconductor substrate, be not easy to produce leakage current, the annealing temperature simultaneously formed needed for nickel-platinum suicide is lower, be not easy to form the larger nickel disilicide of sheet resistance, be also conducive to the resistance reducing nickel silicide layer.But the resistance due to described nickel-platinum suicide is greater than the resistance of nickel silicide, if the too high resistance that can improve nickel silicide layer on the contrary of the content of platinum, therefore described platinum accounts for the scope of the whole atomic percent containing nickel metal layer is 5% ~ 10%.
Forming the described technique containing nickel metal layer 110 is physical vapor deposition (PVD).In the present embodiment, described physical vapor deposition (PVD) can adopt nickel platinum alloy target sputter method, utilizes plasma body to bombard described nickel platinum alloy, and the atom be sputtered out is formed containing nickel metal layer 110 at described substrate 100 surface aggregation.The scope that described platinum accounts for the atomic percent of whole nickel platinum alloy target is 5% ~ 10%, and the scope that described nickel accounts for the atomic percent of whole nickel platinum alloy target is 90% ~ 95%.In other embodiments, described physical vapor deposition (PVD) can also adopt More target sputtering together method, i.e. nickel target and platinum target co-sputtering.The described mass ratio containing nickel in nickel metal layer 110 and platinum obtains by regulating the sputtering power of nickel target and platinum target.
Described containing nickel metal layer 110 surface formed sealing coat 120 be titanium nitride membrane, described titanium nitride membrane is described containing nickel metal layer 110 and ambient atmos for isolating, can prevent containing nickel metal layer 110 surface oxidized, thus reduce the sheet resistance of the final nickel silicide layer formed, the final resistance reducing nickel silicide layer.The technique forming described titanium nitride membrane is chemical vapour deposition or physical vapor deposition.Because the method forming described titanium nitride membrane is the known technology of those skilled in the art, be not described further at this.
Please refer to Fig. 3, carry out the first anneal to described containing nickel metal layer, form silication two nickel dam 111 at described substrate 100 and unreacted containing between nickel metal layer 112.Described first anneal is rapid thermal annealing, and the temperature of described annealing is 200 DEG C ~ 350 DEG C, and the time of annealing is 10s ~ 60s.
Please also refer to Fig. 3 and Fig. 4, after carrying out the first anneal, remove described sealing coat 120 and unreacted containing nickel metal layer 112, expose described silication two nickel dam 111.
Remove described sealing coat 120 and the unreacted technique containing nickel metal layer 112 is wet etching, the solution for wet etching is acid solution.In the present embodiment, removing titanium nitride membrane and the unreacted solution containing nickel metal layer are the mixture of sulfuric acid and hydrogen peroxide.Because silication two nickel dam 111 can not react with acid, titanium nitride membrane and the unreacted nickel metal layer 112 that contains are removed, and silication two nickel dam 111 is retained.
Please refer to Fig. 5, formed containing hydrionic silicon nitride layer 130 on described silication two nickel dam 111 surface.
Described is 1E15atom/cm containing hydrionic content range in hydrionic silicon nitride layer 130
2~ 1E25atom/cm
2.The thickness range of described silicon nitride layer 130 is
in the present embodiment, forming the described technique containing hydrionic silicon nitride layer 130 is plasma enhanced chemical vapor deposition (PECVD).Utilizing PECVD to form silicon nitride adopts silane and nitrogen or silane and nitrogen to react usually, and reaction equation is as follows:
SiH
4(gaseous state)+NH
3(gaseous state) → Si
xn
yh
z(solid-state)+H
2(gaseous state)
SiH
4(gaseous state)+N
2(gaseous state) → Si
xn
yh
z(solid-state)+H
2(gaseous state)
The composition of the silicon nitride layer 130 that PECVD is formed is non-stoichiometrics, so write as Si
xn
yh
z.Wherein, NH
3with SiH
4the hydrogen content of the silicon nitride layer 130 that reaction is formed is greater than N
2and SiH
4the hydrogen content of the silicon nitride layer 130 that reaction is formed.The silicon nitride layer 130 formed owing to utilizing PECVD is containing a large amount of hydrogen ions, make follow-up when carrying out annealing process described hydrogen ion can be diffused in silication two nickel dam 111 that described silicon nitride layer 130 covers, the final nickel silicide layer 130 formed is made also to be rich in hydrogen ion, thus effectively can reduce the resistance of nickel silicide layer 130, the RC reducing circuit postpones.
In the present embodiment, the substrate temperature range utilizing PECVD to form silicon nitride layer 130 is 300 DEG C ~ 500 DEG C, and air pressure range is 1torr ~ 10torr, and the power range of electrode is 50W ~ 400W.The reactant gases utilizing PECVD to form described silicon nitride layer comprises ammonia and silane or comprises nitrogen and silane or comprise ammonia, nitrogen and silane.In the present embodiment, the reactant gases forming described silicon nitride layer comprises ammonia, nitrogen and silane, the flow rate of described silane is 50sccm ~ 200sccm, and the flow rate of described ammonia is 200sccm ~ 1000sccm, and the flow rate of described nitrogen is 500sccm ~ 2000sccm.
In other embodiments, forming the described method containing hydrionic silicon nitride layer is: form silicon nitride layer on described silication two nickel dam surface, carry out Hydrogen implantation formed containing hydrionic silicon nitride layer described silicon nitride layer.Wherein, the technique forming described silicon nitride layer is chemical vapour deposition.
Please also refer to Fig. 5 and Fig. 6, the second anneal is carried out to described silication two nickel dam 111, form nickel silicide layer 113.
Described second anneal is rapid thermal annealing, and the temperature of described annealing is 300 DEG C ~ 450 DEG C, and the time of annealing is 10s ~ 60s.The nickel silicide layer 113 formed owing to utilizing twice annealing process is not easy to form nickel disilicide spine, described nickel disilicide spine resistance more greatly and easily cause the generation of leakage current between source/drain region, therefore, the resistance of the nickel silicide layer utilizing second annealing process to be formed is less, and the RC reducing circuit postpones.
Due in the process of described second anneal, the hydrogen ion in described silicon nitride layer 130 can be diffused in described silication two nickel dam 111.When described silication two nickel dam 111 forms nickel silicide layer through anneal, the described interface roughness that can reduce nickel silicide layer and silicon substrate containing hydrionic nickel silicide layer, reduce the contact resistance of nickel silicide layer and silicon substrate, and the described quantity that also can reduce crystal boundary containing hydrionic nickel silicide layer, reduce the defect of crystal boundary, reduce the sheet resistance of nickel silicide layer, thus reduce the resistance of nickel silicide layer.And due to hydrionic concentration in described silicon nitride layer 130 very large, and described nickel silicide layer 113 surface coverage has described silicon nitride layer 130, the hydrogen ion be doped in described nickel silicide layer 113 can only spread downwards, make the hydrionic concentration in described nickel silicide layer 113 very large, effectively can reduce the resistance of nickel silicide layer 113.
Please refer to Fig. 7, for N-type substrate surface formed doped with hydrionic nickel silicide layer with not doped with the test result comparison diagram of the sheet resistance of hydrionic nickel silicide layer.Ordinate zou is the sheet resistance of nickel silicide layer, and X-coordinate is annealing temperature.Trilateral represents not doped with hydrionic nickel silicide layer, and square represents doped with hydrionic nickel silicide layer.As shown in data in Fig. 7, when annealing region is at 400 DEG C ~ 500 DEG C, N-type substrate surface formed the sheet resistance doped with hydrionic nickel silicide layer be significantly less than N-type substrate surface formed not doped with the sheet resistance of hydrionic nickel silicide layer.
Please refer to Fig. 8, for P type substrate surface formed doped with hydrionic nickel silicide layer with not doped with the test result comparison diagram of the sheet resistance of hydrionic nickel silicide layer.Ordinate zou is the sheet resistance of nickel silicide layer, and X-coordinate is annealing temperature.Trilateral represents not doped with hydrionic nickel silicide layer, and square represents doped with hydrionic nickel silicide layer.As shown in data in Fig. 8, when annealing region is at 400 DEG C ~ 500 DEG C, P type substrate surface formed the sheet resistance doped with hydrionic nickel silicide layer be significantly less than P type substrate surface formed not doped with the sheet resistance of hydrionic nickel silicide layer.
In the embodiment of the present invention, before carrying out the second anneal formation nickel silicide layer, utilize pecvd process to be formed containing hydrionic silicon nitride layer on described silication two nickel dam surface, when carrying out the second anneal, hydrogen ion in described silicon nitride layer can be diffused in silication two nickel dam, make containing hydrogen ion in the final nickel silicide layer formed, can effectively reduce the resistance of nickel silicide layer, the RC reducing circuit postpones.
Further, the nickel metal layer that contains for the formation of nickel silicide layer has included alloyed metal, the annealing temperature contained needed for nickel metal layer annealing formation nickel silicide layer containing a small amount of alloyed metal is lower, annealing time is shorter, compared with the nickel metal layer not containing alloyed metal, described annealed containing nickel metal layer containing alloyed metal, is not easy to form the larger nickel disilicide of resistance, is also conducive to the sheet resistance reducing nickel silicide layer.
The embodiment of the present invention additionally provides a kind of method for forming semiconductor devices, please refer to Fig. 9, is the schematic flow sheet of embodiment of the present invention method for forming semiconductor devices, specifically comprises:
Step S201, provides semiconducter substrate, forms grid structure, in the semiconducter substrate of described grid structure both sides, form source/drain region at described semiconductor substrate surface;
Step S202, is formed containing nickel metal layer on described grid structure, surface, source/drain region, forms sealing coat at described nickeliferous layer on surface of metal;
Step S203, to described containing after nickel metal layer carries out the first anneal, remove described sealing coat and unreacted containing nickel metal layer, forms silication two nickel dam;
Step S204, is formed containing hydrionic silicon nitride layer on described silication two nickel dam surface;
Step S205, carries out the second anneal to described silication two nickel dam, forms nickel silicide layer.
Figure 10 to Figure 16 is the cross-sectional view of the method for forming semiconductor devices of one embodiment of the invention.
Please refer to Figure 10, semiconducter substrate 200 is provided, form grid structure 210 on described semiconducter substrate 200 surface, in the semiconducter substrate 200 of described grid structure 210 both sides, form source/drain region 220.
Described semiconducter substrate 200 is silicon substrate, silicon-on-insulator substrate one wherein.The device that described semiconducter substrate 200 is formed is nmos pass transistor, PMOS transistor or CMOS transistor, according to the difference of the device formed, doped with N-type ion or P type ion in described semiconducter substrate 200.Fleet plough groove isolation structure (not shown) is also formed to form the active area of electric isolution in described semiconducter substrate 200.In the present embodiment, explain to form nmos pass transistor.Because semiconducter device to be formed is nmos pass transistor, in described semiconducter substrate 200, the ion of doping is P type ion.
Described grid structure 210 comprises the gate oxide 211 being positioned at described semiconducter substrate 200 surface, the gate electrode 212 being positioned at described gate oxide 211 surface and is positioned at the side wall 213 of described gate oxide 211, gate electrode 212 sidewall surfaces.The material of described gate oxide 211 is silicon oxide, and the material of described gate electrode 212 is the polysilicon of polysilicon or doping, and the material of described side wall 213 is silicon oxide, silicon nitride or the rhythmo structure of the two.Because the formation method of described grid structure is the known technology of those skilled in the art, do not repeat them here.
The concrete technology forming described source/drain region 220 comprises: form the gate oxide 211 be positioned in described semiconducter substrate 200 successively, after gate electrode 212, with photoetching offset plate figure (not shown) for mask, to described gate oxide 211, the semiconducter substrate of gate electrode 212 both sides carries out the first ion implantation formation light dope source/drain region (not shown), at described gate oxide 211, after gate electrode 212 sidewall forms side wall 213, with described side wall 213 for mask, second ion implantation formation heavy doping source/drain region (not shown) is carried out to the semiconducter substrate of described side wall 213 both sides, described light dope source/drain region and formation source/drain region, heavy doping source/drain region 220.The type of described dopant ion is N-type ion or P type ion.In the present embodiment, the type of described source/drain region 220 dopant ion is N-type ion.
Please refer to Figure 11, formed containing nickel metal layer 230 on described grid structure 210, surface, source/drain region 220, form sealing coat 240 described containing nickel metal layer 230 surface.
The described nickel metal layer 230 that contains at least comprises nickel, alloyed metal can also be comprised, wherein said alloyed metal is wherein one or more the combination of tungsten, tantalum, zirconium, titanium, hafnium, platinum, palladium, vanadium, niobium, cobalt, and the scope that described alloyed metal accounts for the whole atomic percent containing nickel metal layer was 0% ~ 10% (comprising 0%, 10%).Described alloyed metal can prevent nickel from spreading in the process of anneal too fast thus form nickel silicide, nickel disilicide spine, described nickel silicide, nickel disilicide spine easily produce the leakage current between source/drain region.And contain the lower containing the annealing temperature needed for nickel metal layer 230 of described alloyed metal, annealing time is shorter, compared with the nickel metal layer not containing alloyed metal, described containing alloyed metal containing nickel metal layer annealed, be not easy to form the larger nickel disilicide of sheet resistance, be also conducive to the resistance of the nickel silicide layer reducing follow-up formation.
Forming the described technique containing nickel metal layer 230 is physical vapor deposition (PVD).The alloys target sputtering method that described physical vapor deposition (PVD) can adopt alloyed metal and nickel jointly to form, utilize plasma body to bombard described alloys target, the atom be sputtered out is formed containing nickel metal layer 230 at described grid structure 210, source/drain region 220 surface aggregation.Described physical vapor deposition (PVD) can also adopt More target sputtering together method, i.e. nickel target and alloyed metal target co-sputtering.The described atomic ratio containing nickel in nickel metal layer 230 and alloyed metal obtains by regulating the sputtering power of nickel target and alloyed metal target.
After described physical gas-phase deposition, the described nickel metal layer 230 that contains covers described grid structure 210, source/drain region 220 and surface of shallow trench isolation structure, in the present embodiment, directly carry out the first anneal to described containing nickel metal layer 230, form silication two nickel dam.Only can react with silicon materials containing the metal in nickel metal layer 230 due to described, silication two nickel dam of therefore follow-up formation only can be formed in the surface of the gate electrode of surface, source/drain region 220 and grid structure 210, realizes autoregistration.Also can first etch containing nickel metal layer 230 described in other embodiments, what remove the region not needing to form nickel silicide layer contains nickel metal layer, such as surface of shallow trench isolation structure containing nickel metal layer, then the first anneal is carried out, at surface formation silication two nickel dam of the gate electrode of surface, source/drain region 220 and grid structure 210.
Described containing nickel metal layer 230 surface formed sealing coat 240 be titanium nitride membrane, described titanium nitride membrane is described containing nickel metal layer 230 and ambient atmos for isolating, prevent containing nickel metal layer 230 surface oxidized, thus reduce the sheet resistance of the final nickel silicide layer formed.The technique forming described titanium nitride membrane is chemical vapour deposition or physical vapor deposition.Because the method forming described titanium nitride membrane is the known technology of those skilled in the art, be not described further at this.
Please refer to Figure 12, carry out the first anneal to described containing nickel metal layer, described substrate 200 and no reaction form silication two nickel dam 231 containing between nickel metal layer 232.Described silication two nickel dam 231 is positioned at surface, source/drain region 220 and grid structure 210 surface.Described first anneal is rapid thermal annealing, and the temperature of described annealing is 200 DEG C ~ 350 DEG C, and the time of annealing is 10s ~ 60s.
Please also refer to Figure 12 and 13, after carrying out the first anneal, remove described sealing coat 240 and unreacted containing nickel metal layer 232, expose described silication two nickel dam 231.
Remove described sealing coat 240 and the unreacted technique containing nickel metal layer 232 is wet etching, the solution for wet etching is acid solution.In the present embodiment, removing titanium nitride membrane and the unreacted solution containing nickel metal layer are the mixture of sulfuric acid and hydrogen peroxide.Because silication two nickel dam 231 can not react with acid, described sealing coat 240 and the unreacted nickel metal layer 232 that contains are removed, and silication two nickel dam 231 is retained.
Please refer to Figure 14, formed containing hydrionic silicon nitride layer 250 on described silication two nickel dam 231 surface.
Described is 1E15atom/cm containing hydrionic content range in hydrionic silicon nitride layer 250
2~ 1E25atom/cm
2.The thickness range of described silicon nitride layer 250 is
In the present embodiment, forming the described technique containing hydrionic silicon nitride layer 250 is plasma enhanced chemical vapor deposition (PECVD).Utilizing PECVD to form silicon nitride adopts silane and nitrogen or silane and nitrogen to react usually, and the final silicon nitride layer generated contains a large amount of hydrogen ions.The silicon nitride layer formed owing to utilizing PECVD contains a large amount of hydrogen ions, make follow-up when carrying out annealing process described hydrogen ion can be diffused in silication two nickel dam 231 that described silicon nitride layer 250 covers, the final nickel silicide layer formed is made also to be rich in hydrogen ion, thus effectively can reduce the resistance of nickel silicide layer, the RC reducing circuit postpones.
In other embodiments, forming the described method containing hydrionic silicon nitride layer is: form silicon nitride layer on described silication two nickel dam surface, carry out Hydrogen implantation formed containing hydrionic silicon nitride layer described silicon nitride layer.Wherein, the technique forming described silicon nitride layer is chemical vapour deposition.
Please also refer to Figure 14 and Figure 15, the second anneal is carried out to described silication two nickel dam 231, form nickel silicide layer 233.
Described second anneal is rapid thermal annealing, and the temperature of described annealing is 300 DEG C ~ 450 DEG C, and the time of annealing is 10s ~ 60s.Because the nickel silicide layer utilizing twice annealing process to be formed is not easy to form nickel disilicide spine, described nickel disilicide spine resistance more greatly and easily cause the generation of leakage current between source/drain region, therefore, the resistance of the nickel silicide layer utilizing second annealing process to be formed is less, and the RC reducing circuit postpones.
Due in the process of described second anneal, the hydrogen ion in described silicon nitride layer 250 can be diffused in described silication two nickel dam 231.When described silication two nickel dam 231 forms nickel silicide layer 233 through anneal, the described interface roughness that can reduce nickel silicide layer 233 and semiconducter substrate 200 containing hydrionic nickel silicide layer 233, reduce the contact resistance of nickel silicide layer and silicon substrate, and the described number of grain boundaries that also can reduce nickel silicide layer inside containing hydrionic nickel silicide layer 233, reduce the defect of crystal boundary, reduce the sheet resistance of nickel silicide layer, thus the final resistance reducing nickel silicide layer.And due to concentration hydrionic in described silicon nitride layer very large, and described nickel silicide layer 233 surface coverage has described silicon nitride layer 250, the hydrogen ion be doped in described nickel silicide layer 233 can only spread downwards, make the hydrionic concentration in described nickel silicide layer 233 very large, effectively can reduce the resistance of nickel silicide layer 233.
Please refer to Figure 16, UV radiation 300 is carried out to described silicon nitride layer 250, form the silicon nitride layer 255 with tensile stress.
The semiconducter device formed due to the embodiment of the present invention is nmos pass transistor, current carrier in the channel region of described nmos pass transistor is electronics, when the crystalline network of described channel region is subject to stretching, the travelling speed of described electronics will accelerate, and can improve the electric property of nmos pass transistor.Therefore, carry out UV (UltraViolet, ultraviolet) radiation 300 to described silicon nitride layer 250, the hydrogen ion in described silicon nitride layer 250 is overflowed, the silicon nitride layer 255 after effusion hydrogen ion can produce high tensile stress.Because UV radiating capacity interrupts si-h bond and hydrogen bound to nitrogen, described in interrupt after hydrogen ion can form hydrogen and overflow from silicon nitride layer.After removing hydrogen ion, silicon key remaining in described silicon nitride layer and nitrogen key can form silazine link again, because described Siliciumatom and Nitrogen ion have been fixed on certain region by lattice and cannot have alleviated strain, the silazine link of described new formation can be stretched, and final formation has the silicon nitride layer 255 of tensile stress.
Wherein, the temperature of described UV radiation 300 is 350 DEG C ~ 500 DEG C, and the time of radiation is 1min ~ 10min, and be nitrogen with gas, the flow rate of described nitrogen is 5000sccm ~ 20000sccm, and air pressure is 1torr ~ 10torr.
The described silicon nitride layer 255 with tensile stress can also as etching barrier layer during formation through hole.Due to after described semiconductor device surface forms medium layer, in described source/drain region, grid structure surface forms the through hole running through described medium layer by etching technics, and described through hole is used for filler metal and forms conductive plunger.But because the through hole on grid structure surface is different from the degree of depth of the through hole on surface, source/drain region, be easy to the nickel silicide layer over etching on grid structure surface to fall.When described grid structure and surface, source/drain region are formed with silicon nitride layer, because the etching selection ratio of described silicon nitride layer and medium layer is very large, etch media layer all can stop at described silicon nitride layer surface when forming through hole, recycle same etching technics to etch the uniform silicon nitride layer of described thickness, the via etch on final grid mechanism and surface, source/drain region all stops at described nickel silicide layer surface, can not impact the electrical connection of nickel silicide layer.
In other embodiments, when the final semiconducter device formed is PMOS transistor, because the current carrier in the channel region of described PMOS transistor is hole, when the crystalline network of described channel region is compressed, the travelling speed in described hole will accelerate, and can improve the electric property of PMOS transistor.Therefore, after forming described nickel silicide layer, removing is described containing hydrionic silicon nitride layer, and forms the silicon nitride layer with stress under compression on described PMOS transistor surface.Described have all right as etching barrier layer during formation through hole of the silicon nitride layer of stress under compression.The silicon nitride layer due to formation with stress under compression is the known technology of those skilled in the art, is not described in detail in this.
In the embodiment of the present invention, before carrying out the second anneal formation nickel silicide layer, utilize pecvd process to be formed containing hydrionic silicon nitride layer on described silication two nickel dam surface, when carrying out the second anneal, hydrogen ion in described silicon nitride layer can be diffused in silication two nickel dam, make containing hydrogen ion in the final nickel silicide layer formed, can effectively reduce the resistance of nickel silicide layer, the RC reducing circuit postpones.
Further, described containing hydrionic silicon nitride layer through UV radiation, the silicon nitride layer with tensile stress can be formed, the travelling speed of the current carrier in nmos pass transistor channel region can be improved, improve the electric property of nmos pass transistor.The described silicon nitride layer with tensile stress can also as etching barrier layer during formation through hole.
Further, after formation nickel silicide layer, removing is described containing hydrionic silicon nitride layer, and described nickel silicide layer is formed the silicon nitride layer with stress under compression, the travelling speed of the current carrier in PMOS transistor channel region can be improved, improve the electric property of PMOS transistor.The described silicon nitride layer with stress under compression can also as etching barrier layer during formation through hole.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (26)
1. a nickel silicide layer formation method, is characterized in that, comprising:
Substrate is provided, forms silication two nickel dam at described substrate surface; The method forming described silication two nickel dam comprises: formed containing nickel metal layer at described substrate surface, forms sealing coat at described nickeliferous layer on surface of metal; Carry out the first anneal to described containing nickel metal layer, remove described sealing coat and unreacted containing nickel metal layer, form silication two nickel dam at described substrate surface;
Formed containing hydrionic silicon nitride layer on described silication two nickel dam surface;
Second anneal is carried out to described silication two nickel dam being coated with described silicon nitride layer, forms nickel silicide layer.
2. nickel silicide layer formation method as claimed in claim 1, is characterized in that, described is 1E15atom/cm containing hydrionic content range in hydrionic silicon nitride layer
2~ 1E25atom/cm
2.
3. nickel silicide layer formation method as claimed in claim 1, it is characterized in that, form the described technique containing hydrionic silicon nitride layer to comprise: utilize chemical vapor deposition method to form silicon nitride layer on described silication two nickel dam surface, carry out Hydrogen implantation to described silicon nitride layer and formed containing hydrionic silicon nitride layer.
4. nickel silicide layer formation method as claimed in claim 1, is characterized in that, forming the described technique containing hydrionic silicon nitride layer is plasma enhanced chemical vapor deposition.
5. nickel silicide layer formation method as claimed in claim 4, it is characterized in that, the concrete technology parameter utilizing plasma enhanced chemical vapor deposition to form described silicon nitride layer comprises: substrate temperature range is 300 DEG C ~ 500 DEG C, air pressure range is 1torr ~ 10torr, and the power range of electrode is 50W ~ 400W.
6. nickel silicide layer formation method as claimed in claim 4, it is characterized in that, the reactant gases utilizing plasma enhanced chemical vapor deposition to form described silicon nitride layer comprises ammonia and silane or comprises nitrogen and silane or comprise ammonia, nitrogen and silane.
7. nickel silicide layer formation method as claimed in claim 6, it is characterized in that, when the reactant gases forming described silicon nitride layer comprises ammonia, nitrogen and silane, the flow rate of described silane is 50sccm ~ 200sccm, the flow rate of described ammonia is 200sccm ~ 1000sccm, and the flow rate of described nitrogen is 500sccm ~ 2000sccm.
8. nickel silicide layer formation method as claimed in claim 1, is characterized in that, the described thickness range containing hydrionic silicon nitride layer is
9. nickel silicide layer formation method as claimed in claim 1, is characterized in that, the described nickel metal layer that contains comprises nickel and alloyed metal.
10. nickel silicide layer formation method as claimed in claim 9, is characterized in that, described alloyed metal is wherein one or more the combination of tungsten, tantalum, zirconium, titanium, hafnium, platinum, palladium, vanadium, niobium, cobalt.
11. nickel silicide layer formation methods as claimed in claim 9, is characterized in that, the scope that described alloyed metal accounts for containing the atomic percent of nickel metal layer is 0% ~ 10%.
12. nickel silicide layer formation methods as claimed in claim 9, it is characterized in that, described alloyed metal is platinum, and the scope that described platinum accounts for containing the atomic percent of nickel metal layer is 5% ~ 10%.
13. nickel silicide layer formation methods as claimed in claim 1, it is characterized in that, described sealing coat is titanium nitride layer.
14. 1 kinds of method for forming semiconductor devices, is characterized in that, comprising:
Semiconducter substrate is provided, forms grid structure at described semiconductor substrate surface, in the semiconducter substrate of described grid structure both sides, form source/drain region;
Formed containing nickel metal layer on described grid structure, surface, source/drain region, form sealing coat at described nickeliferous layer on surface of metal;
To described containing after nickel metal layer carries out the first anneal, remove described sealing coat and unreacted containing nickel metal layer, form silication two nickel dam;
Formed containing hydrionic silicon nitride layer on described silication two nickel dam surface;
Second anneal is carried out to described silication two nickel dam being coated with described silicon nitride layer, forms nickel silicide layer.
15. method for forming semiconductor devices as claimed in claim 14, is characterized in that, when described semiconducter device is nmos pass transistor, also comprise, after carrying out the second anneal, carry out ultraviolet radiation to described containing hydrionic silicon nitride layer, form the silicon nitride layer with tensile stress.
16. method for forming semiconductor devices as claimed in claim 15, it is characterized in that, the processing parameter of described ultraviolet radiation comprises: temperature is 350 DEG C ~ 500 DEG C, and the time of radiation is 1min ~ 10min.
17. method for forming semiconductor devices as claimed in claim 15, it is characterized in that, the adjoint gas of described ultraviolet radiation is nitrogen, the flow rate of described nitrogen is 5000sccm ~ 20000sccm, and air pressure is 1torr ~ 10torr.
18. method for forming semiconductor devices as claimed in claim 14, it is characterized in that, when described semiconducter device is PMOS transistor, also comprise, removing is described containing hydrionic silicon nitride layer, forms the silicon nitride layer with stress under compression on described nickel silicide layer surface.
19. method for forming semiconductor devices as claimed in claim 14, it is characterized in that, form the described technique containing hydrionic silicon nitride layer to comprise: utilize chemical vapor deposition method to form silicon nitride layer on described silication two nickel dam surface, carry out Hydrogen implantation to described silicon nitride layer and formed containing hydrionic silicon nitride layer.
20. method for forming semiconductor devices as claimed in claim 14, is characterized in that, forming the described technique containing hydrionic silicon nitride layer is plasma enhanced chemical vapor deposition.
21. method for forming semiconductor devices as claimed in claim 14, is characterized in that, described is 1E15atom/cm containing hydrionic content range in hydrionic silicon nitride layer
2~ 1E25atom/cm
2.
22. method for forming semiconductor devices as claimed in claim 14, is characterized in that, the described thickness range containing hydrionic silicon nitride layer is
23. method for forming semiconductor devices as claimed in claim 14, is characterized in that, the described nickel metal layer that contains comprises nickel and alloyed metal.
24. method for forming semiconductor devices as claimed in claim 23, is characterized in that, described alloyed metal is wherein one or more the combination of tungsten, tantalum, zirconium, titanium, hafnium, platinum, palladium, vanadium, niobium, cobalt.
25. method for forming semiconductor devices as claimed in claim 23, is characterized in that, the scope that described alloyed metal accounts for containing the atomic percent of nickel metal layer is 0% ~ 10%.
26. method for forming semiconductor devices as claimed in claim 14, it is characterized in that, described sealing coat is titanium nitride layer.
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| CN103489787B (en) * | 2013-09-22 | 2016-04-13 | 上海华力微电子有限公司 | Improve the method for source and drain contact and silicon nitride film adhesive force |
| CN103489825B (en) * | 2013-09-22 | 2016-01-20 | 上海华力微电子有限公司 | Solve the process of silicon nitride and nickel silicide interface spallation problems |
| CN104178739B (en) * | 2014-08-11 | 2017-03-15 | 昆山海普电子材料有限公司 | A kind of nickel platinum alloy target with copper alloy backing plate and preparation method thereof |
| CN106033721B (en) * | 2015-03-11 | 2019-10-25 | 中芯国际集成电路制造(上海)有限公司 | The method for forming metal silicide |
| CN112462145A (en) * | 2020-11-24 | 2021-03-09 | 上海华力集成电路制造有限公司 | Detection method of nickel silicide heat treatment process |
| CN114230154B (en) * | 2021-12-22 | 2022-11-22 | 东海县太阳光新能源有限公司 | Quartz crucible with long service life and low deformation rate and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1512546A (en) * | 2002-12-26 | 2004-07-14 | ̨������·����ɷ�����˾ | Method for forming grid contact window |
| CN1514473A (en) * | 2002-12-31 | 2004-07-21 | �Ҵ���˾ | Caking action of retarding nickel silicide using Ni alloy |
| CN101393869A (en) * | 2007-09-17 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method for silicon nitride film and contact etching stop layer |
-
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1512546A (en) * | 2002-12-26 | 2004-07-14 | ̨������·����ɷ�����˾ | Method for forming grid contact window |
| CN1514473A (en) * | 2002-12-31 | 2004-07-21 | �Ҵ���˾ | Caking action of retarding nickel silicide using Ni alloy |
| CN101393869A (en) * | 2007-09-17 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method for silicon nitride film and contact etching stop layer |
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