CN1649080A - Method for producing semiconductor element connection surface zone - Google Patents
Method for producing semiconductor element connection surface zone Download PDFInfo
- Publication number
- CN1649080A CN1649080A CN 200410003317 CN200410003317A CN1649080A CN 1649080 A CN1649080 A CN 1649080A CN 200410003317 CN200410003317 CN 200410003317 CN 200410003317 A CN200410003317 A CN 200410003317A CN 1649080 A CN1649080 A CN 1649080A
- Authority
- CN
- China
- Prior art keywords
- connection surface
- surface zone
- semiconductor element
- element connection
- making semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 14
- 229910052799 carbon Inorganic materials 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 25
- 230000004888 barrier function Effects 0.000 claims description 18
- 230000005611 electricity Effects 0.000 claims description 17
- 239000002002 slurry Substances 0.000 claims description 17
- 150000001721 carbon Chemical class 0.000 claims description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- -1 carbon ion Chemical class 0.000 claims description 4
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 3
- 239000001569 carbon dioxide Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000006396 nitration reaction Methods 0.000 claims description 3
- 238000003672 processing method Methods 0.000 claims 9
- 150000003376 silicon Chemical class 0.000 claims 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 2
- 238000005255 carburizing Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 11
- 125000004429 atom Chemical group 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910018999 CoSi2 Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000019771 cognition Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Abstract
This invention relates to a method for manufacturing semiconductor element interface zone including providing a semiconductor basic material to form a grating structure on the semiconductor basic material, implanting foreign atoms on the semiconductor basic material to form an interface zone and an insulation layer on the grating structure and the basic material, carburizing the insulation to form a gap wall on the side wall of the grating structure and implanting foreign atoms in the basic material to form a source/drain adjacent to the interface zone and to carry out heat process to the material.
Description
Technical field
The present invention is relevant for a kind of manufacture method of formation semiconductor element connection surface zone, particularly about a kind of method of making PMOS semiconductor element connection surface zone.
Background technology
When semiconductor element such as CMOS (Complementary Metal Oxide Semiconductor), because amass into the raising of degree, the shared area of element is more little relatively.So advanced semiconductor technology, the size of integrated circuit component has narrowed down to deep-sub-micrometer, owing to the generation that causes some problems of dwindling of size.
Along with semi-conductive progress, it is meticulous more to make semiconductor element, and the requirement of foreign atom depth distribution is also meticulous more.Usually, the method that ion is implanted often is used to accurately control the distribution of the foreign atom degree of depth and concentration, at the processing procedure that ion is implanted, foreign atom with a kind of form of charged ion via quickening to obtain the appropriate location in the lattice of direct impacts silicon wafers behind the energy.So the depth distribution of ion can be controlled by ion energy, the concentration of foreign atom can be controlled by the time of ion implantation and the size of current of ion beam simultaneously.
In the prior art, the ion beam of charged ion such as suitable energy utilizes ion implanter may to plant (ionimplanter) and goes in the Silicon Wafer.Then, therefore the defective that causes when needing a tempering manufacturing process to deactivate impurity element and reparation bump causes the ion of implantation to adjust its distributing position again again, also can produce the phenomenon (transient enhance diffusion) of moment diffusion increase simultaneously.The result is difficult to form supershallow connection surface with the conventional ion implantation.Moreover, when the linewidth requirements of element during less than 90nm, each regional area in the element, comprise source electrode, drain electrode and metal-oxide semiconductor (MOS) and all will dwindle thereupon, the diffusion depth that so connects face must accurately be controlled to reduce short-channel effect (short channel effect) and perforation effect (punch-througheffect).
After the component size development enters below the 90nm, have the low-resistance source of supershallow connection surface/drain electrode extension area (source/drain extensions) and be the needs on the most realistic, can suppress short-channel effect (shortchannel effect) and have high current drives (high current drivability).Recent studies have shown that the carbon ion implantation can reach the effect of making supershallow connection surface with the mode of low-yield implantation, carbon atom combines the diffusion that therefore suppresses foreign atom with the gap of semiconductor substrate, yet the carbon atom that ion is implanted but can cause and meet the face place at p-n and higher leakage current generating is arranged and cause lower production capacity, and said circumstances is for using the ill effect that must consider when carbon atom is implanted.
Summary of the invention
In above-mentioned background of invention, the conventional ion implantation can't be made the supershallow connection surface of actual needs.Purpose of the present invention is to provide a kind of manufacture method of making the semiconductor element connection surface zone.It is the scope of carbon containing electricity slurry may command connection surface zone dopant profile, so through follow-up temper, dopant atoms can be suppressed and can't spread.
Another object of the present invention is providing a kind of connection surface zone that utilizes carbon containing electricity slurry to make semiconductor element.Because carbon containing electricity slurry only carries out Carburization Treatment on the wafer substrate surface, can significantly reduce the defective of wafer substrate, help follow-up crystallization heat again to handle, and cause connect face at p-n higher leakage current is arranged when avoiding producing similar ion and implanting carbon atom.
According to above-described purpose, disclose a kind of method of making the semiconductor element connection surface zone, its method comprises provides the semiconductor ground, form a grid structure on semiconductor substrate, implant a foreign atom and form a connection surface zone in semiconductor substrate, form an insulating barrier on grid structure and semiconductor substrate, utilize carbon containing electricity slurry that insulating barrier is carried out Carburization Treatment, form a clearance wall on the grid structure sidewall, foreign atom implanted semiconductor ground is formed the source/drain electrode adjacent with connection surface zone, and semiconductor substrate is carried out a heat treatment.
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
Description of drawings
Figure 1A to Fig. 1 F is a succession of generalized section that the inventive method is made the semiconductor element connection surface zone.
Embodiment
The present invention is described in detail as follows with schematic diagram, and when the detailed description embodiment of the invention, the profile of expression semiconductor structure can be disobeyed general ratio and be done local the amplification in order to explanation in manufacture of semiconductor, so should be with this as the cognition that qualification is arranged.In addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
In this embodiment, disclose a kind of method of making the semiconductor element connection surface zone, its method comprises provides the semiconductor ground, form a grid structure on semiconductor substrate, implant a foreign atom and form a connection surface zone in semiconductor substrate, form an insulating barrier on grid structure and semiconductor substrate, utilize carbon containing electricity slurry that insulating barrier is carried out Carburization Treatment, form a clearance wall on the grid structure sidewall, foreign atom implanted semiconductor ground is formed the source/drain electrode adjacent with connection surface zone, and semiconductor substrate is carried out a heat treatment.
One embodiment of the invention are with reference to Figure 1A to Fig. 1 F.At first according to Figure 1A, provide semiconductor ground 10, silicon base material for example is to form the MOS element of p type or n type.In the present embodiment, some elements or structure (not in graphic demonstration) can be included in the semiconductor substrate 10, for example some impure wells or isolated component.The person of connecing, an oxide layer and a conductive layer are formed on the semiconductor substrate 10 in regular turn.This oxide layer and conductive layer form a grid structure that comprises lock oxide layer 20 and gate electrode 21 after by the lithography patterning.Very the person sometimes for special design, can form a compensate for clearance wall (offset spacer) (not in graphic demonstration) on the sidewall of grid structure.
The person of connecing is implanted in the above-mentioned structure with p type admixture, to form some PMOS elements.In the present embodiment, with the admixture 11 of periodic table three races (III) element, for example boron is implanted to formation source in the semiconductor substrate 10/drain electrode and extends connection surface zone.The another kind of selection is that first implanting germanium re-uses in the low-energy boron ion implanted semiconductor ground 10 of the about 1 ~ 10keV of energy after forming amorphous materialization surface on the semiconductor substrate 10.Be noted that the present invention is applied to form the zone of PMOS element, but be not limited to only form the PMOS element, also can form the NMOS element in another zone on semiconductor substrate 10.
On the other hand, with reference to Figure 1B, behind above-mentioned admixture 11 formation source/drain electrode in semiconductor substrate 10 extension connection surface zone 15 (its thickness range is haply less than 400 dusts), utilize the method for conformal deposited, on grid structure and semiconductor substrate 10 surfaces, form insulating barrier 25, for example an oxide layer.The person of connecing, one of feature of the present invention, utilize 13 pairs of insulating barriers 25 of carbon containing electricity slurry to carry out Carburization Treatment, utilize a heat treatment afterwards again, for example the Rapid Thermal temper of boiler tube temper and elimination source/drain electrode lattice defect just can make the carbon atom 14 in the insulating barrier 25 be diffused into source/drain electrode extension connection surface zone 15.Heat treated temperature range is about 500 ~ 1200 ℃.In the present embodiment, this heat treatment is the Rapid Thermal temper (about 900 ~ 1200 ℃ of temperature range) of directly utilizing the elimination source that is used in the successive process/drain electrode 18 lattice defects, make in the insulating barrier 25 carbon atom be diffused into source/drain electrode and extend connection surface zone 15, so be not limited thereto.Because carbon atom 14 can and suppress the diffusion of boron in conjunction with the gap (interstitials) of connection surface zone, can make source/drain electrode extension connection surface zone 15 stable existences.In addition, in the present embodiment, the source of carbon containing electricity slurry 13 is one to contain the gas of carbon dioxide, so is not limited thereto.Wherein, the power bracket that carbon containing electricity slurry uses is approximately 0.1 watt/square centimeter to 0.5 watt/square centimeter, and its carbon ion diffuses to the concentration range of connection surface zone approximately greater than 1e19/cm3.
Afterwards, on insulating barrier 25, form a dielectric layer, for example nitration case with the method for conformal deposited again.Then, utilize etching mode to remove partial insulative layer 25 and dielectric layer 27, only stay at the insulating barrier 25 of grid structure sidewall and dielectric layer 27 with clearance wall 29 by way of compensation, shown in Fig. 1 C.Then, utilize again a p type ion implant 17 in the semiconductor substrate 10 with formation source/drain region 18, shown in Fig. 1 D.Then, by about 900 ~ 1200 ℃ of serviceability temperature, the temper step in the time of staying in (dwell time) about 0 ~ 30 second, for example Rapid Thermal temper (RTA) is eliminated lattice defect and activated impurity element to reach.In the present embodiment, another feature of the present invention, this tempering step the more important thing is that the carbon atom 14 that makes in the insulating barrier 25 is diffused into source/drain electrode and extends connection surface zone 15, to suppress the diffusion of boron atom, shown in Fig. 1 D except above-mentioned effect is arranged.
With reference to Fig. 1 E, the metallic cobalt 30 that deposits about 100 dusts of a layer thickness is in gate electrode 21 and source/drain electrode 18.Form the cobalt silicide of the aligning voluntarily CoSi of partial reaction through follow-up temper, and remove unreacted cobalt metal 30 for the first time.With reference to Fig. 1 F, carry out the cobalt silicide of the aligning voluntarily CoSi2 31 that secondary hot temper reacts completely with formation at last again.
In the method for the present invention, control concentration and the degree of depth of carbon atom by adjusting the time, the power that use when carbon containing electricity slurry is handled insulating barrier 25 at insulating barrier 25, and make carbon atom diffuse to semiconductor substrate 10 via a heat treatment, the boron atom that suppresses supershallow connection surface laterally with diffusion depth longitudinally, and guarantee that the supershallow connection surface that forms can not cause the diffusion of boron because of follow-up heat treatment or thermal cycle processing procedure.
Though the present invention describes with reference to current specific embodiment, but those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, under the situation that does not break away from spirit of the present invention, also can make the variation and the modification of various equivalences, therefore, as long as variation, the modification to the foregoing description all will drop in the scope of claims of the present invention in connotation scope of the present invention.
Claims (20)
1. method of making the semiconductor element connection surface zone comprises:
The semiconductor ground is provided;
Form a grid structure on this semiconductor substrate;
Implant a foreign atom in this semiconductor substrate to form a connection surface zone;
Form an insulating barrier on this grid structure and this semiconductor substrate;
Utilize carbon containing electricity slurry that this insulating barrier is carried out Carburization Treatment; And
This semiconductor substrate is carried out a heat treatment.
2. the method for making semiconductor element connection surface zone as claimed in claim 1 is characterized in that, also comprises:
Form a clearance wall on a sidewall of this grid structure; And
Implant in this semiconductor substrate this foreign atom adjacent with this connection surface zone to form a source/drain electrode.
3. the method for making semiconductor element connection surface zone as claimed in claim 2 is characterized in that, the step that wherein forms this clearance wall comprises:
Conformal formation one nitration case is on this insulating barrier; And
The some of removing this nitration case and this insulating barrier is to form this clearance wall.
4. the method for making semiconductor element connection surface zone as claimed in claim 1 is characterized in that, wherein a thickness range of this connection surface zone is haply less than 400 dusts.
5. the method for making semiconductor element connection surface zone as claimed in claim 1 is characterized in that, wherein this carbon containing electricity slurry refers to use a source of containing carbon dioxide.
6. the method for making semiconductor element connection surface zone as claimed in claim 1 is characterized in that, wherein the power bracket of this carbon containing electricity slurry use is approximately 0.1 watt/square centimeter to 0.5 watt/square centimeter.
7. the method for making semiconductor element connection surface zone as claimed in claim 1 is characterized in that, the step that wherein forms this insulating barrier comprises conformal formation monoxide.
8. the method for making semiconductor element connection surface zone as claimed in claim 1 is characterized in that, wherein this foreign atom comprises and is selected from one of following group: three (III) families and five (V) family element.
9. the method for making semiconductor element connection surface zone as claimed in claim 1 is characterized in that, wherein the carbon ion of this carbon containing electricity slurry is diffused into a concentration range of this connection surface zone approximately greater than 1e19/cm3.
10. the method for making semiconductor element connection surface zone as claimed in claim 1 is characterized in that, wherein this heat treated temperature range is for being approximately 500～1200 ℃.
11. the method for making semiconductor element connection surface zone as claimed in claim 1 is characterized in that, wherein this heat treatment comprises one of the following method that is selected from: a boiler tube temper and a Rapid Thermal temper.
12. a processing method of making the semiconductor element connection surface zone comprises:
One silicon base material is provided;
Form a grid structure on this silicon base material;
Form first clearance wall on a sidewall of this grid structure;
Implant a boracic admixture in a part of zone of this silicon base material to form one first doped region;
Form an oxide layer on this first clearance wall, this grid structure and this silicon base material;
Utilize carbon containing electricity slurry that this oxide layer is carried out Carburization Treatment;
Form second clearance wall on this first clearance wall;
It is adjacent with this first doped region to form second doped region that one p type admixture is implanted this silicon base material;
Utilize this silicon base material of Rapid Thermal temper; And
Form a metal silicide on this grid structure and this silicon base material.
13. the processing method of making semiconductor element connection surface zone as claimed in claim 12 is characterized in that, wherein the thickness range of this first doped region is haply less than 400 dusts.
14. the processing method of making semiconductor element connection surface zone as claimed in claim 12 is characterized in that, wherein this carbon containing electricity slurry refers to use a source of containing carbon dioxide.
15. the processing method of making semiconductor element connection surface zone as claimed in claim 12 is characterized in that, wherein the power bracket of this carbon containing electricity slurry use is approximately 0.1 watt/square centimeter to 0.5 watt/square centimeter.
16. the processing method of making semiconductor element connection surface zone as claimed in claim 12 is characterized in that, wherein the carbon ion of this carbon containing electricity slurry is diffused into a concentration range of this first doped region approximately greater than 1e19/cm3.
17. the processing method of making semiconductor element connection surface zone as claimed in claim 12 is characterized in that, wherein this oxide layer is a silicon dioxide layer.
18. the processing method of making semiconductor element connection surface zone as claimed in claim 12 is characterized in that, wherein this second clearance wall is a silicon nitride layer.
19. the processing method of making semiconductor element connection surface zone as claimed in claim 12 is characterized in that, wherein a temperature range of this Rapid Thermal temper is approximately 900～1200 ℃.
20. the processing method of making semiconductor element connection surface zone as claimed in claim 12 is characterized in that, wherein this metal silicide is one to aim at cobalt silicide voluntarily.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100033177A CN100336167C (en) | 2004-01-20 | 2004-01-20 | Method for producing semiconductor element connection surface zone |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100033177A CN100336167C (en) | 2004-01-20 | 2004-01-20 | Method for producing semiconductor element connection surface zone |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1649080A true CN1649080A (en) | 2005-08-03 |
| CN100336167C CN100336167C (en) | 2007-09-05 |
Family
ID=34867561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100033177A Expired - Lifetime CN100336167C (en) | 2004-01-20 | 2004-01-20 | Method for producing semiconductor element connection surface zone |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100336167C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035523A (en) * | 2011-09-30 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| CN108122776A (en) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | FINFEF devices and forming method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821563A (en) * | 1990-12-25 | 1998-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device free from reverse leakage and throw leakage |
| TW429517B (en) * | 1999-12-16 | 2001-04-11 | United Microelectronics Corp | Gate oxide layer manufacturing method |
| TW434711B (en) * | 2000-02-14 | 2001-05-16 | Taiwan Semiconductor Mfg | Method for making silicide |
-
2004
- 2004-01-20 CN CNB2004100033177A patent/CN100336167C/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035523A (en) * | 2011-09-30 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| CN103035523B (en) * | 2011-09-30 | 2016-03-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of Transistor forming method |
| CN108122776A (en) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | FINFEF devices and forming method thereof |
| US10770570B2 (en) | 2016-11-29 | 2020-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and methods of forming |
| CN108122776B (en) * | 2016-11-29 | 2022-02-11 | 台湾积体电路制造股份有限公司 | FINFET device and method of forming the same |
| US11450757B2 (en) | 2016-11-29 | 2022-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and methods of forming |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100336167C (en) | 2007-09-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4342429B2 (en) | Manufacturing method of semiconductor device | |
| EP1121713B1 (en) | Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits | |
| US8187959B2 (en) | Semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same | |
| JP2005521265A5 (en) | ||
| JP2006024946A (en) | Manufacturing method of polycrystalline silicon and manufacturing method of semiconductor element utilizing the same | |
| CN101350308A (en) | Gold oxygen semiconductor field effect electric crystal and method for reducing damage in source/drain electrode area | |
| JP2006059843A (en) | Semiconductor device and its manufacturing method | |
| US20070232033A1 (en) | Method for forming ultra-shallow high quality junctions by a combination of solid phase epitaxy and laser annealing | |
| KR100458086B1 (en) | Method of forming contact in semiconductor device and fabrication method of pMOSFET using the same | |
| TW201133567A (en) | Cold implant for optimized silicide formation | |
| JP2005322893A (en) | Dopant doping method and manufacturing method of semiconductor device | |
| CN100336167C (en) | Method for producing semiconductor element connection surface zone | |
| US7888223B2 (en) | Method for fabricating P-channel field-effect transistor (FET) | |
| CN100386885C (en) | Low temp polycrystal silicon film transistor and manufacturing method thereof | |
| US20100015788A1 (en) | Method for manufacturing semiconductor device | |
| US7060547B2 (en) | Method for forming a junction region of a semiconductor device | |
| KR20070000330A (en) | Method for manufacturing semiconductor device | |
| US20080145992A1 (en) | Method of Manufacturing a Semiconductor Device Having Reduced N/P or P/N Junction Crystal Disorder | |
| CN100447964C (en) | Production of thin-film transistor | |
| US6974745B2 (en) | Method of manufacturing semiconductor device | |
| CN100466234C (en) | Film transistor mfg. method | |
| KR100728958B1 (en) | Method of manufacturing semicondutor device | |
| US20060110868A1 (en) | Production of lightly doped drain of low-temperature poly-silicon thin film transistor | |
| TWI228278B (en) | Method for forming a junction region of a semiconductor device | |
| CN101593696B (en) | Method for manufacturing semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070905 |
|
| CX01 | Expiry of patent term |