CN103996619B - Method for solving side wall deposition problem of germanium-silicon selective epitaxy through nitrogen implanting - Google Patents

Method for solving side wall deposition problem of germanium-silicon selective epitaxy through nitrogen implanting Download PDF

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CN103996619B
CN103996619B CN201410253551.9A CN201410253551A CN103996619B CN 103996619 B CN103996619 B CN 103996619B CN 201410253551 A CN201410253551 A CN 201410253551A CN 103996619 B CN103996619 B CN 103996619B
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side wall
silicon
germanium
pmos device
device region
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CN103996619A (en
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邱裕明
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The invention provides a method for solving the side wall deposition problem of a germanium-silicon selective epitaxy through nitrogen implanting. The method comprises the steps that a silicon slice is formed in a substrate, wherein the silicon slice is provided with an NMOS device region and a PMOS device region, the NMOS device region and the PMOS device region are isolated by an isolation area, and gate structures with silicon nitride side walls are formed in the NMOS device region and the PMOS device region respectively; a photoetching mask is arranged on the NMOS device region of the substrate, and the PMOS device region is exposed; side wall surface pretreatment is conducted on the silicon nitride side walls of the PMOS device region exposed out of the photoetching mask through the nitrogen implanting process and the annealing process; etching is conducted on the PMOS device region after side wall surface pretreatment so that a source drain region groove can be formed; the source drain region groove formed through etching is filled through selective epitaxy growth so that a germanium-silicon source drain region can be formed. Low-energy nitrogen implanting and high-temperature annealing are used before etching, side wall surface pretreatment is conducted, as a result, silicon broken bonds can be consumed, the deposition speed of germanium-silicon layers of the side walls is reduced, and deposition selectivity is enhanced.

Description

The method depositing problem using the side wall that nitrogen injection improves germanium silicon selective epitaxial
Technical field
The present invention relates to field of semiconductor manufacture is and in particular to side wall during pmos source-drain area germanium silicon layer selective growth forms sediment Long-pending problem；It is more particularly related to the side wall that a kind of utilization nitrogen injection improves germanium silicon selective epitaxial deposits problem Method.
Background technology
Reduce with silicon-based devices characteristic size, the enhancing of integrated level and complexity, occur in that and a series of be related to material, device The new problem of the aspects such as part physics, device architecture and technology.In order to continue to the fast development of microelectronic, The new technology introducing strain in the raceway groove of mos device is arisen at the historic moment.Strain is introduced in active area by technique, referred to as technique causes to answer Become (process-induced strain).
The performance of cmos circuit is restricted by pmos to a great extent, and therefore, pmos transistor needs the application can be Performance brings up to the technology of nmos level.It is to pmos source and drain by germanium silicon mosaic that the implantation of germanium silicon (sige) source/drain causes strain gauge technique Area, thus producing compressive deformation at raceway groove, improves the carrier mobility of pmos transistor, and the raising of carrier mobility May result in high driving current, improve transistor performance, as shown in Figure 1.Specifically, it is that the source of device, drain region etching are gone Remove, then again deposit germanium silicon layer, because the lattice paprmeter of germanium silicon is more than the lattice paprmeter of silicon, source region and drain region will be to raceway grooves Produce a compression stress, thus improving the transmission characteristic of pmos.
When carrying out the deposit of germanium silicon layer, affect follow-up work because the integrated reason of technique is not intended on side wall germanium silicon layer Skill, so the technique adopting is selectively deposited, generally adopts silane (sih4) or dichloroethylene (dcs) as silicon source, germane And add hydrochloric acid (hcl) to improve epitaxially grown selectivity (geh4).So-called selectivity, refers to the extension in silicon substrate for the germanium silicon layer The speed of growth is very fast, and grows relatively slow on silicon nitride spacer, by depositing the processing step utilizing hcl corrosion, Remove the germanium silicon deposit on side wall.Generally, in order to ensure good surface selectively, high temperature hcl or other techniques can also be used Carry out surface preparation, to clear up side wall surface and source-drain area surface.
However, side wall surface tends to the scission of link of residual silicon, these scission of links make the germanium silicon layer initial growth speed on side wall Degree is accelerated, and after selectively deposited, can leave unnecessary germanium silicon layer 300 (as Fig. 2 institute on pmos device area 200 side wall Show), affect follow-up technique.
Content of the invention
The technical problem to be solved is that there is drawbacks described above in prior art, provides one kind can utilize Nitrogen injection improves the method that the side wall of germanium silicon selective epitaxial deposits problem, wherein the silicon nitride spacer of pmos device area is entered The injection of row nitrogen and the surface preparation of high annealing, reduce the selective speed of growth on side wall for the germanium and silicon epitaxial, suppress side wall On germanium silicon layer deposit.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided it is selectively outer that one kind improves germanium silicon using nitrogen injection The method that the side wall prolonging deposits problem, comprising:
First step, is formed with the nmos device area being separated by isolated area and pmos device in the substrate for providing The silicon chip in region, is wherein formed with the grid knot with silicon nitride spacer on nmos device area and pmos device area Structure；
Second step, for arranging photo etched mask on the nmos device area of substrate, exposes pmos device area；
Third step, the nitrogen of the pmos device area for being exposed to photo etched mask using nitrogen injection technology and annealing process SiClx side wall carries out side wall surface preparation；
Four steps, for performing etching to the pmos device area after side wall surface preparation to form source and drain Area's groove；
5th step, for forming the leakage of germanium silicon source by the source-drain area groove that selective epitaxial growth filling etching is formed Area.
Preferably, Implantation Energy during nitrogen injection technology is 1～2kev, and implantation dosage is 5e14～5e15, and injection tilts Angle is to become 22～30 degree with respect to the line vertical with silicon face.
Preferably, the condition of high-temperature annealing process is that the temperature using 1000～1050 DEG C is moved back in a nitrogen environment Fire is processed.
Preferably, isolated area is shallow trench isolation.
Preferably, the method for the described side wall deposit problem utilizing nitrogen injection to improve germanium silicon selective epitaxial is used for manufacturing Cmos circuit.
The present invention carries out nitrogen injection and the surface preparation of high annealing to the silicon nitride spacer of pmos, consumes side wall surface Unnecessary silicon scission of link, the germanium silicon layer thus reducing initial growth speed on side wall for the selective germanium and silicon epitaxial, on suppression side wall Deposit.
Brief description
In conjunction with accompanying drawing, and by reference to detailed description below, it will more easily have more complete understanding to the present invention And its adjoint advantages and features are more easily understood, wherein:
Fig. 1 schematically shows the pmos structure causing strain gauge technique according to the germanium silicon source/drain implantation of prior art, wherein Germanium silicon layer produces extruding to raceway groove, improves mobility.
Fig. 2 schematically shows the side wall deposit easily producing during the selective epitaxial filling according to prior art and lacks Fall into.
Fig. 3 to Fig. 7 schematically shows utilization nitrogen injection according to the preferred embodiment of the invention and improves germanium silicon selectively The side wall of extension deposits each step of the method for problem.
It should be noted that accompanying drawing is used for the present invention is described, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can Can be not necessarily drawn to scale.And, in accompanying drawing, same or like element indicates same or like label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention Appearance is described in detail.
The principle of the present invention is that the silicon nitride spacer to pmos carries out nitrogen injection and the surface preparation of high annealing, disappears The silicon scission of link of consumption side wall excess surface, thus reducing initial growth speed on side wall for the selective germanium and silicon epitaxial, suppresses side wall On germanium silicon layer deposit.
Will be detailed below the preferred embodiments of the present invention.
Fig. 3 to Fig. 7 schematically shows utilization nitrogen injection according to the preferred embodiment of the invention and improves germanium silicon selectively The side wall of extension deposits each step of the method for problem.
Specifically, as shown in Figures 3 to 6, utilization nitrogen injection according to the preferred embodiment of the invention improves germanium silicon and selects Property extension side wall deposit problem method include:
First step, is formed with, for providing, the nmos device being separated by isolated area 20 (such as shallow trench isolation) in the substrate Part region 100 and the silicon chip of pmos device area 200, wherein on nmos device area 100 and pmos device area 200 It is formed with the grid structure with silicon nitride spacer 10, as shown in Figure 3；
Second step, for arranging photo etched mask 400 on the nmos device area 100 of substrate, exposes pmos device region Domain 200, as shown in Figure 4；
Third step, for pmos device area photo etched mask 400 being exposed using nitrogen injection technology and annealing process 200 silicon nitride spacer 10 carries out side wall surface preparation, as shown in Figure 5；Preferably, Implantation Energy during nitrogen injection technology is 1～2kev, implantation dosage is 5e14～5e15, and injection angle of inclination is to become 22～30 degree with respect to the line vertical with silicon face； And preferably, the condition of high-temperature annealing process is in a nitrogen environment, is made annealing treatment with 1000～1050 DEG C of temperature. This step carries out nitrogen injection and the surface preparation of high annealing, consumes the silicon scission of link of side wall excess surface, reduces follow-up Initial growth speed on side wall for the selective germanium and silicon epitaxial, thus suppress the germanium silicon layer on side wall to deposit.
Four steps, for performing etching to the pmos device area 200 after side wall surface preparation to be formed Source-drain area groove, as shown in Figure 6；
5th step, for forming the leakage of germanium silicon source by the source-drain area groove that selective epitaxial growth filling etching is formed Area 500, as shown in Figure 7.Wherein as shown in fig. 7, in pmos device area 200 unattached germanium silicon layer side wall.
The present invention passes through in the selectively deposited front Nitrogen ion injecting low-yield, median dose or high dose, then through too high Temperature annealing, can consume the silicon scission of link on side wall surface, reduce the germanium silicon layer initial growth speed on side wall, thus ensureing germanium and silicon epitaxial The selectivity of growth.
For example, the method is advantageously used for manufacturing cmos circuit.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in specification " first ", " the Two ", " 3rd " etc. describes each assembly being used only in differentiation specification, element, step etc., rather than is used for representing each Logical relation between assembly, element, step or ordinal relation etc..
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment being not used to Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, The technology contents that the disclosure above all can be utilized are made many possible variations and modification, or are revised as to technical solution of the present invention Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection Interior.

Claims (5)

1. the side wall that a kind of utilization nitrogen injection improves germanium silicon selective epitaxial deposits the method for problem it is characterised in that including:
First step, is formed with the nmos device area being separated by isolated area and pmos device area in the substrate for providing Silicon chip, wherein on nmos device area and pmos device area, be formed with the grid structure with silicon nitride spacer；
Second step, for arranging photo etched mask on the nmos device area of substrate, exposes pmos device area；
Third step, the silicon nitride of the pmos device area for being exposed to photo etched mask using nitrogen injection technology and annealing process Side wall carries out side wall surface preparation；
Four steps is recessed to form source-drain area for performing etching to the pmos device area after side wall surface preparation Groove；
5th step, for forming germanium silicon source drain region by the source-drain area groove that selective epitaxial growth filling etching is formed.
2. utilization nitrogen injection according to claim 1 improves the method that the side wall of germanium silicon selective epitaxial deposits problem, its It is characterised by, Implantation Energy during nitrogen injection technology is 1～2kev, implantation dosage is 5e14～5e15, injection angle of inclination is Become 22～30 degree with respect to the line vertical with silicon face.
3. utilization nitrogen injection according to claim 1 and 2 improves the method that the side wall of germanium silicon selective epitaxial deposits problem, It is characterized in that, the condition of high-temperature annealing process is in a nitrogen environment, is carried out at annealing using 1000～1050 DEG C of temperature Reason.
4. utilization nitrogen injection according to claim 1 and 2 improves the method that the side wall of germanium silicon selective epitaxial deposits problem, It is characterized in that, isolated area is shallow trench isolation.
5. utilization nitrogen injection according to claim 1 and 2 improves the method that the side wall of germanium silicon selective epitaxial deposits problem, It is characterized in that, the method that the described side wall utilizing nitrogen injection to improve germanium silicon selective epitaxial deposits problem is used for manufacturing cmos electricity Road.
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CN105590852A (en) * 2014-10-21 2016-05-18 上海华力微电子有限公司 Method for decreasing dislocation defects of embedded silicon-germanium epitaxial growth
CN111816733B (en) * 2020-07-28 2021-11-09 中国电子科技集团公司第四十四研究所 Pretreatment method for selective germanium epitaxy in waveguide germanium detector manufacturing process

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6090653A (en) * 1998-03-30 2000-07-18 Texas Instruments Method of manufacturing CMOS transistors
CN101241929A (en) * 2007-02-08 2008-08-13 国际商业机器公司 Semiconductor structure and method of forming the structure
CN101572269A (en) * 2008-04-30 2009-11-04 台湾积体电路制造股份有限公司 Source/drain carbon implant and rta anneal, pre-sige deposition
CN102891084A (en) * 2011-07-19 2013-01-23 中芯国际集成电路制造(上海)有限公司 Method for manufacturing P-channel metal oxide semiconductor (PMOS) transistor
CN103035523A (en) * 2011-09-30 2013-04-10 中芯国际集成电路制造(上海)有限公司 Transistor forming method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6090653A (en) * 1998-03-30 2000-07-18 Texas Instruments Method of manufacturing CMOS transistors
CN101241929A (en) * 2007-02-08 2008-08-13 国际商业机器公司 Semiconductor structure and method of forming the structure
CN101572269A (en) * 2008-04-30 2009-11-04 台湾积体电路制造股份有限公司 Source/drain carbon implant and rta anneal, pre-sige deposition
CN102891084A (en) * 2011-07-19 2013-01-23 中芯国际集成电路制造(上海)有限公司 Method for manufacturing P-channel metal oxide semiconductor (PMOS) transistor
CN103035523A (en) * 2011-09-30 2013-04-10 中芯国际集成电路制造(上海)有限公司 Transistor forming method

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