CN103023480B - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
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- CN103023480B CN103023480B CN201210364883.5A CN201210364883A CN103023480B CN 103023480 B CN103023480 B CN 103023480B CN 201210364883 A CN201210364883 A CN 201210364883A CN 103023480 B CN103023480 B CN 103023480B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
It is an object of the invention to provide a kind of semiconductor integrated circuit that clamp voltage can be set as right value.This semiconductor integrated circuit has：Constant current portion（60）, it is supplied to power supply and produces constant current, and wherein said power supply is first voltage；Clamp portion（71）, it is supplied to by constant current portion（60）The constant current producing the low second voltage of producing ratio first voltage, the power supply of first voltage is clamped in second voltage；And reference voltage generating unit（72）, it is supplied to by clamp portion（71）Power supply after clamp simultaneously produces reference voltage, clamp portion（71）It is that grid is connected and multistage MOS transistor that longitudinal type is formed by connecting with drain electrode（M11‑1~M11‑n）.
Description
Technical field
The present invention relates to having the semiconductor integrated circuit of reference voltage circuit.
Background technology
There are high withstand voltage circuit and low voltage holding circuit the semiconductor integrated circuit deposited in semiconductor integrated circuit.So
Semiconductor integrated circuit in be provided with for prevent to low voltage holding circuit apply high voltage clamp circuit (clamp
circuit).
Fig. 6 is of the circuit structure diagram of semiconductor integrated circuit proposing in patent documentation 1 before the applicant
Example.In Fig. 6, semiconductor integrated circuit has power supply terminal 11, resistance 12, clamp circuit 13, low pressure internal circuit 14.
Power supply terminal 11 is the terminal being applied in high voltage VDD1 (being for example 30V to the maximum), its via resistance 12 and clamp circuit 13 and
Internal circuit 14 connects.
Clamp circuit 13 is made up of a npn bipolar transistor 21.The emitter stage warp of npn bipolar transistor 21
It is connected with power supply terminal 11 by resistance 12, and be connected with internal circuit 14.The colelctor electrode of transistor 21 and base stage are connected to one
Rise and be grounded.
Voltage clamp with the junction point of resistance 12 will not damaged internal circuit 14 by the clamp circuit 13 of said structure
Voltage.Clamp voltage i.e. back voltage (the opposite direction voltage between the emitter stage, base stage) example of npn bipolar transistor 21
6V in this way, clamp circuit 13 is fed into the back voltage in transistor 21 for the voltage clamp of internal circuit 14.
Internal circuit 14 has reference voltage generating circuit 16, the low voltage drive being driven by low-voltage (such as below 6V)
With circuit 17.Reference voltage generating circuit 16 is connected with low voltage drive circuit 17.Reference voltage generating circuit 16 has consumption
Type n-channel MOS 23 (depression type n channel MOS transistor) and enhancement mode n-channel to the greatest extent
MOS transistor 24 (enhancement type n channel MOS transistor).The drain electrode of MOS transistor 23 and crystalline substance
The emitter stage of body pipe 21 connects.The source ground of MOS transistor 24.
The grid of MOS transistor 23 is linked together with the grid of MOS transistor 24, and the source electrode of MOS transistor 23
Drain electrode with MOS transistor 24 links together.The MOS transistor 23 of depletion type works as current source, by MOS transistor 23
Source current as between the emitter stage of the drain current MOS transistor 24 that flows through and thus generate of MOS transistor 24, base stage
Threshold voltage (such as 2.0V) be supplied to low voltage drive circuit 17 as reference voltage V REF.
Patent documentation 1：Japanese Unexamined Patent Publication 2009-164415 publication
It is made the existing semiconductor integrated circuit shown in Fig. 6 in the operation forming MOS transistor.Npn bipolarity
Npn knot (npn junction) being formed in the operation be made MOS transistor is come by transistor 21 as bipolar transistor
Use.In the bipolar transistor 21 being formed in the operation forming MOS transistor, the ripple of the back voltage of bipolar transistor 21
Move big it is impossible to clamp voltage is set to right value (6V), the yield rate that result creates semiconductor integrated circuit is deteriorated so
Problem.
Content of the invention
The present invention is the invention proposing in view of the above problems, its object is to provide one kind can set clamp voltage
Semiconductor integrated circuit for right value.
The semiconductor integrated circuit that an embodiment of the invention is related to, has：
Constant current portion (60), it is supplied to power supply and produces constant current, and wherein said power supply is first voltage；
Clamp portion (71), it is supplied to first described in the constant current being produced by described constant current portion (60) producing ratio
The low second voltage of voltage, the power supply of described first voltage is clamped in described second voltage；And
Reference voltage generating unit (72), it is supplied to the power supply after being clamped by described clamp portion (71) and produces benchmark electricity
Pressure,
Described clamp portion (71) be grid is connected with drain electrode and multistage MOS transistor that longitudinal type is formed by connecting (M11-1～
M11-n)；
The n level MOS transistor that described longitudinal type is formed by connecting is operated in zone of saturation,
Using described constant current IREF, the degree of excursion μ of electronicsn, the grid capacity C of per unit areaox, MOS transistor
Grid width W, the grid length L of MOS transistor, the critical voltage V of MOS transistorth, to be expressed as described with following formula
The Vc of two voltages,
VC=n × [2 × IREF/(μnCox)]1/2×(L/W)1/2+n×Vth.
Preferably, described constant current portion (60) has：
Current stabilization portion (63), it by current stabilization and exports described constant current；
First boot portion (61), in certain period that the power supply that it is described first voltage in access rises, to described electric current
Stabilisation portion (63) supplies the power supply for described first voltage；And
Electric current supply unit (62), it is to described current stabilization portion (63) for giving in described reference voltage generating unit (72)
In the corresponding electric current of electric current that flows through.
Preferably, described constant current portion (60) has：
Current stabilization portion (63), it by current stabilization and exports described constant current；
Second boot portion (64), predetermined ginseng that the reference voltage that it produces in described reference voltage generating unit (72) is not enough
When examining voltage, supply the power supply for described first voltage to described current stabilization portion (63)；And
Electric current supply unit (62), it is to described current stabilization portion (63) for giving in described reference voltage generating unit (72)
In the corresponding electric current of electric current that flows through.
Preferably, described reference voltage generating unit (72) has：
First MOS transistor (M13) of depletion type, its drain electrode is supplied to the power supply after being clamped by described clamp portion (71),
Grid and source electrode are connected with the lead-out terminal (73) of described reference voltage；And
Second MOS transistor (M14) of enhancement mode, its grid and drain electrode are connected with the lead-out terminal (73) of described reference voltage
Connect.
Additionally, the reference markss in above-mentioned bracket mark for ease of understanding, it is only an example, and is confined to
The mode of diagram.
By means of the invention it is possible to clamp voltage is set to right value.
Brief description
Fig. 1 is the structure chart of an embodiment monitoring warning system.
Fig. 2 is the structure chart of an embodiment of handset.
Fig. 3 is the circuit structure diagram of an embodiment of the semiconductor integrated circuit of the present invention.
Fig. 4 is the circuit structure diagram of the variation of an embodiment of the semiconductor integrated circuit of the present invention.
Fig. 5 is the schematic diagram of the relation of the output voltage representing supply voltage and adjuster circuit.
Fig. 6 is an example of the circuit structure diagram of semiconductor integrated circuit.
Symbol description
30 machine tools
31 power signal lines
32-1～32-n handset
41 high withstand voltage chips
42 microcomputers
43 substrates
44 supervision sensors
46 reference voltage circuits
47 adjuster circuits
48 receiving circuits
49 transtation mission circuits
60 constant current source portions
61st, 64 boot portion
62 electric current supply units
63 current stabilization portions
65 comparators
66 DC sources
70 reference voltage generating units
71 clamp portions
72 reference voltage generating units
C1 capacitor
M1～M15 MOS transistor
R1, R2 resistance
Specific embodiment
Hereinafter, with reference to the accompanying drawings embodiments of the present invention are illustrated.
<The structure of warning system>
Fig. 1 is the structure chart representing an embodiment monitoring warning system.Monitor that warning system has：Machine tool 30, electricity
Source signal line 31, multiple handset 32-1～32-n.Machine tool 30 is to the multiple handsets 32-1～32-n being connected with power signal line 31
It is supplied respectively to power vd D1.Power vd D1 is usual voltage 24V (maximum voltage 30V).In addition, machine tool 30 is also by power supply signal
Line 31 sends control data with serial communication mode respectively to multiple handsets 32-1～32-n.
Each handset 32-1～32-n is supplied to power supply thus working from machine tool 30 respectively, using built-in supervision sensor
The data collection being configured environment is monitored.Then, the output data monitoring sensor is carried out by each handset with threshold value
Relatively judged, alarm (warning) is produced according to result of determination.Each handset 32-1～32-n is when producing alarm by electricity
Source signal line 31 sends data with alert with serial communication mode to machine tool 30.
<The structure of handset>
Fig. 2 represents the structure chart of an embodiment of handset.Handset has：High withstand voltage chip 41, microcomputer 42,
Monitor sensor 44.High withstand voltage chip 41 and microcomputer 42 are on substrate (basechip) 43.
Power signal line 31 is connected with terminal 45.Reference voltage circuit 46 in high withstand voltage chip 41, adjuster circuit 47,
Receiving circuit 48, transtation mission circuit 49 are connected with terminal 45 respectively.Reference voltage circuit 46 is via terminal 45 from power signal line 31
It is supplied to power vd D1 (usual voltage 24V, maximum voltage 30V), produce reference voltage V REF (such as 2.0V), and be supplied to
To adjuster circuit 47.
Adjuster circuit 47 is supplied to power vd D1 via terminal 45 from power signal line 31, generates with reference voltage V REF
On the basis of for example stable DC voltage in 5V being exported.The DC voltage of adjuster circuit 47 output is divided as power supply
It is not supplied to receiving circuit 48, transtation mission circuit 49, adjuster circuit 50.Adjuster circuit 50 supplies according to from adjuster circuit 47
5V DC voltage generate microcomputer such as 2.5V DC voltage, and be fed to microcomputer 42.
Receiving circuit 48 detects the change in voltage of the power signal line 31 via terminal 45 supply, and differentiation is to go here and there from machine tool 30
The control data of row transmission is still from the data with alert of other handset serial transmissions, and will determine the control number from machine tool
According to or be supplied to microcomputer 42 from the data with alert of other handsets.
Transtation mission circuit 49 when from microcomputer 42 supply data with alert when, by the low level moment in this data with alert
The voltage of terminal 45 is pulled down to such as 9V, this data with alert is transmitted serially to power signal line 31.
Microcomputer 42 is supplied to control data by receiving circuit 48 from machine tool 30, and is carried out according to this control data
Work.Microcomputer 42 is supervised using the data collection that supervision sensor 44 enters the setting environment such as trip temperature, humidity, cigarette
Depending on.The data collected is compared to be judged by microcomputer 42 with threshold value set in advance, according to result of determination
Produce alarm (warning).Then, the data with alert of the identification information containing itself, alert categories etc. is generated when producing alarm,
Machine tool 30 is transmitted serially to by transtation mission circuit 49.
<The structure of reference voltage circuit>
Fig. 3 represents that the semiconductor integrated circuit of the present invention is the circuit structure of an embodiment of reference voltage circuit 46
Figure.Reference voltage circuit 46 has：Constant current source portion 60, reference voltage generating unit 70.In constant current source portion 60, resistance
One end of R1 is connected with power vd D1 (usual voltage 24V, maximum 30V).The other end of resistance R1 is grounded via capacitor C1, and
And be connected with the grid of p-channel MOS transistor M1.
The source electrode of MOS transistor M1 is connected with power vd D1, and drain electrode is connected with junction point A via resistance R2.Junction point A with
The drain electrode of p-channel MOS transistor M4, the drain electrode of n-channel MOS M5, the grid of n-channel MOS M7 connect.Above-mentioned
Resistance R1, R2, capacitor C1, MOS transistor M1 constitute boot portion 61.In order to by current stabilization portion 63 stably by electric current
It is supplied to clamp portion 71 and be provided with boot portion 61.
Source electrode is connected by p-channel MOS transistor M2 with power vd D1, by the grid of grid and drain electrode and MOS transistor M4
Connect, and be connected with the drain electrode of n-channel MOS M3.The grid of MOS transistor M3 and the n of reference voltage generating unit 70
The grid of raceway groove M15 and drain electrode connect, the source ground of MOS transistor M3.
MOS transistor M4 is connected with the grid of MOS transistor M2 and drain electrode, and MOS transistor M2, M4 constitute current mirroring circuit
(current mirror circuit).The drain electrode of MOS transistor M4 is connected with the drain electrode of MOS transistor M5, MOS transistor M5
Grid be connected with the source electrode of MOS transistor 7, the source ground of MOS transistor M5.
The drain electrode of MOS transistor M7 is connected with the drain electrode of p-channel MOS transistor M6.The drain electrode of MOS transistor M6 and MOS
The grid of p-channel MOS transistor M10 of the grid of transistor M6 and reference voltage generating unit 70 connects, the source of MOS transistor M6
Pole is connected with power vd D1, and MOS transistor M6, M10 constitute current mirroring circuit.The source electrode of MOS transistor M7 be junction point B with
The grid of MOS transistor M5 connects, and via resistance R3 ground connection.
Above-mentioned MOS transistor M2, M3 constitutes electric current supply unit 62, and electric current is supplied to MOS transistor M4.MOS crystal
Pipe M4～M7 and resistance R3 constitutes current stabilization portion 63, carries out stabilisation to the drain current of MOS transistor M10.
In reference voltage generating unit 70, the source electrode of MOS transistor M10 is connected with power vd D1, MOS transistor M10's
Drain electrode is that junction point C is connected with the grid of n-channel MOS M12, and, the n-channel MOS that be formed by connecting multistage with longitudinal type
The grid of MOS transistor M11-1 in transistor M11-1～M11-n and drain electrode connect.MOS transistor M11-1～M11-n divides
Grid is not connected with drain electrode, the source electrode of the MOS transistor of higher level is connected with the grid of the MOS transistor of subordinate and drain electrode.
The source ground of the MOS transistor M11-n of subordinate.In addition, the MOS crystal by the source electrode of the MOS transistor of higher level and subordinate
The drain electrode of pipe connects and is referred to as longitudinal type connection.The series of MOS transistor M11-1～M11-n is to tens of stages from several levels.As
The MOS transistor M10 of above-mentioned current source and respectively by grid and drain electrode connect and the multistage MOS crystal being formed by connecting of longitudinal type
Pipe M11-1～M11-n constitutes clamp portion 71.
Here, if grid is connected, is all operated in zone of saturation with drain electrode by MOS transistor M11-1～M11-n,
Then the current source of MOS transistor M11-1～M11-n is the drain current I of MOS transistor M10REFWith following (1) Shi Laibiao
Show.Wherein, μnIt is the degree of excursion [cm of electronics2/V/s]、CoxIt is the grid capacity [F/m of per unit area2], W be MOS transistor
Grid width, L be the grid length of MOS transistor, VGSIt is gate source voltage across poles, the V of MOS transistorthIt is MOS crystal
The critical voltage (threshold voltage) of pipe.
IREF=(μnCox/2)×[W(VGS-Vth)2/L]……(1)
(1) solution is with regard to VGS, then
VGS=[2 × IREF/(μnCox)]1/2×(L/W)1/2+Vth……(2)
If the series of MOS transistor M11-1 is 1 grade, the voltage V of junction point CCI.e. clamp voltage VCIt is with (2) formula table
The V showingGS, but the series of the MOS transistor M11-1～M11-n after being connected due to longitudinal type is n, so the voltage V of junction point CC
I.e. clamp voltage VCTo be represented with following (3) formulas.
VC=n × [2 × IREF/(μnCox)]1/2×(L/W)1/2+n×Vth……(3)
The clamp portion 71 being made up of above-mentioned MOS transistor M11-1～M11-n is by junction point C i.e. MOS transistor
The grid clamping of M12 is in voltage VC(VCIt is, for example, the value of 6V～7V degree).MOS transistor M12 is by grid voltage VCEnter line level
Exported from source electrode after displacement.
So, flow through drain source voltage across poles during constant current with drain electrode in MOS transistor grid being coupled together
Being accurately determined is as represented by (2) formula, above-mentioned will be many with longitudinal type with the MOS transistor that couples together of drain electrode for grid
The clamp voltage V in the clamp portion 71 that level connects and constitutesCTo be represented with (3) formula, larger fluctuation will not be produced, but correctly
Value.
The drain electrode of MOS transistor M12 is connected with power vd D1, and the source electrode of MOS transistor M12 is brilliant with depletion type n-channel MOS
The drain electrode of body pipe M13 connects.The grid of MOS transistor M13 and source electrode are connected with the grid of n-channel MOS M14 and drain electrode
And be connected with lead-out terminal 73, MOS transistor M13 constitutes reference voltage generating unit 72 together with MOS transistor M14.
The MOS transistor M13 of depletion type carrys out work as current source, and the source current of MOS transistor M13 is brilliant as MOS
The drain current of body pipe M14 flows through, and the threshold voltage (such as 2.0V) of consequent MOS transistor M14 is as reference voltage
VREF exports from terminal 73.
Here, MOS transistor as shown in Figure 3 M1～M15, except MOS transistor M13, M14, entirely enhancement mode
High withstand voltage MOS transistor.On the contrary, depletion type n-channel MOS M13 is due to passing through such as diffusion method on the surface of p-type substrate
Form the raceway groove of N-shaped so being low pressure, in addition, MOS transistor M14 is the low pressure n-channel MOS of enhancement mode.
Reference voltage generating unit 72 is the low voltage holding circuit being made up of MOS transistor M13 and M14.When being made with high withstand voltage MOS transistor
Make during depletion-type mos transistor that (- 0.4V is attached for Vt it is difficult to stably set negative pinch-off voltage (pinch offvoltage)
Closely), and manufacturing cost also rises.
The source electrode of MOS transistor M14 and the grid of n-channel MOS M15 and the grid of drain electrode and MOS transistor M3
Pole connects, the source ground of MOS transistor M15.Thus, MOS transistor M15, M3 constitutes current mirroring circuit.
<The action of reference voltage circuit>
When after accessing power supply, power vd D1 rises from 0V, the charging current of capacitor C1 flows through resistance R1, by resistance
R1MOS transistor M turns on.Thus, the drain current of MOS transistor M1 flows through resistance R2, and the voltage of junction point A rises, and MOS is brilliant
Body pipe M7 turns on, and the source current of MOS transistor M7 flows through resistance R2, and the voltage of junction point B rises.
The source current of MOS transistor M7 is the drain current of MOS transistor M6, so being electric current with MOS transistor M6
The drain current of the MOS transistor M10 of mirror structure becomes the value proportional to the drain current of MOS transistor M6.MOS transistor
The drain current of M10 flows through MOS transistor M11-1～M11-n, is thus connected the voltage V of point CC(3) formula that is clamped at represents
Voltage.
The drain current of MOS transistor M12 is the voltage V based on junction point CCFixed value, by this drain current stream
Cross MOS transistor M13, M14, reference voltage generating unit 72 is from terminal 73 output reference voltage VREF.
In addition, the drain current of MOS transistor M14 is substantially fixing, the drain current of MOS transistor M14 is MOS crystal
The drain current of pipe M15, MOS transistor M15, M3 be current-mirror structure, so flow through in the drain electrode of MOS transistor M3 with
The corresponding electric current of drain current of MOS transistor M15.And then, because MOS transistor M2, M4 are current-mirror structure, so
Approximately fixed electric current corresponding with the drain current of MOS transistor M3 is flow through in the drain electrode of MOS transistor M4.
Hereafter, even if the charging of capacitor C1 terminates MOS transistor M1 cut-off, by the MOS crystal of electric current supply unit 62
The action of pipe M2, M3, the drain current of MOS transistor M4 also can substantially fixedly proper flow, so the voltage of junction point A is not
Can reduce.Additionally, by by the Voltage Feedback of junction point B to MOS transistor M5, the voltage of junction point A by approximately fixed be solid
Determine voltage, the drain current of MOS transistor M6, M10 is approximately fixed.
<The variation of reference voltage circuit>
Fig. 4 represents that the semiconductor integrated circuit of the present invention is the variation of an embodiment of reference voltage circuit 46
Circuit structure diagram.In the diagram, boot portion 61 is replaced to be provided with boot portion 64.Boot portion 64 has comparator 65, DC source
66th, MOS transistor M2, resistance R2.The non-inverting input terminal of comparator 65 is supplied to reference voltage Vr from DC source 66, than
It is supplied to the voltage of lead-out terminal 73 compared with the reversed input terminal of device 65, the output of comparator 65 is supplied to MOS transistor M1
Grid.Additionally, reference voltage Vr is set to value (such as 1.5～1.9V journey of not enough reference voltage V REF (such as 2.0V)
Degree).
In the diagram, when after accessing power supply, power vd D1 rises from 0V, reference voltage V REF deficiency reference voltage Vr's
Period, the drain current of the MOS transistor M1 exporting high level by comparator 65 and turning on flows through resistance R2, junction point A's
Voltage rises MOS transistor M7 conducting, and the source current of MOS transistor M7 flows through resistance R2, and the voltage of junction point B rises.
The source current of MOS transistor M7 is the drain current of MOS transistor M6, so being electric current with MOS transistor M6
The drain current of mirror structure MOS transistor M10 becomes the value proportional to the drain current of MOS transistor M6.By flowing through MOS
The drain current of transistor M10, the voltage V of junction point CCTo be represented with (3) formula.
The drain current of MOS transistor M12 becomes the voltage V based on junction point CCValue, flow through by this drain current
MOS transistor M13,14, reference voltage generating unit 72 is from terminal 73 output reference voltage VREF.
The drain current of MOS transistor M14 is the drain current of MOS transistor M15, and MOS transistor M15, M3 are electric current
Mirror structure, so flow through electric current corresponding with the drain current of M15 in the drain electrode of MOS transistor M3.And, MOS transistor
M2, M4 are current-mirror structure, so flowing through electricity corresponding with MOS transistor M3 drain current in the drain electrode of MOS transistor M4
Stream.
Hereafter, end, by MOS transistor M4 even if reference voltage V REF is reference voltage Vr above MOS transistor M1
The voltage of drain current junction point A also will not reduce, the voltage of junction point B is fed back to MOS transistor M5, is thus connected a little
By approximately fixed for predetermined voltage, the drain current of MOS transistor M6, M10 is approximately fixed to the voltage of A.
And then, when due to power vd D1 moment disconnect make reference voltage V REF deficiency reference voltage Vr when, due to than
Compared with the output mos transistor M1 conducting of device 65, it is possible to reference voltage V REF is reverted to predetermined voltage (such as 2.0V).
Show in Fig. 5 between the voltage of power vd D1 and the output voltage of adjuster circuit 47 in the terminal 45 of Fig. 2
Relation.There is illustrated situations below：When having carried out pincers using MOS transistor M11-1～M11-n in reference voltage circuit 46
During position, even if power vd D1 rises to maximum rated 30V and also can protect reference voltage circuit 46, the output electricity of adjuster circuit 47
It is pressed in 5V stable.
Additionally, being than existing npn for clamping the chip area shared by MOS transistor M11-1～M11-n of voltage
The slightly larger degree of chip area shared by bipolar transistor 21, by using MOS transistor M11-1～M11-n, hardly
Increase the area of high withstand voltage chip 41.
Claims (4)
1. a kind of semiconductor integrated circuit is it is characterised in that have：
Constant current portion, it is supplied to power supply and produces constant current, and wherein said power supply is first voltage；
Clamp portion, its be supplied to produced by described constant current portion constant current and first voltage described in producing ratio low
Two voltages, the power supply of described first voltage is clamped in described second voltage；And
Reference voltage generating unit, it is supplied to the power supply after being clamped by described clamp portion and produces reference voltage,
Described clamp portion is to be connected and n level MOS transistor that longitudinal type is formed by connecting grid with drain electrode,
The n level MOS transistor that described longitudinal type is formed by connecting is operated in zone of saturation,
Using described constant current IREF, the degree of excursion μ of electronicsn, the grid capacity C of per unit areaox, the grid of MOS transistor
Width W, the grid length L of MOS transistor, the critical voltage V of MOS transistorth, to be expressed as described second electricity with following formula
The Vc of pressure,
VC=n × [2 × IREF/(μnCox)]1/2×(L/W)1/2+n×Vth.
2. semiconductor integrated circuit according to claim 1 it is characterised in that
Described constant current portion has：
Current stabilization portion, it by current stabilization and exports described constant current；
First boot portion, in certain period that the power supply that it is described first voltage in access rises, to described current stabilization portion
Supply the power supply for described first voltage；And
Electric current supply unit, it corresponds to described current stabilization portion for giving the electric current flowing through in described reference voltage generating unit
Electric current.
3. semiconductor integrated circuit according to claim 1 it is characterised in that
Described constant current portion has：
Current stabilization portion, it by current stabilization and exports described constant current；
Second boot portion, during reference voltage that it produces in described reference voltage generating unit is not enough predetermined reference voltage, to
Described current stabilization portion supplies the power supply for described first voltage；And
Electric current supply unit, it corresponds to described current stabilization portion for giving the electric current flowing through in described reference voltage generating unit
Electric current.
4. semiconductor integrated circuit according to any one of claim 1 to 3 it is characterised in that
Described reference voltage generating unit has：
First MOS transistor of depletion type, its drain electrode is supplied to power supply, grid and source electrode and institute after being clamped by described clamp portion
The lead-out terminal stating reference voltage connects；And
Second MOS transistor of enhancement mode, its grid and drain electrode are connected with the lead-out terminal of described reference voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011-210733 | 2011-09-27 | ||
| JP2011210733A JP5849567B2 (en) | 2011-09-27 | 2011-09-27 | Semiconductor integrated circuit |
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| Publication Number | Publication Date |
|---|---|
| CN103023480A CN103023480A (en) | 2013-04-03 |
| CN103023480B true CN103023480B (en) | 2017-03-01 |
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| NL2014280B1 (en) * | 2015-02-12 | 2016-10-13 | Univ Delft Tech | Level shifter. |
| CN106020330A (en) * | 2016-07-22 | 2016-10-12 | 四川和芯微电子股份有限公司 | Low-power-consumption voltage source circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101488362A (en) * | 2008-01-08 | 2009-07-22 | 三美电机株式会社 | Semiconductor device |
| CN101820255A (en) * | 2010-04-12 | 2010-09-01 | 湖北大学 | Voltage follower for high voltage input |
| CN102053645A (en) * | 2011-01-31 | 2011-05-11 | 成都瑞芯电子有限公司 | Wide-input voltage high-power supply rejection ratio reference voltage source |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01217611A (en) * | 1988-02-26 | 1989-08-31 | Sharp Corp | Constant voltage generating circuit |
| JP4703133B2 (en) * | 2004-05-25 | 2011-06-15 | ルネサスエレクトロニクス株式会社 | Internal voltage generation circuit and semiconductor integrated circuit device |
| JP5040397B2 (en) * | 2007-03-28 | 2012-10-03 | 富士電機株式会社 | Reference voltage circuit |
| JP5245871B2 (en) * | 2009-01-30 | 2013-07-24 | ミツミ電機株式会社 | Reference voltage generation circuit |
-
2011
- 2011-09-27 JP JP2011210733A patent/JP5849567B2/en active Active
-
2012
- 2012-09-26 CN CN201210364883.5A patent/CN103023480B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101488362A (en) * | 2008-01-08 | 2009-07-22 | 三美电机株式会社 | Semiconductor device |
| CN101820255A (en) * | 2010-04-12 | 2010-09-01 | 湖北大学 | Voltage follower for high voltage input |
| CN102053645A (en) * | 2011-01-31 | 2011-05-11 | 成都瑞芯电子有限公司 | Wide-input voltage high-power supply rejection ratio reference voltage source |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5849567B2 (en) | 2016-01-27 |
| JP2013073341A (en) | 2013-04-22 |
| CN103023480A (en) | 2013-04-03 |
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