CN103021830A - Wafer processing method - Google Patents
Wafer processing method Download PDFInfo
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- CN103021830A CN103021830A CN2012103496086A CN201210349608A CN103021830A CN 103021830 A CN103021830 A CN 103021830A CN 2012103496086 A CN2012103496086 A CN 2012103496086A CN 201210349608 A CN201210349608 A CN 201210349608A CN 103021830 A CN103021830 A CN 103021830A
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- wafer
- processing method
- etching
- wafer processing
- nanostructured layers
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- 238000003672 processing method Methods 0.000 title claims abstract description 55
- 238000005530 etching Methods 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000002086 nanomaterial Substances 0.000 claims abstract description 16
- 239000007788 liquid Substances 0.000 claims description 25
- 239000002245 particle Substances 0.000 claims description 11
- 239000002061 nanopillar Substances 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- SQGYOTSLMSWVJD-UHFFFAOYSA-N silver(1+) nitrate Chemical compound [Ag+].[O-]N(=O)=O SQGYOTSLMSWVJD-UHFFFAOYSA-N 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 4
- 229910017604 nitric acid Inorganic materials 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 2
- 229910021641 deionized water Inorganic materials 0.000 claims description 2
- 229910001961 silver nitrate Inorganic materials 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 17
- 230000008569 process Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000005336 cracking Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 131
- 238000005516 engineering process Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 229960000583 acetic acid Drugs 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012362 glacial acetic acid Substances 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
The invention provides a wafer processing method which can be used for improving the strength of a wafer, wherein the wafer is provided with a plurality of surfaces, and the surfaces comprise a largest surface with the largest area and side surfaces connected with the edges of the largest surface. The wafer processing method of the present invention comprises the steps of: etching the side surface of the wafer by an etching method to form a nano-structure layer capable of dispersing the stress of the wafer. Therefore, the wafer processed by the method has good anti-cracking performance, and can be prevented from being worn or even cracked due to external force in a semiconductor process or other processing processes.
Description
Technical field
The present invention relates to a kind of wafer processing method, specifically, the invention relates to a kind of processing method of producing the wafer with high resistance disruptiveness.
Background technology
In recent years electronic industry development is advanced by leaps and bounds, and various multi-functional portable electronic products are as intelligent mobile phone, mobile computer, flat computer etc. have all incorporated in the people's life, so that people's life is more and more convenient.In the behind of electronic industry development, the maturation development that is located thereon the semiconductor industry of trip has great contribution.Except the people's livelihood, Military Electronics industry, energy aspect such as solar energy industry and illumination aspect such as LED industry all have the relevance of quite large degree with semiconductor industry.In addition, semi-conductive technology also can be applicable to other fields such as living skill, and it is wide that it involves scope, and the foundation stone that is referred to as science and technology in modern age was not yet.
The wafer that semiconductor technology is produced can be widely used in the above-mentioned various application, and the yield of wafer can say the quality that has directly determined end product, and therefore, all circles all have high input quantity research to guarantee its quality on the material of wafer and production method.No matter it is the wafer of which kind of application, must pass through the multiple tracks processing technology, for example, wafer cutting, etching, surface treatment, encapsulation, IC test supervisor, could obtain electronic building brick or the photoelectric subassembly of practical application.
In the technique of above-mentioned various processing wafers, wafer often can be subject to the different External Force Acting of degree.Generally speaking, various functional structures are arranged on the main surface that wafer has maximum area usually on the wafer, and each structure often can cause defective on the material at wafer, and easily produce the phenomenon that stress are concentrated in these defectives.When suffered external force increased gradually, the stress concentration phenomenon on these zones can be more violent.Because present wafer material all is the material of using fragility, for example, Silicon Wafer, therefore above-mentioned stress concentration phenomenon easily so that the wafer stress place of concentrating produces slight crack even causes wafer breakage, and then reduces the wafer yield and improves simultaneously its production cost.
Summary of the invention
The invention provides a kind of wafer processing method of producing the wafer with high resistance disruptiveness, the problem that exists to solve prior art.
One specific embodiment according to the present invention, the wafer that wafer processing method of the present invention is processed has a plurality of surfaces, and it is included in a largest face that has maximum area in each surface, and the side surface that connects described largest face edge.Wafer processing method comprises the following step: with the side surface of lithographic method etched wafer, to form the nanostructured layers with dispersive stress function on described side surface, to disperse the stress of wafer.
In this specific embodiment, can comprise a plurality of nanostructures with the nanostructured layers that lithographic method was etched, each nanostructure can form stress concentration point on the side surface respectively at wafer, when wafer is stressed, on the nanostructured layers a plurality of stress concentration points with stress dispersion to the whole nanostructured layers, therefore, can avoid stress concentration on the functional structure of wafer, and then prevent that wafer from producing slight crack even break.
Can be described in detail and accompanying drawing is further understood by following about the advantages and spirit of the present invention.
Description of drawings
Figure 1 shows that the flow chart of steps of the one specific embodiment wafer processing method according to the present invention.
Fig. 2 A is depicted as the not schematic diagram of the wafer of the wafer processing method processing of process Fig. 1.
Fig. 2 B is depicted as the schematic diagram through the wafer after the wafer processing method processing of Fig. 1.
The wafer processing method that Figure 3 shows that Fig. 1 is processed the actual look enlarged drawing of the nanostructured layers that the side surface of wafer obtains.
Figure 4 shows that the chart of the corresponding etch period of tension force that wafer that the wafer processing method of another specific embodiment according to the present invention obtains can bear.
The schematic diagram of the wafer processing method that Figure 5 shows that another specific embodiment according to the present invention after to each side surface etching of wafer.
Figure 6 shows that the generalized section through the wafer after the wafer processing method processing of Fig. 1.
Reference numeral:
S10 ~ S16: process step 2,3: wafer
20,30: largest face 22,32: side surface
220,320: nanostructured layers 222: nano-pillar
224: nanoneedle R: reference line
Embodiment
The invention provides a kind of wafer processing method, can be used to promote resistance to rupture and the intensity of wafer.According to a specific embodiment, wafer processing method of the present invention mainly comprises following steps: with the side surface of lithographic method etched wafer, to form nanostructured layers on side surface.Can disperse the suffered stress of wafer with the nanostructured layers on the side surface of the wafer after the method processing, and further promote die strength.
See also Fig. 1 and Fig. 2 A ~ Fig. 2 B, Figure 1 shows that the flow chart of steps of the wafer processing method of one specific embodiment according to the present invention, Fig. 2 A is depicted as the not schematic diagram of the wafer 2 of the wafer processing method processing of process Fig. 1, and Fig. 2 B is depicted as the schematic diagram through the wafer 2 after the wafer processing method processing of Fig. 1.
Shown in Fig. 2 A, wafer 2 can have a plurality of surfaces, and wherein, largest face 20 has area maximum in each surface, 22 edges that connect largest face 20 of side surface.On the practice, wafer be shaped as circle or square sheet, that is the area of side surface is less.Generally speaking, the functional structure wafer arranges such as electrodes such as grid, drain electrode or source electrodes, is arranged on the largest face usually, does not have enough spaces on the side surface above-mentioned functions structure can be set.
As shown in Figure 1, this specific embodiment wafer processing method comprises the following step: step S10, with the native oxide on the wafer 2 of buffer oxide etching liquid (BOE) removing Fig. 2 A; Step S12 is with the first mechanical damage layer of removing on the liquid removing wafer 2; Step S14 immerses side surface 22 in the etching liquid, in the given time side surface 22 is carried out etching; Step S16 removes liquid with second after the etching and removes residual etching liquid molecule particle on the side surface 22.Note that behind the etching technics of step S14, namely form nanostructured layers 220 on the side surface 22, shown in Fig. 2 B.
In this specific embodiment, wafer 2 is a silicon wafer, because silicon atom is oxidation formation native oxide under the environment of oxygenous and water easily, and this native oxide will hinder etching, therefore removes native oxide with the buffer oxide etching liquid first in the step S10 of wafer processing method.In addition, wafer 2 has passed through the multiple tracks processing technology, for example, wafer cutting or surface treatment, may be subject to the mechanical damage layer that above-mentioned processing technology causes on its surface, therefore in the step S12 of wafer processing method, with the first mechanical damage layer of removing on the liquid removing wafer 2.In the practice, first removes liquid can be by hydrofluoric acid (HF) solution of concentration 49%, nitric acid (HNO3) solution and the glacial acetic acid (CH3COOH) of concentration 70%, mixes according to the volume ratio of 2:7:1.By the above-mentioned first processing of removing liquid, the mechanical damage layer of 15 ~ 20 micron thickness on about removable wafer 2 in 30 seconds.
After through native oxide and mechanical damage layer on step S10 and the step S12 removing wafer 2, can carry out the etching technics of step S14.The employed etching liquid of step S14 can be that the hydrofluoric acid (HF) of concentration ratio 250:1 and silver nitrate (AgNO3) are mixed in the solvent and get in practice.The molecule particle of the residual etching liquid of common meeting on the side surface 22 after the etching; these residual molecule particles may affect the characteristic of wafer 2 itself; perhaps in subsequent technique, produce harmful effect, therefore in step S16, remove liquid with second and remove residual molecule particle on the wafer 2.As mentioned above, contain silver in the etching liquid composition of this specific embodiment, therefore residual etching molecule particle is silver-colored molecule particle after the etching.Second removes liquid then can be nitric acid and deionized water and mixes according to the volume ratio of 1:3, is used for removing residual silver-colored molecule particle.
According to the wafer processing method of this specific embodiment, comprise a large amount of nanostructures in the nanostructured layers 220 that etches on wafer 2 side surfaces 22, these nanostructures further are nano-pillar or nanoneedle.See also Fig. 3, the wafer processing method that Figure 3 shows that Fig. 1 is processed the actual look enlarged drawing of the nanostructured layers 220 that the side surface 22 of wafer 2 obtains.As shown in Figure 3, nanostructured layers 220 comprises nano-pillar 222 and nanoneedle 224, and wherein, the distance between two adjacent nanostructure tops is between 10 nanometer to 1000 nanometers, and the etching depth of whole nanostructure is between 0.1 micron to 100 microns.The nanostructured layers 220 that note that Fig. 3 is got by above-mentioned etching liquid etching 20 minutes, that is to say, the scheduled time among the step S14 is 20 minutes.
With the nano-pillar 222 and nanoneedle 224 that the wafer processing method of this specific embodiment is made, the defective of meeting on side surface 22 and each nanostructure place of interconnecting formation material.In addition, being etched the nano-pillar 222 that produces itself may be also with fault in material with nanoneedle 224.Generally speaking, the phenomenon that stress is concentrated easily occurs in the fault in material place, and in other words, when wafer 2 was subject to tension force, nano-pillar 222, nanoneedle 224, both may have the concentrated phenomenon of stress with side surface 22 junctions or each nanostructure place of being connected to each other.
Because nano-pillar 222 belongs to nanoscale with the size of nanoneedle 224, and the nanoneedle 224 that comprises a myriad of in the nanostructured layers 220 is dispersed throughout wherein with nano-pillar 222, is formed therefore nanostructured layers 220 is covered in the fault in material point that the part of side surface 22 can be considered by a myriad of.When wafer 2 was subjected to tension force, nanostructured layers 220 concentrated on the stress on the wafer 2 respectively on the formed fault in material point of all nanostructures.With regard to the result, stress is to be scattered in the part that is covered by nanostructured layers 220 on the whole side surface 22 on the contrary, and in other words, this is the stress dispersion phenomenon of a face, but not the stress concentration phenomenon of point or line.
Be dispersed to other position of avoiding concentrating on wafer 2 on the nanostructured layers 220 of side surface 22 owing to stress, for example, the formed fault in material of functional structure or wafer 2 carried out the fault in material that other handling procedure causes on the largest face 20.Therefore, the nanostructured layers 220 that has the stress dispersion effect in this specific embodiment can help wafer 2 opposing tension force, in other words, can promote the intensity of wafer 2 resistance to fractures own.
The wafer processing method of this specific embodiment, the etching scheduled time of step S14 is 20 minutes, however in practice, the scheduled time can be more than 20 minutes, was not limited to 20 minutes.See also Fig. 4, Figure 4 shows that the chart of the corresponding etch period of tension force that wafer that the wafer processing method of another specific embodiment according to the present invention obtains can bear.As shown in Figure 4, the tension force that the longitudinal axis in the chart does not break for wafer can bear, transverse axis is the etching scheduled time of the wafer processing method of above-mentioned specific embodiment, in addition, the wafer that reference line R representative is processed without the wafer processing method of this specific embodiment, it can bear and the maximum tension that do not break.
By can finding out among Fig. 4, etching surpasses the maximum tension that 20 minutes wafer can bear and is about 3N, the maximum tension 2N that can bear greater than the wafer of processing without the wafer processing method of this specific embodiment.When etching surpassed 20 minutes, along with the lengthening of the scheduled time, the maximum tension that wafer can bear is thereupon stable increase also.Hence one can see that, and the wafer processing method of this specific embodiment can help wafer to resist the intensity of breaking and increasing wafer really.
Above-mentioned wafer 2 be shaped as rectangle, therefore two largest face 20 and four side surfaces 22 should be arranged.In the practice, the step S14 of wafer processing method can be respectively carries out etching to all side surfaces of wafer, all can form nanostructured layers on all side surfaces.See also Fig. 5, Figure 5 shows that the schematic diagram after another specific embodiment wafer processing method according to the present invention is to each side surface 32 etching of wafer 3.As shown in Figure 5, only one of them side surface 22 of wafer 2 is carried out etching compared to Fig. 1, the method of all side surfaces 32 being carried out etching can form the larger nanostructured layers of area 320, therefore stress can be dispersed to more on the large tracts of land, and make wafer 3 have resistance to rupture and the intensity higher than wafer 2.
In above-mentioned specific embodiment, the side surface of wafer immersed in the etching liquid form nanostructured layers, the edge that largest face is connected in side surface also can immerse in the etching liquid and be etched.See also Fig. 6, Figure 6 shows that the generalized section through the wafer 2 after the wafer processing method processing of Fig. 1.As shown in Figure 6, in edge one scope that the largest face 20 of wafer 2 is connected with side surface 22, being etched equally forms nanostructured layers 220, and the nanostructured layers 220 that is formed at largest face 20 edges also can help wafer 2 opposing tension force.Generally speaking, see through the nanostructured layers that the wafer processing method of this specific embodiment forms in largest face, its scope from the largest face edge towards the center along stretching 1 centimetre, yet the present invention is not limited this.In the practice, according to the degree of depth of wafer material and wafer immersion etching liquid, nanostructured layers can have different scopes in largest face, is as the criterion with the functional structure on the face that do not have the greatest impact.
In above-mentioned each specific embodiment, the nanostructured layers that is positioned at wafer side face forms with the etching liquid etching, and it is a kind of wet-etching technology.Yet the present invention does not limit with wet-etching technology and forms nanostructured layers, anyly can be all the claimed scope of wafer processing method of the present invention at the lithographic method that wafer side face forms nanostructured layers.
In another specific embodiment, wafer processing method can carry out etching to the side surface of wafer with the method for etching plasma of dry method.In detail, utilize the bias voltage in the plasma chamber to make the interior charged particle of plasma clash into the side surface of wafer, and then form nanostructured layers at side surface.Because method for etching plasma is different from the etching mechanism of above-mentioned wet etching method, therefore formed nanostructured layers may comprise and the nanostructure that nano-pillar or the different kenels of nanoneedle are arranged.In addition, the pre-treatment of dry etch process and post-processing step also may be different with above-mentioned wet-etching technology, therefore wafer processing method of the present invention can have corresponding treatment step according to different etching technique.
In sum, wafer processing method of the present invention can etching form nanostructured layers on the side surface of wafer, and a large amount of nanostructures of scattering in the nanostructured layers can be disperseed the stress on the wafer.Compared to conventional wafer, the wafer of processing its side surface through wafer processing method of the present invention has stronger resistance to rupture, that is higher than the intensity of conventional wafer.Wafer processing method of the present invention is more difficult because being subject to tension force breaks in general processing technology except helping wafer, also can make the higher resistance to rupture of the tool of wafer own and intensity and can stand the more processing technology of high-tension, and usefulness and its applicable field of further having improved wafer.
By being described in detail of above preferred embodiment, hope can be known description feature of the present invention and spirit more, and is not to come category of the present invention is limited with above-mentioned disclosed preferred embodiment.On the contrary, its objective is the arrangement of wishing in the category of the claim of institute of the present invention wish application, to contain various changes and tool equality.Therefore, the category of the claim that the present invention applies for should be done the broadest explanation according to above-mentioned explanation, contains the arrangement of all possible change and tool equality to cause it.
Claims (12)
1. wafer processing method, in order to promote the intensity of wafer, described wafer has a plurality of surfaces, and the side surface that described a plurality of surface comprises the largest face with maximum area and connects described largest face one edge, described method comprises the following step: with the described side surface of the described wafer of a lithographic method etching, to form the nanostructured layers in order to the stress that disperses described wafer on described side surface.
2. wafer processing method according to claim 1 is characterized in that, described nanostructured layers includes a plurality of nanostructures.
3. wafer processing method according to claim 2 is characterized in that, the shape of described a plurality of nanostructures comprises in nano-pillar and the nanoneedle at least one.
4. wafer processing method according to claim 3 is characterized in that, the spacing on two adjacent described nanostructure tops is between 10 nanometer to 1000 nanometers.
5. wafer processing method according to claim 2 is characterized in that, the degree of depth of described nanostructure is between 0.1 micron to 100 microns.
6. wafer processing method according to claim 1 is characterized in that, described lithographic method is the wet etching method.
7. wafer processing method according to claim 6 is characterized in that, described wet etching method comprises the following step: described side surface is immersed in the etching liquid, within the scheduled time described side surface is carried out etching; And remove liquid with one after the etching and remove etching liquid molecule particle residual on the described side surface.
8. wafer processing method according to claim 7 is characterized in that, described etching liquid is mixed in the solvent according to the predetermined concentration ratio by hydrofluoric acid and silver nitrate and forms.
9. wafer processing method according to claim 8 is characterized in that, the described scheduled time was greater than 20 minutes.
10. wafer processing method according to claim 8 is characterized in that, after the etching on the described side surface residual etching liquid molecule particle be silver-colored molecule particle, and described removing liquid is mixed according to a predetermined ratio by nitric acid and deionized water at least.
11. wafer processing method according to claim 1 is characterized in that, described lithographic method is method for etching plasma.
12. wafer processing method according to claim 1, it is characterized in that, adopt the step of the described side surface of the described wafer of described lithographic method etching, further form in the scope of described nanostructured layers on the described edge of described largest face, and described scope is stretched 1 centimetre in edge, the center towards described largest face from described edge.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100133875A TWI515780B (en) | 2011-09-21 | 2011-09-21 | Wafer processing method |
| TW100133875 | 2011-09-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103021830A true CN103021830A (en) | 2013-04-03 |
| CN103021830B CN103021830B (en) | 2016-09-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210349608.6A Expired - Fee Related CN103021830B (en) | 2011-09-21 | 2012-09-20 | Wafer processing method |
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| TW (1) | TWI515780B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105845757A (en) * | 2015-01-14 | 2016-08-10 | 叶哲良 | Bendable solar chip capable of optimizing thickness and conversion efficiency |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW460961B (en) * | 1999-05-21 | 2001-10-21 | Plasmasil Llc | A method of processing semiconductor wafers |
| US20090181525A1 (en) * | 2005-01-07 | 2009-07-16 | Park Sung-Soo | Wafer structure and epitaxial growth method for growing the same |
| TW201007892A (en) * | 2008-08-06 | 2010-02-16 | Jer-Liang Yeh | Substrate with high fracture strength |
| TW201111272A (en) * | 2009-09-25 | 2011-04-01 | Jing-Tang Yang | A novel method of self-assembling monolayer and the reaction time controlled for the formation of surfaces with controllable wettability |
-
2011
- 2011-09-21 TW TW100133875A patent/TWI515780B/en not_active IP Right Cessation
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2012
- 2012-09-20 CN CN201210349608.6A patent/CN103021830B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW460961B (en) * | 1999-05-21 | 2001-10-21 | Plasmasil Llc | A method of processing semiconductor wafers |
| US20090181525A1 (en) * | 2005-01-07 | 2009-07-16 | Park Sung-Soo | Wafer structure and epitaxial growth method for growing the same |
| TW201007892A (en) * | 2008-08-06 | 2010-02-16 | Jer-Liang Yeh | Substrate with high fracture strength |
| TW201111272A (en) * | 2009-09-25 | 2011-04-01 | Jing-Tang Yang | A novel method of self-assembling monolayer and the reaction time controlled for the formation of surfaces with controllable wettability |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105845757A (en) * | 2015-01-14 | 2016-08-10 | 叶哲良 | Bendable solar chip capable of optimizing thickness and conversion efficiency |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI515780B (en) | 2016-01-01 |
| TW201314754A (en) | 2013-04-01 |
| CN103021830B (en) | 2016-09-07 |
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