CN102968538B - The modeling method of PSP mismatch model of MOS transistor - Google Patents
The modeling method of PSP mismatch model of MOS transistor Download PDFInfo
- Publication number
- CN102968538B CN102968538B CN201210506129.0A CN201210506129A CN102968538B CN 102968538 B CN102968538 B CN 102968538B CN 201210506129 A CN201210506129 A CN 201210506129A CN 102968538 B CN102968538 B CN 102968538B
- Authority
- CN
- China
- Prior art keywords
- mis
- mismatch
- model
- psp
- wot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses the modeling method of a kind of PSP mismatch model of MOS transistor (mismatch model), be included on standard P SP model part and increase device performance mismatch submodule, this device performance mismatch submodule comprises the fitting parameter relevant to device performance mismatch and parametric equation, and fitting parameter is the influence coefficient of device performance mismatch to the basic parametric t oxo of PSP model, vfbo and wot influence degree.Wherein this device performance mismatch submodule passes through described influence coefficient to transistor linearity threshold voltage V
tlin, saturation threshold voltage V
tsat, linear drain current I
dlinwith saturated drain current I
dsatvariation characteristic apply impact, the flat-band voltage vfbo that determining device performance mismatch has nothing to do to gate oxide thickness toxo and size and blocked the effect of effective channel width variable quantity wot that the transverse dispersion of adulterating causes by raceway groove, redefines described gate oxide thickness toxo, the described flat-band voltage vfbo that has nothing to do with size and describedly blocks by raceway groove effective channel width variable quantity wot that the transverse dispersion of adulterating causes.
Description
Technical field
The invention belongs to integrated circuit fields, particularly relate to a kind of modeling method of MOS transistor PSP mismatch (mismatch) model.
Background technology
The technological fluctuation of various degrees in ic manufacturing process, the device performance in every sequence of process steps all may affect performance and the cost rate of chip.Along with the development of microelectric technique, in CMOS integrated circuit technology, device feature size and gate oxide thickness have reached dark nanometer scale, although device performance is improved, but circuit also becomes more responsive for technological fluctuation, the impact of technological fluctuation on performance of integrated circuits of device property is more serious.Therefore in integrated circuit design for technological fluctuation consideration and estimate and seem very important.
As integrated circuit (IC) design and the important bridge between manufacturing, MOSFET element model can estimate the impact of technological fluctuation in various physical influence and ic manufacturing process in chip effectively.In MOSFET element model, consider mismatch (mismatch) model, effectively can estimate the impact of technological fluctuation in dark nanometer scale device manufacturing processes.Therefore a kind of SPICE model with accurate mismatch model parameter can more accurately for integrated circuit (IC) design slip-stick artist predicts the device electrology characteristic considered in technological fluctuation situation.
Technological fluctuation problem has just caused the concern of expert scholar at the end of the nineties in last century.People's researchs such as Nassif.S.R draw the technological fluctuation only can not considering chip chamber, because the proportional of device size reduces, the process sensitive degree of chip increases, consider and estimate technological fluctuation (the i.e. mismatch attribute of chip internal in a chip design, refer to position in same wafer to close on and the electrology characteristic difference existed between the identical device of dimensional structure), effectively can improve performance and the yield rate of chip.Traditional method is to a large amount of IV performance data of each device collection, then uses optimization method extraction device model parameter.This method accurately but very consuming time.The people such as Purviance are the S parameter measured values carrying out approximate representation MESFET with the linear combination of one group of mutual uncorrelated random variables with its main thought of statistical model that principal component analysis establishes MESFET.For deep sub-micro MOSFET device, short-channel effects mismatch (mismatch) attribute, and therefore the people such as Bastos adds short-channel effect part in their mismatch research.
In recent years, more domestic scholars were also studied the impact that technological fluctuation produces, as Xian Electronics Science and Technology University achieves certain achievement in the interconnection considering technological fluctuation.But it is also little in the research of systematically setting up integrated circuit MOSFET technological fluctuation model.
PSP model based on surface potential is distributed by Exact Solution channel surface gesture, thus obtain the equation of electric charge and electric current, it is more accurate to the description of device property, is current industry widely used model when nanometer scale standard technology MOSFET carries out modeling.PSP SPICE model provides model module comprehensive in a large number.The present invention is on the basis of original standard P SP model, by adding device performance mismatch parameter and parametric equation thereof to PSP SPICE model platform with the form of electronic circuit, mismatch (mismatch) model relevant to device performance mismatch of Erecting and improving, more adequately technological fluctuation analysis and the emulation of device electrology characteristic can be carried out to designed circuit, thus improve performance and the yield rate of device.
Summary of the invention
The object of the present invention is to provide a kind of modeling method of MOS transistor PSP mismatch (mismatch) model, standard P SP model part increases device performance mismatch submodule.This device performance mismatch submodule comprises the fitting parameter relevant to device performance mismatch and parametric equation, the fitting parameter flat-band voltage vfbo that to be device performance mismatch have nothing to do to PSP model basic parameter gate oxide thickness toxo and size and blocked the influence coefficient of effective channel width variable quantity wot influence degree that the transverse dispersion of adulterating causes by raceway groove.This device performance mismatch submodule passes through described influence coefficient to transistor linearity threshold voltage V
tlin, saturation threshold voltage V
tsat, linear drain current I
dlinwith saturated drain current I
dsatvariation characteristic apply impact, revise the expression formula of toxo, vfbo and wot described in PSP model, the i.e. flat-band voltage vfbo that has nothing to do to gate oxide thickness toxo and size of determining device performance mismatch and blocked the effect of effective channel width variable quantity wot that the transverse dispersion of adulterating causes by raceway groove, redefines described gate oxide thickness toxo, the described flat-band voltage vfbo that has nothing to do with size and describedly blocks by raceway groove effective channel width variable quantity wot that the transverse dispersion of adulterating causes.
Described influence coefficient comprises: device performance mismatch is to parameter d toxo_mis, dvfbo_mis and dwot_mis of described toxo, vfbo and wot influence degree.
Described correction in the method for the expression formula of toxo, vfbo and wot in PSP model also comprises intermediate variable dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v of being obtained by the computing of described influence coefficient, participates in the expression of toxo, vfbo and wot.Wherein said dtoxo_mis_v is the variable quantity affecting gate oxide thickness by device performance mismatch; Described dvfbo_mis_v is the variable quantity affecting the flat-band voltage had nothing to do with size by device performance mismatch; Described dwot_mis_v is the variable quantity affecting the effective channel width caused by the transverse dispersion of raceway groove blocking-up doping by device performance mismatch.
Wherein, describedly obtain in the computing of intermediate variable by influence coefficient, comprise the parameter geo_fac relevant to device size, the computing obtaining geo_fac is as follows:
In formula, l is the channel length of MOSFET element, and w is the channel width of MOSFET element.
Wherein, the origin cause of formation of described mismatch (mismatch) model is technological fluctuation, in electrical simulation, think that these fluctuations are what to be caused by the walk random of a lot of independent variable, therefore described intermediate variable meets Gaussian distribution, and the distribution and expression formula of fluctuation is random=agauss (0.0,1.0,1), wherein agauss (0.0,1.0,1) represent that expectation is 0, variance is the Gaussian distribution of 1.
Therefore described intermediate variable dtoxo_mis_v, dvfbo_mis_v, dwot_mis_v are determined by following formula:
dtoxo_mis_v=dtoxo_mis·randoml·geo_fac
dvfbo_mis_v=dvfbo_mis·random2·geo_fac
dwot_mis_v=dwot_mis·random3·geo_fac
In formula
random1=agauss(0.0,1.0,1)
random2=agauss(0.0,1.0,1)
random3=agauss(0.0,1.0,1)。
The flat-band voltage vfbo that the present invention is had nothing to do to described gate oxide thickness toxo and size by intermediate variable dtoxo_mis_v, dvfbo_mis_v, dwot_mis_v, to be blocked effective channel width variable quantity wot that the transverse dispersion of adulterating causes by raceway groove and make correction.The relation of described intermediate variable dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v and toxo, vfbo and wot, the parametric equation that namely toxo, vfbo and wot change by device performance mismatch affects is respectively:
toxo=toxo
original+dtoxo_mis_v
vfbo=vfbo
original+dvfbo_mis_v
wot=wot
original+dwot_mis_v
Toxo in formula
originalbe initial gate oxide thickness value, namely DC Model extracts the gate oxide thickness value obtained; Vfbo
originalbe the initial flat-band voltage value irrelevant with size, namely DC Model extracts the flat-band voltage value irrelevant with size obtained; wot
originalbe the initial change amount that the transverse dispersion blocking doping by raceway groove causes effective channel width to change, namely DC Model extracts the effective channel width variable quantity caused by the transverse dispersion of raceway groove blocking-up doping obtained.
The MOSFET that the present invention is suitable for is the MOSFET comprising 22nm-130nm standard technology.
According to the model that the modeling method of MOS transistor PSP mismatch (mismatch) model of the present invention is set up, its physical meaning is clear and definite, degree of accuracy is high, the device electrology characteristic difference that accurate consideration causes due to technological fluctuation, can carry out more accurately analog simulation to the MOSFET electrology characteristic of different size type.
Accompanying drawing explanation
The schematic block diagram of the model that the modeling method that Fig. 1 is MOS transistor PSP mismatch (mismatch) model of the present invention is set up;
Fig. 2 is σ value σ (the Δ V of NMOSFET linear threshold voltage variable quantity
tlin) with the graph of a relation of geometric parameter factor geo_fac;
Fig. 3 is σ value σ (the Δ V of NMOSFET saturation threshold voltage variety
tsat) with the graph of a relation of geometric parameter factor geo_fac;
Fig. 4 is σ value σ (the Δ I of the linear drain current relative variation of NMOSFET
dlin/ I
dlin) with the graph of a relation of geometric parameter factor geo_fac;
Fig. 5 is σ value σ (the Δ I of NMOSFET saturated drain current relative variation
dsat/ I
dsat) with the graph of a relation of geometric parameter factor geo_fac;
Fig. 6 is σ value the σ (-Δ V of PMOSFET linear threshold voltage variable quantity
tlin) with the graph of a relation of geometric parameter factor geo_fac;
Fig. 7 is σ value the σ (-Δ V of PMOSFET saturation threshold voltage variety
tsat) with the graph of a relation of geometric parameter factor geo_fac;
Fig. 8 is σ value σ (the Δ I of the linear drain current relative variation of PMOSFET
dlin/ I
dlin) with the graph of a relation of geometric parameter factor geo_fac;
Fig. 9 is σ value σ (the Δ I of PMOSFET saturated drain current relative variation
dsat/ I
dsat) with the graph of a relation of geometric parameter factor geo_fac.
Embodiment
The present invention is elaborated further below in conjunction with drawings and Examples.Following examples are not limitation of the present invention, and under the spirit and scope not deviating from inventive concept, the change that those skilled in the art can expect and advantage are all included in the present invention.
The invention provides the modeling method of MOS transistor PSP mismatch (mismatch) model, be in particular the modeling method of 22nm-130nm standard technology MOSFET PSP mismatch (mismatch) model relevant to device performance mismatch.The model physical meaning that the method is set up is clear and definite, degree of accuracy is high, accurately considers the device electrology characteristic difference because technological fluctuation causes, contributes to carrying out more accurately analog simulation to the MOSFET electrology characteristic of different size type.
The inventive method increases device performance mismatch submodule on standard P SP model part.This device performance mismatch submodule comprises the fitting parameter relevant to device performance mismatch and parametric equation, the fitting parameter flat-band voltage vfbo that to be device performance mismatch have nothing to do to PSP model basic parameter gate oxide thickness toxo and size and blocked the influence coefficient of effective channel width variable quantity wot influence degree that the transverse dispersion of adulterating causes by raceway groove.This device performance mismatch submodule by influence coefficient to transistor linearity threshold voltage V
tlin, saturation threshold voltage V
tsat, linear drain current I
dlinwith saturated drain current I
dsatvariation characteristic apply impact, revise the expression formula of toxo, vfbo and wot described in PSP model, with the actual performance enabling the PSP mismatch model obtained by modeling method of the present invention emulate nanoscopic MOSFET device more accurately.That is, this device performance mismatch submodule passes through described influence coefficient to transistor linearity threshold voltage V
tlin, saturation threshold voltage V
tsat, linear drain current I
dlinwith saturated drain current I
dsatvariation characteristic apply impact, the flat-band voltage vfbo that determining device performance mismatch has nothing to do to gate oxide thickness toxo and size and blocked the effect of effective channel width variable quantity wot that the transverse dispersion of adulterating causes by raceway groove, redefines described gate oxide thickness toxo, the described flat-band voltage vfbo that has nothing to do with size and describedly blocks by raceway groove effective channel width variable quantity wot that the transverse dispersion of adulterating causes.
The schematic block diagram of the model that the modeling method that Fig. 1 is MOS transistor PSP mismatch (mismatch) model of the present invention is set up.As shown in Figure 1, the present invention is the model that the modeling method of MOS transistor PSP mismatch (mismatch) model is set up, and computing formula (parametric equation namely in Fig. 1) and the relevant fitting parameter of the PSP SPICE model parameter changed by device performance mismatch affects by three are incorporated in PSP SPICE model platform with the form of electronic circuit.Wherein, three PSP SPICE model parameters are: gate oxide thickness toxo, the flat-band voltage vfbo had nothing to do with size and block effective channel width variable quantity wot that the transverse dispersion of adulterating causes by raceway groove.The main application of present pre-ferred embodiments is to utilize three PSPSPICE parameter calculation formulas and fitting parameter to calculate the concrete numerical value of toxo, vfbo and wot of different channel lengths and width MOSFET, and then is emulated in conjunction with the electrology characteristic of PSP SPICE model platform to MOSFET by the numerical value of these PSP SPICE parameters under different channel lengths and width.
In the present invention, influence coefficient comprises: device performance mismatch is to parameter d toxo_mis, dvfbo_mis and dwot_mis of described toxo, vfbo and wot influence degree.These three parameters are the fitting parameters added in modeling process, its initial value is all set to zero, by regulating the actual test case of the value of these three fitting parameters to device to carry out matching, when matching reaches precision prescribed, the value of these three fitting parameters can be obtained.
Described revise consider device performance mismatch after in PSP model the expression formula of toxo, vfbo and wot method in also comprise intermediate variable dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v of being obtained by the computing of described influence coefficient, participate in the expression of toxo, vfbo and wot.Wherein said dtoxo_mis_v is the variable quantity affecting gate oxide thickness by device performance mismatch; Described dvfbo_mis_v is the variable quantity affecting the flat-band voltage had nothing to do with size by device performance mismatch; Described dwot_mis_v is the variable quantity affecting the effective channel width caused by the transverse dispersion of raceway groove blocking-up doping by device performance mismatch.
Described revise consider device performance mismatch after in PSP model the expression formula of toxo, vfbo and wot method in also comprise by intermediate variable dtoxo_mis_v, dvfbo_mis_v, dwot_mis_v, described gate oxide thickness toxo and size are had nothing to do flat-band voltage vfbo, to be blocked effective channel width variable quantity wot that the transverse dispersion of adulterating causes by raceway groove and make correction.The relation of described intermediate variable dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v and toxo, vfbo and wot, the parametric equation that namely toxo, vfbo and wot change by device performance mismatch affects is respectively:
toxo=toxo
original+dtoxo_mis_v
vfbo=vfbo
original+dvfbo_mis_v
wot=wot
original+dwot_mis_v
Toxo in formula
originalbe initial gate oxide thickness value, namely DC Model extracts the gate oxide thickness value obtained; Vfbo
originalbe the initial flat-band voltage value irrelevant with size, namely DC Model extracts the flat-band voltage value irrelevant with size obtained; wot
originalbe the initial change amount that the transverse dispersion blocking doping by raceway groove causes effective channel width to change, namely DC Model extracts the effective channel width variable quantity caused by the transverse dispersion of raceway groove blocking-up doping obtained.
Wherein, describedly obtain in the computing of intermediate variable by influence coefficient, comprise the parameter geo_fac relevant to device size, the computing obtaining geo_fac is as follows:
In formula, l is the channel length of MOSFET element, and w is the channel width of MOSFET element.
Wherein, the origin cause of formation of described mismatch (mismatch) model is technological fluctuation, in electrical simulation, think that these fluctuations are what to be caused by the walk random of a lot of independent variable, therefore described intermediate variable meets Gaussian distribution, and the distribution and expression formula of fluctuation is random=agauss (0.0,1.0,1), wherein agauss (0.0,1.0,1) represent that expectation is 0, variance is the Gaussian distribution of 1.
Therefore described intermediate variable dtoxo_mis_v, dvfbo_mis_v, dwot_mis_v are determined by following formula:
dtoxo_mis_v=dtoxo_mis·random1·geo_fac
dvfbo_mis_v=dvfbo_mis·random2·geo_fac
dwot_mis_v=dwot_mis·random3·geo_fac
In formula
random1=agauss(0.0,1.0,1)
random2=agauss(0.0,1.0,1)
random3=agauss(0.0,1.0,1)。
First, PSP SPICE model is used to be 0.036-0.9 μm to 40nm standard technology channel length, channel width is that the MOSFET of 0.108-0.9 μm measures, then carries out PSP model parameter extraction, obtains these devices toxo, vfbo, wot SPICE model parameter numerical value.
By with 40nm standard technology MOSFET embodiment, PSP mismatch (mismatch) model how applying modeling method of the present invention acquisition is described in further detail below.
Fig. 2 is the σ value of NMOSFET linear threshold voltage variable quantity and the geometric parameter graph of a relation because of geo_fac.Fig. 6 is the σ value of PMOSFET linear threshold voltage variable quantity and the graph of a relation of geometric parameter factor geo_fac.Under normal temperature, zero lining is applied partially to MOSFET, for having same channel length l and channel width w and 35 MOSFET that present position is closed on wafer carry out linear threshold voltage measurement respectively, NMOSFET measuring condition is Vds (drain voltage)=0.05V, Vgs (grid voltage)=1.8V, Vbs (substrate bias)=0V, PMOSFET measuring condition is Vds=-0.05V, Vgs=-1.8V, Vbs=0V, then the σ value calculating linear threshold voltage variable quantity according to the value of linear threshold voltage and the model of PSP inside.Under different channel length l and channel width w, extract the σ value of the linear threshold voltage variable quantity of each size MOSFET respectively, then the σ value of linear threshold voltage variable quantity is carried out curve fitting, ordinate is the σ value of linear threshold voltage variable quantity, horizontal ordinate 1/sqrt (w*1) is the parameter geo_fac relevant to device size, and (writing for ease of expression formula in model file replaces with sqrt (w*1)
).Figure orbicular spot is test data point, and dotted line is test point trend curve, and side's point is emulated data point, and solid line is simulated point matched curve, makes two curves all cross initial point.For NMOSFET, the expression formula of dotted line is y=0.003*x, and namely dotted line slope is 0.003, and the expression formula of solid line is y=0.003*x, and namely solid line slope is 0.003.As shown in Figure 2 and Figure 6, along with the increase of geo_fac, the σ value of MOSFET linear threshold voltage variable quantity increases gradually, the difference of slope between main detection actual measured results curve and simulation result curve, slope differences now between two curves is the smaller the better, as seen from the figure, experiment curv slope and simulation curve slope to be accurate to after radix point the 3rd still consistent, owing to considering the device electrology characteristic difference because technological fluctuation causes exactly, therefore, it is possible to carry out more accurate analog simulation to the MOSFET electrology characteristic of different size type.
Fig. 3 is the σ value of NMOSFET saturation threshold voltage variety and the graph of a relation of geometric parameter factor geo_fac.Fig. 7 is the σ value of PMOSFET saturation threshold voltage variety and the graph of a relation of geometric parameter factor geo_fac.Under normal temperature, zero lining is applied partially to MOSFET, for having same channel length l and channel width w and 35 MOSFET that present position is closed on wafer carry out saturation threshold voltage measurement respectively, NMOSFET measuring condition is Vds=1.8V, Vgs=1.8V, Vbs=0V, PMOSFET measuring condition is Vds=-1.8V, Vgs=-1.8V, Vbs=0V, then the σ value calculating saturation threshold voltage variety according to the value of saturation threshold voltage and the model of PSP inside.Under different channel length l and channel width w, extract the σ value of the saturation threshold voltage variety of each size MOSFET respectively, then the σ value of saturation threshold voltage variety is carried out curve fitting, ordinate is the σ value of saturation threshold voltage variety, horizontal ordinate 1/sqrt (w*1) is the parameter geo_fac relevant to device size, and (writing for ease of expression formula in model file replaces with sqrt (w*1)
).Figure orbicular spot is test data point, and dotted line is test point trend curve, and side's point is emulated data point, and solid line is simulated point matched curve, makes two curves all cross initial point.For NMOSFET, the expression formula of dotted line is y=0.003*x, and namely dotted line slope is 0.003, and the expression formula of solid line is y=0.003*x, and namely solid line slope is 0.003.As shown in Figure 3 and Figure 7, along with the increase of geo_fac, the σ value of MOSFET saturation threshold voltage variety increases gradually, the difference of slope between main detection actual measured results curve and simulation result curve, slope differences now between two curves is the smaller the better, as seen from the figure, experiment curv slope and simulation curve slope to be accurate to after radix point the 3rd still consistent, owing to considering the device electrology characteristic difference because technological fluctuation causes exactly, therefore, it is possible to carry out more accurate analog simulation to the MOSFET electrology characteristic of different size type.
Fig. 4 is the σ value of the linear drain current relative variation of NMOSFET and the graph of a relation of geometric parameter factor geo_fac.Fig. 8 is the σ value of the linear drain current relative variation of PMOSFET and the graph of a relation of geometric parameter factor geo_fac.Under normal temperature, zero lining is applied partially to MOSFET, for having same channel length l and channel width w and 35 MOSFET that present position is closed on wafer carry out linear drain current measurement respectively, NMOSFET measuring condition is Vds=0.05V, Vgs=1.8V, Vbs=0V, PMOSFET measuring condition is Vds=-0.05V, Vgs=-1.8V, Vbs=0V, then the σ value calculating linear drain current relative variation according to the value of linear drain current and the model of PSP inside.Under different channel length l and channel width w, extract the σ value of the linear drain current relative variation of each size MOSFET respectively, then the σ value of linear drain current relative variation is carried out curve fitting, ordinate is the σ value of linear drain current relative variation, horizontal ordinate 1/sqrt (w*1) is the parameter geo_fac relevant to device size, and (writing for ease of expression formula in model file replaces with sqrt (w*1)
).Figure orbicular spot is test data point, and dotted line is test point trend curve, and side's point is emulated data point, and solid line is simulated point matched curve, makes two curves all cross initial point.For NMOSFET, the expression formula of dotted line is y=0.004*x, and namely dotted line slope is 0.004, and the expression formula of solid line is y=0.004*x, and namely solid line slope is 0.004.As shown in Figure 4 and Figure 8, along with the increase of geo_fac, the σ value of the linear drain current relative variation of MOSFET increases gradually, the difference of slope between main detection actual measured results curve and simulation result curve, slope differences now between two curves is the smaller the better, as seen from the figure, experiment curv slope and simulation curve slope to be accurate to after radix point the 3rd still consistent, owing to considering the device electrology characteristic difference because technological fluctuation causes exactly, therefore, it is possible to carry out more accurate analog simulation to the MOSFET electrology characteristic of different size type.
Fig. 5 is the σ value of NMOSFET saturated drain current relative variation and the graph of a relation of geometric parameter factor geo_fac.Fig. 9 is the σ value of PMOSFET saturated drain current relative variation and the graph of a relation of geometric parameter factor geo_fac.Under normal temperature, zero lining is applied partially to MOSFET, for having same channel length l and channel width w and 35 MOSFET that present position is closed on wafer carry out saturated drain current measurement respectively, NMOSFET measuring condition is Vds=1.8V, Vgs=1.8V, Vbs=0V, PMOSFET measuring condition is Vds=-1.8V, Vgs=-1.8V, Vbs=0V, then the σ value calculating saturated drain current relative variation according to the value of saturated drain current and the model of PSP inside.Under different channel length l and channel width w, extract the σ value of the saturated drain current relative variation of each size MOSFET respectively, then the σ value of saturated drain current relative variation is carried out curve fitting, ordinate is the σ value of saturated drain current relative variation, horizontal ordinate 1/sqrt (w*1) is the parameter geo_fac relevant to device size, and (writing for ease of expression formula in model file replaces with sqrt (w*1)
).Figure orbicular spot is test data point, and dotted line is test point trend curve, and side's point is emulated data point, and solid line is simulated point matched curve, makes two curves all cross initial point.For NMOSFET, the expression formula of dotted line is y=0.004*x, and namely dotted line slope is 0.004, and the expression formula of solid line is y=0.004*x, and namely solid line slope is 0.004.As shown in figs. 5 and 9, along with the increase of geo_fac, the σ value of MOSFET saturated drain current relative variation increases gradually, the difference of slope between main detection actual measured results curve and simulation result curve, slope differences now between two curves is the smaller the better, as seen from the figure, experiment curv slope and simulation curve slope to be accurate to after radix point the 3rd still consistent, owing to considering the device electrology characteristic difference because technological fluctuation causes exactly, therefore, it is possible to carry out more accurate analog simulation to the MOSFET electrology characteristic of different size type.
Be only preferred embodiment of the present invention in sum, be not used for limiting practical range of the present invention.Namely all equivalences done according to the content of the present patent application the scope of the claims change and modify, and portion should belong to technology category of the present invention.
Claims (8)
- The modeling method of 1.MOS transistor PSP mismatch model, it is characterized in that, be included on standard P SP model part and increase device performance mismatch submodule, described device performance mismatch submodule comprises the fitting parameter relevant to device performance mismatch and parametric equation, the described fitting parameter flat-band voltage vfbo that to be device performance mismatch have nothing to do to PSP model basic parameter gate oxide thickness toxo and size and blocked the influence coefficient of effective channel width variable quantity wot influence degree that the transverse dispersion of adulterating causes by raceway groove; Wherein, described device performance mismatch submodule passes through described influence coefficient to transistor linearity threshold voltage V tlin, saturation threshold voltage V tsat, linear drain current I dlinwith saturated drain current I dsathe impact of the variation characteristic applying of t, revises the expression formula of toxo, vfbo and wot described in PSP model.
- 2. the modeling method of PSP mismatch model of MOS transistor as claimed in claim 1, it is characterized in that, described influence coefficient comprises: device performance mismatch is to fitting parameter dtoxo_mis, dvfbo_mis and dwot_mis of described toxo, vfbo and wot influence degree.
- 3. the modeling method of PSP mismatch model of MOS transistor as claimed in claim 1, it is characterized in that, described in described correction PSP model, the expression formula of toxo, vfbo and wot also comprises intermediate variable dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v of being obtained by the computing of described influence coefficient, participates in the expression of toxo, vfbo and wot; Wherein said dtoxo_mis_v is the variable quantity affecting gate oxide thickness by device performance mismatch; Described dvfbo_mis_v is the variable quantity affecting the flat-band voltage had nothing to do with size by device performance mismatch; Described dwot_mis_v is the variable quantity affecting the effective channel width caused by the transverse dispersion of raceway groove blocking-up doping by device performance mismatch.
- 4. the modeling method of PSP mismatch model of MOS transistor as claimed in claim 3, is characterized in that, is describedly obtained in the computing of described intermediate variable by influence coefficient, and comprise the parameter geo fac relevant to device size, the computing obtaining geo fac is as follows:Wherein l is the channel length of MOSFET element, and w is the channel width of MOSFET element.
- 5. the modeling method of PSP mismatch model of MOS transistor as claimed in claim 3, it is characterized in that, described intermediate variable meets Gaussian distribution, the distribution and expression formula of fluctuation is random=agauss (0.0,1.0,1), wherein agauss (0.0,1.0,1) represent that expectation is 0, variance is the Gaussian distribution of 1.
- 6. the modeling method of PSP mismatch model of MOS transistor as claimed in claim 3, it is characterized in that, described intermediate variable dtoxo_mis_v, dvfbo_mis_v, dwot_mis_v are determined by following formula:dtoxo_mis_v=dtoxo_mis·random1·geo_facdvfbo_mis_v=dvfbo_mis·random2·geo_facdwot_mis_v=dwot_mis·random3·geo_facWhereinrandom1=agauss(0.0,1.0,1)random2=agauss(0.0,1.0,1)random3=agauss(0.0,1.0,1)。
- 7. the modeling method of PSP mismatch model of MOS transistor as claimed in claim 3, it is characterized in that, toxo described in described correction PSP model, the expression formula of vfbo and wot also comprises by intermediate variable dtoxo_mis_v, dvfbo_mis_v, dwot_mis_v is to described gate oxide thickness toxo, with the flat-band voltage vfbo that size is irrelevant, effective channel width variable quantity wot that the transverse dispersion blocking doping by raceway groove causes makes correction, described intermediate variable dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v and toxo, the relation of vfbo and wot, i.e. toxo, the parametric equation that vfbo and wot changes by device performance mismatch affects is respectively:toxo=toxo original+dtoxo_mis_vvfbo=vfbo original+dvfbo_mis_vwot=wot original+dwot_mis_vWherein toxo originalbe initial gate oxide thickness value, namely DC Model extracts the gate oxide thickness value obtained; Vfbo originalbe the initial flat-band voltage value irrelevant with size, namely DC Model extracts the flat-band voltage value irrelevant with size obtained; wot originalbe the initial change amount that the transverse dispersion blocking doping by raceway groove causes effective channel width to change, namely DC Model extracts the effective channel width variable quantity caused by the transverse dispersion of raceway groove blocking-up doping obtained.
- 8. the modeling method of PSP mismatch model of MOS transistor according to claim 1, is characterized in that, described MOSFET is the MOSFET comprising 22nm-130nm standard technology.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210506129.0A CN102968538B (en) | 2012-11-30 | 2012-11-30 | The modeling method of PSP mismatch model of MOS transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210506129.0A CN102968538B (en) | 2012-11-30 | 2012-11-30 | The modeling method of PSP mismatch model of MOS transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102968538A CN102968538A (en) | 2013-03-13 |
CN102968538B true CN102968538B (en) | 2015-08-19 |
Family
ID=47798675
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210506129.0A Active CN102968538B (en) | 2012-11-30 | 2012-11-30 | The modeling method of PSP mismatch model of MOS transistor |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102968538B (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104090999B (en) * | 2014-06-24 | 2018-05-29 | 上海集成电路研发中心有限公司 | The production method of MOS angle models in a kind of SRAM |
CN104657558B (en) * | 2015-02-28 | 2018-01-26 | 上海华虹宏力半导体制造有限公司 | The method for extracting LOD effect models |
CN105138803A (en) * | 2015-09-27 | 2015-12-09 | 上海华力微电子有限公司 | Universal mismatch model with consideration of temperature effect and method for extracting mismatch model |
CN105302943B (en) * | 2015-09-27 | 2018-08-24 | 上海华力微电子有限公司 | A kind of dominant relevant mismatch model of bias voltage and its extracting method |
CN108614904B (en) * | 2016-12-11 | 2021-10-12 | 复旦大学 | Method for rapidly analyzing yield of integrated circuit parameters based on simulation data correlation |
CN108153960A (en) * | 2017-12-21 | 2018-06-12 | 上海华力微电子有限公司 | A kind of modeling method of the mismatch model with temperature effect model |
CN111381139B (en) * | 2018-12-29 | 2022-04-26 | 长鑫存储技术有限公司 | Semiconductor device testing method and semiconductor device testing system |
CN111368490B (en) * | 2020-02-24 | 2023-07-18 | 杰华特微电子股份有限公司 | Circuit system of lateral double-diffusion transistor and modeling method thereof |
CN112052637A (en) * | 2020-08-31 | 2020-12-08 | 中国科学院微电子研究所 | BSIMMG-based FDSOI MOSFET model generation method and device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101281877A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Method for measuring MOS transistor dismatching features, territory pattern and forming method thereof |
CN101739472A (en) * | 2008-11-18 | 2010-06-16 | 上海华虹Nec电子有限公司 | Method for constructing and simulating MOSFET mismatch model |
CN102385646A (en) * | 2010-09-03 | 2012-03-21 | 上海华虹Nec电子有限公司 | Correction method for device mismatch of MOS (Metal Oxide Semiconductor) transistors |
-
2012
- 2012-11-30 CN CN201210506129.0A patent/CN102968538B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101281877A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Method for measuring MOS transistor dismatching features, territory pattern and forming method thereof |
CN101739472A (en) * | 2008-11-18 | 2010-06-16 | 上海华虹Nec电子有限公司 | Method for constructing and simulating MOSFET mismatch model |
CN102385646A (en) * | 2010-09-03 | 2012-03-21 | 上海华虹Nec电子有限公司 | Correction method for device mismatch of MOS (Metal Oxide Semiconductor) transistors |
Non-Patent Citations (1)
Title |
---|
基于表面势的MOSFET模型;程彬杰等;《固体电子学研究与进展》;20000229;第20卷(第1期);全文 * |
Also Published As
Publication number | Publication date |
---|---|
CN102968538A (en) | 2013-03-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102968538B (en) | The modeling method of PSP mismatch model of MOS transistor | |
CN105468828B (en) | A kind of modeling method of III-V race HEMT surface potentials basis set about pattern type | |
CN102645569B (en) | Measuring circuit and measuring method of fluctuation of threshold voltage of MOS (Metal Oxide Semiconductor) device | |
Sun et al. | On the accuracy of channel length characterization of LDD MOSFET's | |
CN102142057B (en) | BSIM4 stress model applied to MOSFET electrical simulation | |
US20130054210A1 (en) | Method for Determining BSIMSOI4 DC Model Parameters | |
CN102176215B (en) | Modeling method for SPICE model series of SOI (Silicon on Insulator) field effect transistor | |
CN105138803A (en) | Universal mismatch model with consideration of temperature effect and method for extracting mismatch model | |
CN101685478A (en) | Circuit simulation based on gate spacing from adjacent mos transistors | |
CN105022878A (en) | Radio frequency SOI-MOS varactor substrate model and parameter extracting method thereof | |
Chauhan et al. | Compact modeling of lateral nonuniform doping in high-voltage MOSFETs | |
CN105302943A (en) | Bias voltage dominant relevance mismatch model and extracting method | |
CN105226054A (en) | A kind of general mismatch model and extracting method thereof | |
CN101571884A (en) | Modeling method for MOSFET BSIM3 hot carrier injection reliability model | |
CN107622959B (en) | Calibration method for MOS capacitor CV characteristic curve in TCAD simulation | |
CN112733477B (en) | GaN HEMT modeling method based on error function precision compensation | |
US8271254B2 (en) | Simulation model of BT instability of transistor | |
CN105975646A (en) | Systems, methods and computer program products for analyzing performance of semiconductor devices | |
CN102915394B (en) | PSP stress model applied to MOSFET (Metal Oxide Semiconductor Field Effect Transistor) electric emulation | |
CN109977564B (en) | Method and system for improving applicability of SOI process diode model | |
CN102592006A (en) | Novel MOSFET (metal-oxide-semiconductor field effect transistor) NQS (network queuing system) model and circuit simulation method | |
CN108875200B (en) | General WPE optimization model and extraction method thereof | |
CN113361229B (en) | Analog calculation method of MOSFET (Metal-oxide-semiconductor field Effect transistor) intrinsic voltage | |
Ismail et al. | Modeling of temperature variations in MOSFET mismatch for circuit simulations | |
Hillebrand et al. | V th is dead-long live the threshold voltage |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |