CN102968538B - The modeling method of PSP mismatch model of MOS transistor - Google Patents

Abstract

The invention discloses a modeling method of a MOS transistor PSP mismatch model (mismatch model), which includes adding a device performance mismatch sub-module to the standard PSP model part, and the device performance mismatch sub-module includes a simulated model related to the device performance mismatch. The fitting parameters and parametric equations, the fitting parameters are the influence coefficients of the device performance mismatch on the basic parameters toxo, vfbo and wot of the PSP model. The device performance mismatch sub-module determines the device performance mismatch through the impact of the influence coefficient on the transistor linear threshold voltage V _tlin , saturation threshold voltage V _tsat , linear drain current I _dlin and saturation drain current I _dsat The gate oxide thickness toxo, the size-independent flat band voltage vfbo and the effective channel width variation wot caused by the lateral diffusion of channel stop doping are paired to redefine the gate oxide thickness toxo, the and The size-independent flat-band voltage vfbo and the effective channel width variation wot caused by the lateral diffusion of channel-stop doping.

Description

Modeling Method of PSP Mismatch Model of MOS Transistor

technical field

The invention belongs to the field of integrated circuits, in particular to a modeling method for a MOS transistor PSP mismatch model.

Background technique

There are different degrees of process fluctuations in the manufacturing process of integrated circuits, and the device performance in the sequence of each process step may affect the performance and cost rate of the chip. With the continuous development of microelectronics technology, the feature size and gate oxide thickness of the device in the CMOS integrated circuit process have reached the order of deep nanometers. Although the performance of the device has been improved, the circuit has become more sensitive to process fluctuations. The process of device characteristics The impact of fluctuations on the performance of integrated circuits is even more severe. Therefore, it is very important to consider and estimate process fluctuations in integrated circuit design.

As an important bridge between integrated circuit design and manufacturing, the MOSFET device model can effectively predict the impact of various physical effects in the chip and process fluctuations in the integrated circuit manufacturing process. Considering the mismatch model in the MOSFET device model can effectively predict the impact of process fluctuations in the fabrication of deep nanoscale devices. Therefore, a SPICE model with accurate mismatch model parameters can more accurately predict the electrical characteristics of devices considering process fluctuations for integrated circuit design engineers.

The problem of process fluctuation has attracted the attention of experts and scholars in the industry in the late 1990s. Nassif.S.R et al. researched that we should not only consider the process fluctuations between chips. Due to the proportional reduction of the device size, the process sensitivity of the chip increases. Consider and estimate the process fluctuations inside the chip (that is, mismatching) in the chip design. properties, which refer to the differences in electrical characteristics between devices that are adjacent in the same wafer and have the same size and structure), can effectively improve the performance and yield of chips. The traditional method is to collect a large amount of IV characteristic data for each device, and then use optimization methods to extract device model parameters. This method is precise but very time-consuming. Purviance et al established a statistical model of MESFET with principal component analysis. The main idea is to use a linear combination of a group of independent random variables to approximate the measured values of S parameters of MESFET. For deep submicron MOSFET devices, the short-channel effect affects the mismatch (mismatch) properties, so Bastos et al. added the short-channel effect part to their mismatch research.

In recent years, some domestic scholars have also conducted research on the impact of process fluctuations. For example, Xidian University has achieved certain results in interconnection considering process fluctuations. But there are few researches on systematically establishing integrated circuit MOSFET process fluctuation model.

The PSP model based on the surface potential obtains the equations of charge and current by accurately solving the channel surface potential distribution. It describes the device characteristics more accurately, and is currently widely used in the industry when modeling nanoscale standard process MOSFETs. model. PSP SPICE models provide a large number of comprehensive model modules. Based on the original standard PSP model, the present invention establishes a perfect mismatch model related to device performance mismatch by adding device performance mismatch parameters and their parameter equations to the PSP SPICE model platform in the form of sub-circuits , can more accurately analyze the process fluctuation and simulate the electrical characteristics of the device for the designed circuit, so as to improve the performance and yield of the device.

Contents of the invention

The object of the present invention is to provide a modeling method of a MOS transistor PSP mismatch model, which adds a device performance mismatch sub-module to the standard PSP model. The device performance mismatch sub-module includes fitting parameters and parameter equations related to device performance mismatch. The influence coefficient of the influence degree of the effective channel width variation wot caused by the lateral diffusion of blocking doping. The device performance mismatch sub-module corrects the PSP model through the influence of the influence coefficient on the variation characteristics of transistor linear threshold voltage V _tlin , saturation threshold voltage V _tsat , linear drain current I _dlin and saturated drain current I _dsat The expressions of said toxo, vfbo and wot, that is to determine the device performance mismatch pair gate oxide thickness toxo, the size-independent flat band voltage vfbo and the effective channel width variation wot caused by the lateral diffusion of channel stop doping to redefine the gate oxide thickness toxo, the dimension-independent flat-band voltage vfbo, and the effective channel width variation wot caused by the lateral diffusion of channel stop doping.

The influence coefficient includes: parameters dtoxo_mis, dvfbo_mis and dwot_mis of the degree of influence of device performance mismatch on the toxo, vfbo and wot.

The method for correcting the expressions of toxo, vfbo and wot in the PSP model also includes the intermediate variables dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v obtained by the operation of the influence coefficient, which participate in the expression of toxo, vfbo and wot. Wherein, the dtoxo_mis_v is the variation of the gate oxide thickness affected by the device performance mismatch; the dvfbo_mis_v is the variation of the flat band voltage which is affected by the device performance mismatch and has nothing to do with the size; the dwot_mis_v is affected by the device performance mismatch by The amount of change in effective channel width due to lateral diffusion of channel-stop doping.

Wherein, the operation of obtaining the intermediate variable from the influence coefficient includes the parameter geo_fac related to the device size, and the operation of obtaining geo_fac is as follows:

$\mathrm{<span\; class="notranslate">\; geo</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; fac</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\sqrt{\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; w</span>}}}$

Where l is the channel length of the MOSFET device, and w is the channel width of the MOSFET device.

Wherein, the cause of the mismatch (mismatch) model is process fluctuations. In electrical simulation, these fluctuations are considered to be caused by random walks of many independent variables, so the intermediate variables conform to Gaussian distribution, and the distribution expression of fluctuations is random = agauss(0.0, 1.0, 1), where agauss(0.0, 1.0, 1) represents a Gaussian distribution with an expectation of 0 and a variance of 1.

Therefore, the intermediate variables dtoxo_mis_v, dvfbo_mis_v, and dwot_mis_v are determined by the following formulas:

dtoxo_mis_v=dtoxo_mis randoml geo_fac

dvfbo_mis_v=dvfbo_mis random2 geo_fac

dwot_mis_v=dwot_mis random3 geo_fac

In the formula

random1=agauss(0.0, 1.0, 1)

random2=agauss(0.0, 1.0, 1)

random3=agauss(0.0, 1.0, 1).

The present invention uses the intermediate variables dtoxo_mis_v, dvfbo_mis_v, and dwot_mis_v to correct the gate oxide thickness toxo, the size-independent flat-band voltage vfbo, and the effective channel width variation wot caused by lateral diffusion of channel stop doping. The relationship between the intermediate variables dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v and toxo, vfbo and wot, that is, the parameter equations of toxo, vfbo and wot being affected by the mismatch of device performance are respectively:

toxo＝toxo _original +dtoxo_mis_v

vfbo＝vfbo _original +dvfbo_mis_v

wot＝wot _original +dwot_mis_v

where toxo _original is the initial gate oxide thickness value, that is, the gate oxide thickness value extracted by the DC model; vfbo _original is the size-independent initial flat-band voltage value, that is, the size-independent flat-band voltage value extracted by the DC model; wot _original is the initial variation of the effective channel width caused by the lateral diffusion of the channel-stopping dopant, that is, the variation of the effective channel width caused by the lateral diffusion of the channel-stopping dopant extracted by the DC model.

The applicable MOSFET of the present invention is a MOSFET including 22nm-130nm standard technology.

According to the model established by the modeling method of the MOS transistor PSP mismatch (mismatch) model of the present invention, its physical meaning is clear, the accuracy is high, and the difference in electrical characteristics of the device due to process fluctuations is accurately considered, and MOSFETs of different sizes and types can be accurately considered. The electrical characteristics are simulated more accurately.

Description of drawings

Fig. 1 is the schematic structural block diagram of the model that the modeling method of MOS transistor PSP mismatch (mismatch) model of the present invention establishes;

Fig. 2 is the relationship diagram of the σ value σ(ΔV _tlin ) of the linear threshold voltage variation of the NMOSFET and the geometric parameter factor geo_fac;

Fig. 3 is a relationship diagram between the σ value σ(ΔV _tsat ) of the NMOSFET saturation threshold voltage variation and the geometric parameter factor geo_fac;

Fig. 4 is a relationship diagram between the σ value σ(ΔI _dlin /I _dlin ) and the geometric parameter factor geo_fac of the relative variation of the linear drain current of the NMOSFET;

Fig. 5 is a relationship diagram between the σ value σ(ΔI _dsat /I _dsat ) and the geometric parameter factor geo_fac of the relative variation of the saturated drain current of the NMOSFET;

Fig. 6 is a relationship diagram between the σ value σ(-ΔV _tlin ) and the geometric parameter factor geo_fac of the linear threshold voltage variation of the PMOSFET;

Fig. 7 is a relationship diagram between the σ value σ(-ΔV _tsat ) of the PMOSFET saturation threshold voltage variation and the geometric parameter factor geo_fac;

Fig. 8 is a relationship diagram between the σ value σ(ΔI _dlin /I _dlin ) and the geometric parameter factor geo_fac of the relative variation of the linear drain current of the PMOSFET;

FIG. 9 is a graph showing the relationship between the σ value σ(ΔI _dsat /I _dsat ) of the relative variation of the saturated drain current of the PMOSFET and the geometric parameter factor geo_fac.

Detailed ways

The present invention will be further elaborated below in conjunction with the accompanying drawings and examples. The following examples do not limit the present invention. Without departing from the spirit and scope of the inventive concept, changes and advantages that can be imagined by those skilled in the art are all included in the present invention.

The invention provides a modeling method of a PSP mismatch model of a MOS transistor, specifically a modeling method of a PSP mismatch model related to a mismatch between a 22nm-130nm standard process MOSFET and device performance. The model established by this method has clear physical meaning and high accuracy, and accurately considers the differences in device electrical characteristics caused by process fluctuations, which is helpful for more accurate simulation of the electrical characteristics of MOSFETs of different sizes and types.

The method of the invention adds a device performance mismatch sub-module to the part of the standard PSP model. The device performance mismatch sub-module includes fitting parameters and parameter equations related to device performance mismatch. The influence coefficient of the influence degree of the effective channel width variation wot caused by the lateral diffusion of blocking doping. The device performance mismatch sub-module modifies the effects described in the PSP model by influencing the influence coefficients exert on the variation characteristics of transistor linear threshold voltage V _tlin , saturation threshold voltage V _tsat , linear drain current I _dlin , and saturated drain current I _dsat The expression of toxo, vfbo and wot, so that the PSP mismatch model obtained by the modeling method of the present invention can more accurately simulate the actual performance of nanoscale MOSFET devices. That is to say, the device performance mismatch sub-module is determined by the impact of the influence coefficient on the variation characteristics of the transistor linear threshold voltage V _tlin , saturation threshold voltage V _tsat , linear drain current I _dlin and saturated drain current I _dsat The effect of device performance mismatch on the gate oxide thickness toxo, the size-independent flat band voltage vfbo and the effective channel width variation wot caused by the lateral diffusion of channel stop doping, to redefine the gate oxide thickness toxo, The size-independent flat-band voltage vfbo and the effective channel width variation wot caused by lateral diffusion of channel-stop doping.

FIG. 1 is a schematic structural block diagram of a model established by a modeling method for a MOS transistor PSP mismatch model of the present invention. As shown in Figure 1, the present invention is the model that the modeling method of MOS transistor PSP mismatch (mismatch) model establishes, by the calculation formula (being Fig. 1 The parameter equations in ) and related fitting parameters are introduced into the PSP SPICE model platform in the form of sub-circuits. Among them, the three PSP SPICE model parameters are: gate oxide thickness toxo, size-independent flat-band voltage vfbo, and effective channel width variation wot caused by lateral diffusion of channel-stop doping. The main purpose of the preferred embodiment of the present invention is to utilize three PSPSPICE parameter calculation formulas and fitting parameters to calculate the specific values of toxo, vfbo and wot of different channel lengths and width MOSFETs, and then use these PSP SPICE parameters in different channel lengths The electrical characteristics of the MOSFET are simulated by combining the values under the width and width with the PSP SPICE model platform.

In the present invention, the influence coefficient includes: parameters dtoxo_mis, dvfbo_mis and dwot_mis of the degree of influence of device performance mismatch on the toxo, vfbo and wot. These three parameters are fitting parameters added during the modeling process, and their initial values are all set to zero. By adjusting the values of these three fitting parameters, the actual test conditions of the device are fitted. When the fitting meets the requirements When the accuracy is high, the values of these three fitting parameters can be obtained.

The method of modifying the expressions of toxo, vfbo and wot in the PSP model after considering the mismatch of device performance also includes the intermediate variables dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v obtained by the operation of the influence coefficient, which participate in toxo, vfbo and wot expression. Wherein, the dtoxo_mis_v is the variation of the gate oxide thickness affected by the device performance mismatch; the dvfbo_mis_v is the variation of the flat band voltage which is affected by the device performance mismatch and has nothing to do with the size; the dwot_mis_v is affected by the device performance mismatch by The amount of change in effective channel width due to lateral diffusion of channel-stop doping.

The method of modifying the expressions of toxo, vfbo and wot in the PSP model after considering the device performance mismatch also includes adjusting the gate oxide thickness toxo, the size-independent flat band voltage vfbo, A correction is made for the effective channel width variation wot caused by the lateral diffusion of the channel-stop doping. The relationship between the intermediate variables dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v and toxo, vfbo and wot, that is, the parameter equations of toxo, vfbo and wot being affected by the mismatch of device performance are respectively:

toxo＝toxo _original +dtoxo_mis_v

vfbo＝vfbo _original +dvfbo_mis_v

wot＝wot _original +dwot_mis_v

where toxo _original is the initial gate oxide thickness value, that is, the gate oxide thickness value extracted by the DC model; vfbo _original is the size-independent initial flat-band voltage value, that is, the size-independent flat-band voltage value extracted by the DC model; wot _original is the initial variation of the effective channel width caused by the lateral diffusion of the channel-stopping dopant, that is, the variation of the effective channel width caused by the lateral diffusion of the channel-stopping dopant extracted by the DC model.

Wherein, the operation of obtaining the intermediate variable from the influence coefficient includes the parameter geo_fac related to the device size, and the operation of obtaining geo_fac is as follows:

$\mathrm{<span\; class="notranslate">\; geo</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; fac</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\sqrt{\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; w</span>}}}$

Where l is the channel length of the MOSFET device, and w is the channel width of the MOSFET device.

Wherein, the cause of the mismatch (mismatch) model is process fluctuations. In electrical simulation, these fluctuations are considered to be caused by random walks of many independent variables, so the intermediate variables conform to Gaussian distribution, and the distribution expression of fluctuations is random = agauss(0.0, 1.0, 1), where agauss(0.0, 1.0, 1) represents a Gaussian distribution with an expectation of 0 and a variance of 1.

Therefore, the intermediate variables dtoxo_mis_v, dvfbo_mis_v, and dwot_mis_v are determined by the following formulas:

dtoxo_mis_v=dtoxo_mis random1 geo_fac

dvfbo_mis_v=dvfbo_mis random2 geo_fac

dwot_mis_v=dwot_mis random3 geo_fac

In the formula

random1=agauss(0.0, 1.0, 1)

random2=agauss(0.0, 1.0, 1)

random3=agauss(0.0, 1.0, 1).

First, use the PSP SPICE model to measure MOSFETs with a channel length of 0.036-0.9 μm and a channel width of 0.108-0.9 μm in the 40nm standard process, and then extract the parameters of the PSP model to obtain the toxo, vfbo, and wot SPICE model parameters of these devices value.

Hereinafter, how to apply the PSP mismatch model obtained by the modeling method of the present invention will be further described in detail in the embodiment of a 40nm standard process MOSFET.

Fig. 2 is a graph showing the relationship between the σ value of the NMOSFET linear threshold voltage variation and the geometric parameter geo_fac. FIG. 6 is a graph showing the relationship between the σ value of the linear threshold voltage variation of the PMOSFET and the geometric parameter factor geo_fac. Apply zero lining bias to the MOSFET at room temperature, and measure the linear threshold voltage of thirty-five MOSFETs with the same channel length l and channel width w and located close to each other on the wafer. The NMOSFET measurement condition is Vds (drain Pole voltage) = 0.05V, Vgs (gate voltage) = 1.8V, Vbs (substrate bias) = 0V, PMOSFET measurement conditions are Vds = -0.05V, Vgs = -1.8V, Vbs = 0V, and then according to the linear The value of the threshold voltage and the model inside the PSP calculate the σ value of the linear threshold voltage variation. Under different channel length l and channel width w, the σ value of the linear threshold voltage change of each size MOSFET is extracted respectively, and then the curve fitting is performed on the σ value of the linear threshold voltage change, and the ordinate is linear The σ value of the threshold voltage variation, the abscissa 1/sqrt(w*1) is the parameter geo_fac related to the device size (in the model file, for the convenience of writing the expression, replace it with sqrt(w*1) ). The dots in the figure are the test data points, the dotted line is the trend curve of the test points, the square points are the simulation data points, and the solid line is the fitting curve of the simulation points, so that both curves pass through the origin. Taking NMOSFET as an example, the expression of the dotted line is y=0.003*x, that is, the slope of the dotted line is 0.003, and the expression of the solid line is y=0.003*x, that is, the slope of the solid line is 0.003. As shown in Figure 2 and Figure 6, with the increase of geo_fac, the σ value of the MOSFET linear threshold voltage variation gradually increases, mainly observing the slope difference between the actual measurement result curve and the simulation result curve, at this time the two curves The smaller the slope difference, the better. It can be seen from the figure that the slope of the measured curve and the simulated curve are accurate to the third decimal place and are still consistent. Due to the accurate consideration of the differences in the electrical characteristics of the device due to process fluctuations, it is possible to perform different sizes. Conduct more accurate simulations of the MOSFET electrical characteristics.

Fig. 3 is a graph showing the relationship between the σ value of the NMOSFET saturation threshold voltage variation and the geometric parameter factor geo_fac. FIG. 7 is a graph showing the relationship between the σ value of the PMOSFET saturation threshold voltage variation and the geometric parameter factor geo_fac. Apply zero offset to the MOSFET at room temperature, and measure the saturation threshold voltage of thirty-five MOSFETs that have the same channel length l and channel width w and are located close to each other on the wafer. The NMOSFET measurement condition is Vds=1.8 V, Vgs=1.8V, Vbs=0V, PMOSFET measurement conditions are Vds=-1.8V, Vgs=-1.8V, Vbs=0V, and then calculate the saturation threshold voltage variation according to the value of the saturation threshold voltage and the internal model of the PSP The σ value. Under different channel length l and channel width w, the σ value of the saturation threshold voltage change of each size MOSFET is extracted, and then the curve fitting is performed on the σ value of the saturation threshold voltage change, and the ordinate is saturation The σ value of the threshold voltage variation, the abscissa 1/sqrt(w*1) is the parameter geo_fac related to the device size (in the model file, for the convenience of writing the expression, replace it with sqrt(w*1) ). The dots in the figure are the test data points, the dotted line is the trend curve of the test points, the square points are the simulation data points, and the solid line is the fitting curve of the simulation points, so that both curves pass through the origin. Taking NMOSFET as an example, the expression of the dotted line is y=0.003*x, that is, the slope of the dotted line is 0.003, and the expression of the solid line is y=0.003*x, that is, the slope of the solid line is 0.003. As shown in Figure 3 and Figure 7, with the increase of geo_fac, the σ value of the MOSFET saturation threshold voltage variation gradually increases. The main observation is the difference in slope between the actual measurement result curve and the simulation result curve. At this time, the two curves The smaller the slope difference, the better. It can be seen from the figure that the slope of the measured curve and the simulated curve are accurate to the third decimal place and are still consistent. Due to the accurate consideration of the differences in the electrical characteristics of the device due to process fluctuations, it is possible to perform different sizes. Conduct more accurate simulations of the MOSFET electrical characteristics.

Fig. 4 is a graph showing the relationship between the σ value of the relative variation of the linear drain current of the NMOSFET and the geometric parameter factor geo_fac. FIG. 8 is a graph showing the relationship between the σ value of the relative variation of the linear drain current of the PMOSFET and the geometric parameter factor geo_fac. Apply zero lining bias to the MOSFET at room temperature, and perform linear drain current measurement on thirty-five MOSFETs with the same channel length l and channel width w and located close to each other on the wafer. The NMOSFET measurement condition is Vds= 0.05V, Vgs=1.8V, Vbs=0V, PMOSFET measurement conditions are Vds=-0.05V, Vgs=-1.8V, Vbs=0V, and then calculate the linear drain according to the value of the linear drain current and the internal model of the PSP The σ value of the relative change in current. Under different channel length l and channel width w, the σ value of the relative change in the linear drain current of each size MOSFET is extracted, and then the curve fitting is performed on the σ value of the relative change in the linear drain current, The ordinate is the σ value of the relative change of the linear drain current, and the abscissa 1/sqrt(w*1) is the parameter geo_fac related to the device size (in the model file, for the convenience of writing the expression, use sqrt(w* 1) instead of ). The dots in the figure are the test data points, the dotted line is the trend curve of the test points, the square points are the simulation data points, and the solid line is the fitting curve of the simulation points, so that both curves pass through the origin. Taking NMOSFET as an example, the expression of the dotted line is y=0.004*x, that is, the slope of the dotted line is 0.004, and the expression of the solid line is y=0.004*x, that is, the slope of the solid line is 0.004. As shown in Figure 4 and Figure 8, with the increase of geo_fac, the σ value of the relative change of MOSFET linear drain current increases gradually, mainly observing the slope difference between the actual measurement result curve and the simulation result curve, at this time the two The smaller the slope difference between the two curves, the better. It can be seen from the figure that the slope of the measured curve and the slope of the simulated curve are accurate to the third decimal place and are still consistent. Due to the accurate consideration of the device electrical characteristics caused by process fluctuations, it can be used for different Conduct more accurate simulations of the electrical characteristics of MOSFETs of different size types.

FIG. 5 is a graph showing the relationship between the σ value of the relative variation of the saturated drain current of the NMOSFET and the geometric parameter factor geo_fac. FIG. 9 is a graph showing the relationship between the σ value of the relative variation of the saturated drain current of the PMOSFET and the geometric parameter factor geo_fac. Under normal temperature, zero lining bias is applied to the MOSFET, and the saturation drain current is measured for thirty-five MOSFETs with the same channel length l and channel width w and located close to each other on the wafer. The NMOSFET measurement condition is Vds= 1.8V, Vgs=1.8V, Vbs=0V, PMOSFET measurement conditions are Vds=-1.8V, Vgs=-1.8V, Vbs=0V, and then calculate the saturated drain according to the value of the saturated drain current and the internal model of the PSP The σ value of the relative change in current. Under different channel length l and channel width w, the σ value of the relative change in the saturated drain current of each size MOSFET is extracted, and then the curve fitting is performed on the σ value of the relative change in the saturated drain current, The ordinate is the σ value of the relative change of the saturated drain current, and the abscissa 1/sqrt(w*1) is the parameter geo_fac related to the device size (in the model file, for the convenience of writing the expression, use sqrt(w* 1) instead of ). The dots in the figure are the test data points, the dotted line is the trend curve of the test points, the square points are the simulation data points, and the solid line is the fitting curve of the simulation points, so that both curves pass through the origin. Taking NMOSFET as an example, the expression of the dotted line is y=0.004*x, that is, the slope of the dotted line is 0.004, and the expression of the solid line is y=0.004*x, that is, the slope of the solid line is 0.004. As shown in Figure 5 and Figure 9, with the increase of geo_fac, the σ value of the relative change of MOSFET saturated drain current increases gradually, mainly to observe the slope difference between the actual measurement result curve and the simulation result curve, at this time the two The smaller the slope difference between the two curves, the better. It can be seen from the figure that the slope of the measured curve and the simulated curve are accurate to the third decimal place and are still consistent. Due to the accurate consideration of the device electrical characteristics caused by process fluctuations, it can be used for different Conduct more accurate simulations of the electrical characteristics of MOSFETs of different size types.

In summary, the above are only preferred embodiments of the present invention, and are not intended to limit the implementation scope of the present invention. That is, all equivalent changes and modifications made according to the content of the patent scope of the present invention should belong to the technical category of the present invention.

Claims (8)

1. The modeling method of MOS transistor PSP mismatch model is characterized in that, comprises on standard PSP model part and increases device performance mismatch sub-module, and described device performance mismatch sub-module includes fitting parameters relevant to device performance mismatch and Parametric equation, the fitting parameters are device performance mismatch pair PSP model basic parameters gate oxide thickness toxo, size-independent flat band voltage vfbo and effective channel width variation wot caused by lateral diffusion of channel stop doping Influence coefficient of influence degree; Wherein, the change of the linear threshold voltage V _tlin , saturation threshold voltage V _tsat , linear drain current I _dlin and saturation drain current I _dsa t of the transistor by the mismatch sub-module of the device performance through the influence coefficient The influence exerted by the properties to modify the expressions of toxo, vfbo and wot described in the PSP model. 2. the modeling method of MOS transistor PSP mismatch model as claimed in claim 1, is characterized in that, described influence coefficient comprises: the fitting parameter dtoxo_mis, dvfbo_mis of device performance mismatch to described toxo, vfbo and wot influence degree and dwot_mis. 3. the modeling method of MOS transistor PSP mismatch model as claimed in claim 1, is characterized in that, the expression of described toxo, vfbo and wot in the described correction PSP model also comprises by the operation of described influence coefficient The obtained intermediate variables dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v are involved in the expression of toxo, vfbo and wot; wherein the dtoxo_mis_v is the variation of gate oxide thickness affected by device performance mismatch; the dvfbo_mis_v is affected by device performance mismatch and size The amount of variation of the irrelevant flat-band voltage; the dwot_mis_v is the amount of variation of the effective channel width caused by the lateral diffusion of the channel stop doping, which is affected by the device performance mismatch. 4. the modeling method of MOS transistor PSP mismatch model as claimed in claim 3, it is characterized in that, in the described operation that obtains described intermediate variable by influence coefficient, comprise the parameter geofac relevant with device size, obtain geo The operation of fac is as follows: Where l is the channel length of the MOSFET device and w is the channel width of the MOSFET device. 5. the modeling method of MOS transistor PSP mismatch model as claimed in claim 3 is characterized in that, described intermediate variable meets Gaussian distribution, and the distribution expression of fluctuation is random=agauss(0.0,1.0,1), wherein agauss(0.0,1.0,1) represents a Gaussian distribution with an expectation of 0 and a variance of 1. 6. the modeling method of MOS transistor PSP mismatch model as claimed in claim 3, is characterized in that, described intermediate variable dtoxo_mis_v, dvfbo_mis_v, dwot_mis_v are determined by following formula: dtoxo_mis_v=dtoxo_mis random1 geo_fac dvfbo_mis_v=dvfbo_mis random2 geo_fac dwot_mis_v=dwot_mis random3 geo_fac in random1=agauss(0.0,1.0,1) random2=agauss(0.0,1.0,1) random3=agauss(0.0,1.0,1). 7. The modeling method of MOS transistor PSP mismatch model as claimed in claim 3, is characterized in that, the expression of described toxo, vfbo and wot in the described correction PSP model also comprises by intermediate variable dtoxo_mis_v, dvfbo_mis_v, dwot_mis_v The gate oxide thickness toxo, the size-independent flat-band voltage vfbo, and the effective channel width variation wot caused by the lateral diffusion of channel stop doping are corrected, and the intermediate variables dtoxo_mis_v, dvfbo_mis_v and dwot_mis_v are related to The relationship between toxo, vfbo, and wot, that is, the parameter equations of toxo, vfbo, and wot that are affected by the mismatch of device performance are: toxo＝toxo _original +dtoxo_mis_v vfbo＝vfbo _original +dvfbo_mis_v wot＝wot _original +dwot_mis_v Among them, toxo _original is the initial gate oxide thickness value, that is, the gate oxide thickness value extracted by the DC model; vfbo _original is the initial flat-band voltage value independent of size, that is, the size-independent flat-band voltage value obtained by the DC model extraction; wot _original is the initial change in effective channel width caused by the lateral diffusion of channel-stop doping, that is, the change in effective channel width caused by the lateral diffusion of channel-stop doping extracted by the DC model. 8. The modeling method of MOS transistor PSP mismatch model according to claim 1, characterized in that, said MOSFET is a MOSFET including a 22nm-130nm standard process.