CN101739472A - Method for constructing and simulating MOSFET mismatch model - Google Patents

Method for constructing and simulating MOSFET mismatch model Download PDF

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CN101739472A
CN101739472A CN200810043941A CN200810043941A CN101739472A CN 101739472 A CN101739472 A CN 101739472A CN 200810043941 A CN200810043941 A CN 200810043941A CN 200810043941 A CN200810043941 A CN 200810043941A CN 101739472 A CN101739472 A CN 101739472A
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CN101739472B (en
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王正楠
周天舒
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses a method for constructing and simulating an MOSFET mismatch model, which adopts a BSIM3 model as a basis and is divided into the following steps of: (1) constructing a model parameter random error statistics expression by the principle of statistics; (2) according to the physical definition of the model parameter random error statistics expression, selecting model parameters with pertinence in the BSIM3 model respectively and adding a statistics expression correction term to the model parameters; (3) constructing a corresponding SPICE macro model; (4) defining the initial value of a correction coefficient; (5) substituting the initial value of the correction coefficient into the model and debugging and simulating the model parameters. By regulating the coefficient of a mismatch error function correction formula in the model, the invention can enable the model to accurately describe the trend of the mismatch error of an actual process. By debugging the parameters, the monitoring trend line of the actual process and the simulation trend line of the model can greatly approach to each other. The modeling method can conveniently and better simulate the mismatch statistical error of the actual process.

Description

The foundation of MOSFET mismatch model and emulation mode
Technical field
The present invention relates to a kind of semiconductor devices modeling method, be specifically related to a kind of foundation and emulation mode of MOSFET mismatch model.
Background technology
In the process of circuit design, because the existence meeting of device technology mismatch error causes certain deviation to design.Comprehensive, the factors such as spacing between the difference between the gate oxide thickness, device size, the device all can exert an influence to the technology mismatch error.
Therefore, the raising that requires along with circuit design not only is embodied on the electrology characteristic the requirement of model accuracy, and also requirement can reflect because the characteristic error that the mismatch of technology causes.But existing device model except the bound of describing the technology level, is not described the actual error situation usually specially.Therefore, be necessary on original model basis, to set up the representation function of mismatch stochastic error.
Summary of the invention
Technical matters to be solved by this invention provides a kind of method for building up of MOSFET mismatch model, and it can set up the representation function of mismatch stochastic error on original model basis.
For solving the problems of the technologies described above, the foundation of MOSFET mismatch model of the present invention and the technical solution of emulation mode are:
Adopting BSIM3 model (by a kind of industrial standard device model of Berkeley University's research and development) is the basis, is divided into following steps:
The first step utilizes Statistics to set up model parameter stochastic error statistical presentation formula;
The error expression of the technological parameter that is inversely proportional to the channel region two-dimensional areas of device is σ Δq 2 = s 1 , q 2 WL ;
With the one dimension of device channel error expression long or the wide technological parameter that is inversely proportional to be σ ΔL 2 = S 1 , P 2 W , σ ΔW 2 = S 2 , P 2 L ;
In second step, according to the physical definition of model parameter stochastic error statistical presentation formula, in the BSIM3 model, select pointed model parameter respectively, and it is added statistical presentation formula correction term;
Select these 5 parameters of vtho, tox, lint, wint and u0 in the BSIM3 model parameter, add correction formula, describe as the error of cut-in voltage, gate oxide thickness, trench gate length, raceway groove grid width and mobility;
The error correction expression formula of cut-in voltage is
The error correction expression formula of gate oxide thickness is
Figure G2008100439418D0000025
The error correction expression formula of mobility is
Figure G2008100439418D0000026
The error correction expression formula that trench gate is long is
The error correction expression formula of raceway groove grid width is
Figure G2008100439418D0000028
In the 3rd step, set up corresponding SPICE macro model;
The 4th step, the initial value of definition correction factor; The initial value of definition coefficient avth0, atox, adl, adw and au0.
The 5th step, in the initial value substitution model with described correction factor, debugging and simulation parameters.
The technique effect that the present invention can reach is:
The present invention can make model accurately describe out the trend of actual process mismatch error by the coefficient of mismatch error function amendment type in the adjustment model.By tuning parameter, actual process monitoring Trendline and model emulation Trendline can be accomplished very approaching.Therefore this modeling method can make things convenient for and simulate preferably the mismatch statistical error of actual process.
Adopt the present invention to set up the MOSFET mismatch model, need not to spend a large amount of time to debug repeatedly, can extract relevant model parameter fast and accurately, can increase work efficiency.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the trend and the cut-in voltage error that by emulation obtain comparison diagram with the trend of device size of the cut-in voltage error that obtains of actual test with device size;
Wherein solid line is represented cut-in voltage error that actual test the obtains Trendline with device size, and the dotted line representative is with the cut-in voltage error that obtains by emulation after in the coefficient of the initial value substitution mismatch error function amendment type Trendline with device size.
Fig. 2 is the trend and the saturation current error that by emulation obtain comparison diagram with the trend of device size of the saturation current error that obtains of actual test with device size;
Wherein solid line is represented saturation current error that actual test the obtains Trendline with device size, and the dotted line representative is with the saturation current error that obtains by emulation after in the coefficient of the initial value substitution mismatch error function amendment type Trendline with device size.
Fig. 3 is the trend and the cut-in voltage error that by emulation obtain comparison diagram with the trend of device size of the cut-in voltage error that obtains of actual test with device size;
Wherein solid line is represented cut-in voltage error that actual test the obtains Trendline with device size, and the cut-in voltage error that obtains by emulation after in the coefficient of the end value substitution mismatch error function amendment type that the dotted line representative obtains parameter extraction is with the Trendline of device size.
Fig. 4 is the trend and the saturation current error that by emulation obtain comparison diagram with the trend of device size of the saturation current error that obtains of actual test with device size;
Wherein solid line is represented saturation current error that actual test the obtains Trendline with device size, and the saturation current error that obtains by emulation after in the coefficient of the end value substitution mismatch error function amendment type that the dotted line representative obtains parameter extraction is with the Trendline of device size.
Fig. 5 is the foundation of MOSFET mismatch model of the present invention and the process flow diagram of emulation mode.
Wherein, the cut-in voltage of vt device, the gate oxide thickness of Tox device, L grid width, the W grid are long, u mobility, S 1, qThe area correction factor, S 1, pThe length correction coefficient, S 2, pThe width correction factor.
Embodiment
As shown in Figure 5, the foundation of MOSFET mismatch model of the present invention and emulation mode are divided into following steps:
1, utilize Statistics to set up model parameter stochastic error statistical presentation formula;
Suppose that a device parameter P is by q1, q2 ..., the functions that technological parameter determined such as qn, that is: P=f (q1, q2, q3 ..., qn).If all there is minute differences in each technological parameter between two identical devices, then the error σ expression formula of parameter P is:
σ ΔP 2 = ( ∂ f ∂ q 1 ) 2 σ Δq 1 2 + ( ∂ f ∂ q 2 ) 2 σ Δq 2 2 + . . . + ( ∂ f ∂ q n ) 2 σ Δqn 2 (1-1)
To the influential technological parameter σ of parameter P 2 Δ qi (i=1,2,3 ..., n)Can have: the cut-in voltage σ of device Δ vt 2, gate oxide thickness σ Δ tox 2, raceway groove grid width σ Δ L 2, the long σ of trench gate Δ W 2, mobility σ Δ μ 2Deng.
The data analysis that test obtains according to actual mismatch can be thought these σ 2 Δ qi (i=1,2,3 ..., n)Be that dimension size with device is inversely proportional to, therefore mismatch error and device dimension write as the function expression of inverse relation.And according to gate oxide thickness σ Δ tox 2, raceway groove grid width σ Δ L 2, the long σ of trench gate Δ W 2, mobility σ Δ μ 2The difference of physical definition, again with σ 2 Δ qi (i=1,2,3 ..., n)Be divided into 2 classes with the relation of device dimension size: a class is σ 2 Δ qiWith the error that the channel region two-dimensional areas of device is inversely proportional to, its expression formula is:
σ Δq 2 = s 1 , q 2 WL - - - ( 1 - 2 )
S wherein 1, qIt is the area correction factor.Usually the error of cut-in voltage, gate oxide thickness and mobility can be used this formal representation.
Another kind of is σ 2 Δ qiOnly grow or the wide error that is inversely proportional to the one dimension of device channel, its expression formula is:
σ ΔL 2 = S 1 , P 2 W - - - ( 1 - 3 )
σ ΔW 2 = S 2 , P 2 L - - - ( 1 - 4 )
S wherein 1, pAnd S 2, pCorrection factor for length and width.
The formula (1-2) that utilizes above hypothesis and formulate (1-3) and (1-4), can be selected the method that correlation parameter adds stochastic error function correction term and set up mismatch model in common BSIM3 model parameter.
2, according to the physical definition of model parameter stochastic error statistical presentation formula, in the BSIM3 model, select pointed model parameter respectively, and it is added statistical presentation formula correction term;
Select to add correction formula in these 5 parameters of vtho, tox, lint, wint and u0 in the BSIM3 model parameter, describe as the error of cut-in voltage, gate oxide thickness, trench gate length, raceway groove grid width and mobility.
Because vth0, tox and u0 have relation with area, thus innovation representation can for:
ΔVth 0 = avth 0 WL * agauss ( 0,1,1 ) ; - - - ( 1 - 5 )
ΔTox = atox WL * agauss ( 0,1,1 ) ; - - - ( 1 - 6 )
Δu 0 = 1 + au 0 WL * agauss ( 0,1,1 ) ; - - - ( 1 - 7 )
Lint, wint because only with the length of device with wide relevant, so innovation representation can for:
Δlint = adl W * agauss ( 0,1,1 ) ; - - - ( 1 - 8 )
Δwint = adw L * agauss ( 0,1,1 ) ; - - - ( 1 - 9 )
Avth0 wherein, atox, adl, adw is respectively the correction factor relevant with size with au0,
Agauss (0,1,1) be the built-in normal state statistical distribution functions of SPICE, in its bracket (0,1, the central value of 0 expression branch function 1) is 0, the maximum sigma amplitude of 1 expression normal state statistical distribution functions curve from central value 0 to the right and left in the 2nd of the bracket is 1, and the 1 sigma number that is expressed as statistical distribution functions in the bracket in the 3rd is one, for example (0,1,3) just represents that normal distribution is is 1 with central value 0 to the distance of 3 sigma of the right and left; Agauss is the built-in function of spice, and spice can be according to the scope therefrom peek at random of agauss definition when emulation.
Can make model effectively depict the mismatch curvilinear trend by above innovation representation.
3, set up corresponding SPICE macro model;
Set up a kind of model of mismatch error easily according to above-mentioned correction formula, its pattern is as follows:
.param
+toxn=1.55e-8 lintn=0 vth0n=0.8558
+vsatn=9.802e4?atoxn=5e-11
+avth0n=0.0158?adln=4e-10 adwn=8e-10
+au0n=1e-3
.subckt?nenh_mis?d?g?s?b?w=1.0E-6?l=1.0E-6?count=1.0
.para
+numsigma_vthmis_n=agauss(0,1,1)
+numsigma_dlmis_n=agauss(0,1,1)
+numsigma_dwmis_n=agauss(0,1,1)
+numsigma_toxmis_n=agauss(0,1,1)
+numsigma_u0mis_n=agauss(0,1,1)
+lef=’l’mismatchflag=1
+wef=’w’
+geo_area=’1/sqrt(count*lef*wef*le12)’
+geo_l=’1/sqrt(count*lef*le6)’
+geo_w=’1/sqrt(count*wef*le6)’
+vth0misn=’avth0n*geo_area*numsigma_vthmis_n*mismatchflag’
+dlmisn=’adln*geo_w*numsigma_dlmis_n*mismatchflag’
+dwmisn=’adwn*geo_l*numsigma_dwmis_n*mismatchflag’
+toxmisn=’atoxn*geo_area*numsigma_toxmis_n*mismatchflag’
+u0misn=’1+au0n*geo_area*numsigma_u0mis_n*mi?smatchflag’
ml?d?g?s?b?nenh?w=w?l=l?m=count
.model?nenh?NMOS
+level=53 version=3.1 mobmod=1
+capmod=2 noimod=2
+tox=’toxn+toxmisn’
+wint=’1.1e-7+dwmisn’
+lint=’lintn+dlmisn’
+vth0=’0.8558+vth0misn’
+u0=’0.035688*u0misn’
+…
This model format has adopted the macro model structure, vth0misn wherein, and dlmisn, dwmisn, toxmisn and u0misn correspond respectively to Δ vth0, Δ lint, Δ wint, Δ tox and Δ u0.Geo_area, geo_l and geo_w have defined the size item in the correction term denominator respectively.Numsigma_vthmis_n, numsigma_dlmis_n, numsigma_dwmis_n, numsigma_toxmis_n and numsigma_u0mis_n separately define it respectively and equal agauss (0,1,1) function is to guarantee that different parameter correction terms is to distinguish random value.Mismatchflag=1 represents that then this model considered the correction term of mismatch statistical error, if mismatchflag=0 then model is still got back to original state, the correction term of its statistical error is not all considered.
The present invention adopts the macro model form to add to the error statistics expression formula of having set up in the model respectively; Different error statistics expression formulas has adopted separately calls the built-in agauss function of spice to guarantee different parameter correction terms random value respectively, add the mismatchflag parameter in this external model again as the switching between common MOSFET model and the mismatch model, can improve the flexibility ratio of model.
4, the initial value of definition correction factor;
In order to improve the efficient of parameter extraction, define coefficient avth0, atox, adl, the initial value of adw and au0 earlier.
At first determine atox, the initial value of adl and adw.According to formula:
ΔTox = atox WL * agauss ( 0,1,1 )
Tox is the gate oxide thickness of device, and the gate oxide thickness monitoring statistics with reference to process monitoring can obtain σ in the technology Δ ToxValue is supposed agauss (0,1,1)=1, represents that then the value to 1 sigma is in the Δ Tox statistical distribution
Figure G2008100439418D0000092
Because the physical size of device is more little, the mismatch situation is serious more, so W and L can consider the situation of device minimum.If obtain the σ of process monitoring Δ Tox, then have
Figure G2008100439418D0000093
σ in the technology for example Δ ToxBe 0.7A, W=0.9um, L=0.54um can obtain the atox value and be 5e-11 (m).
Can obtain adl and these 2 initial values of adw with quadrat method.
With reference to figure 1 and Fig. 2, according to formula
Figure G2008100439418D0000094
The mismatch of vt is defined as Δ Vth in process monitoring, and it is relevant with the Trendline slope that avth0 can regard as.The initial value that can establish avth0 earlier equals slope.
Can provide the initial value of au0 earlier with quadrat method.
After in the initial value substitution model of these 5 parameters, further debugging and emulation can have been done.
The present invention carries out the method for spice artificial debugging parameter again by first definition mismatch model initial parameter value, can save because of tuning parameter repeatedly spends a large amount of time, has improved work efficiency.
5, debugging and simulation parameters.
Model is updated to carries out monte carlo computing in the SPICE emulation tool, much organized different Δ vt and Δ Idsat value, can obtain their σ with the Sigma function Δ vtAnd σ Δ Idsat
By these 5 coefficients of avth0, atox, adl, adw and au0 in the adjustment model, can be so that the σ that last model obtains Δ vtAnd σ Δ IdsatConsistent with the variation tendency of device size with variation tendency in the actual process monitoring.End product as shown in Figure 3, Figure 4, what the x axle was represented among the figure is different components
Figure G2008100439418D0000101
The y axle is respectively σ Δ vtAnd σ Δ Idsat, that solid line is represented is the σ of actual process monitoring Δ vtAnd σ Δ IdsatTrendline, dotted line representative be the σ that model emulation obtains Δ vtAnd σ Δ IdsatTrendline, can see that by tuning parameter, the simulation result of model and measured result are very approaching.Therefore this modeling method can make things convenient for and simulate preferably the mismatch statistical error of actual process.

Claims (4)

1. the foundation of a MOSFET mismatch model and emulation mode, it be basic adopting the BSIM3 model, it is characterized in that, is divided into following steps:
The first step utilizes Statistics to set up model parameter stochastic error statistical presentation formula;
The error expression of the technological parameter that is inversely proportional to the channel region two-dimensional areas of device is
σ Δq 2 = s 1 , q 2 WL ;
With the one dimension of device channel error expression long or the wide technological parameter that is inversely proportional to be
σ ΔL 2 = S 1 , P 2 W , σ ΔW 2 = S 2 , P 2 L ;
In second step, according to the physical definition of model parameter stochastic error statistical presentation formula, in the BSIM3 model, select pointed model parameter respectively, and it is added statistical presentation formula correction term;
In the 3rd step, set up corresponding SPICE macro model;
The 4th step, the initial value of definition correction factor;
The 5th step, in the initial value substitution model with described correction factor, debugging and simulation parameters.
2. the foundation of MOSFET mismatch model according to claim 1 and emulation mode, it is characterized in that: add correction formula in these 5 parameters of vtho, tox, lint, wint and u0 in described second step selection BSIM3 model parameter, error as cut-in voltage, gate oxide thickness, trench gate length, raceway groove grid width and mobility is described, and its expression formula is:
ΔVth 0 = avth 0 WL * agauss ( 0,1,1 ) ;
ΔTox = atox WL * agauss ( 0,1,1 ) ;
Δu 0 = 1 + au 0 WL * agauss ( 0,1,1 ) ;
Δlint = adl W * agauss ( 0,11 ) ;
Δwint = adw L * agauss ( 0,1,1 ) ;
Wherein the channel region two-dimensional areas of vth0, tox, u0 and device is inversely proportional to, long or wide being inversely proportional to of the one dimension of Lint, Wint and device channel, and in correction term, be added with the built-in agauss random statistical of spice function.
3. the foundation of MOSFET mismatch model according to claim 2 and emulation mode is characterized in that: described the 3rd step adopts the macro model form to add to the error statistics expression formula of having set up in the model respectively; Different error statistics expression formulas is separately called the built-in agauss function of spice; Add the mismatchflag parameter as the switching between common MOSFET model and the mismatch model.
4. the foundation of MOSFET mismatch model according to claim 3 and emulation mode is characterized in that: the initial value of described the 4th step definition coefficient avth0, atox, adl, adw and au0.
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