CN102956622B - A kind of induction structure - Google Patents
A kind of induction structure Download PDFInfo
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- CN102956622B CN102956622B CN201210496838.5A CN201210496838A CN102956622B CN 102956622 B CN102956622 B CN 102956622B CN 201210496838 A CN201210496838 A CN 201210496838A CN 102956622 B CN102956622 B CN 102956622B
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- bonding jumper
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- chip inductor
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- screen unit
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Abstract
The invention discloses a kind of induction structure, including on-chip inductor and the screen layer below the on-chip inductor, the screen layer includes at least one screen unit, the screen unit is orthogonal with the vortex flow direction produced by the on-chip inductor, the screen unit is made up of MOM capacitance structure, and the MOM capacitance structure includes that one group is parallel to each other and the first bonding jumper of square with certain intervals；And one group be parallel to each other and the second bonding jumper of square with certain intervals, first bonding jumper of group is located at layer metal level with second bonding jumper of group and forms finger-cross structure, and first bonding jumper connects power supply, second metal strips for grounding.The present invention makes full use of area below on-chip inductor to realize the function of voltage stabilizing mos capacitance.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of inductance for circuit chip structure.
Background technology
Inductance is the important passive device in radio frequency transceiver front end, and radio-frequency front-end transceiver module needs to use integrated electricity
That felt mainly has：Low-noise amplifier, power amplifier, agitator, up-conversion mixer etc..Inductance is played the part of in these modules
Important effect is drilled.
By taking low-noise amplifier as an example, low-noise amplifier is one of important module in radio frequency transceiver, is mainly used in
The signal for being received from antenna is amplified in communication system, be easy to the receiver circuit of rear class to process.Just because of noise amplifier
Whole receiver is located at close to the one-level at first of antenna, its characteristic directly affects the quality that whole receiver receives signal.
For low-noise amplifier, the performance of inductance directly determines the gain of low-noise amplifier, noise, impedance matching etc..
As a rule, Q-value is one of important indicator of an inductance performance, and higher Q-value means that the energy storage of inductance is damaged
Consumption is less, that is to say, that isolating between inductance and substrate is preferable.In addition, to the assessment of an inductance except inductance value, Q-value etc.
Outside conventional performance index, also include impact of the inductance to other circuits in radio system, if inductance itself and peripheral circuits
Isolation preferable, then the work of other circuits will not be affected in inductance work.
Due to the area of integrated silicon inductor generally larger, how while inductance performance is ensured, strengthen inductance and substrate,
Inductance is isolated with other circuits, has great significance for the module for being applied to radio-frequency front-end.
Fig. 1 show the schematic diagram of induction structure in prior art, and which is realized by the structure of the passive masking layer of substrate
Inductance is isolated with substrate.For IC chip typically, for 8 layers of metal level, top-level metallic and time
Top-level metallic is commonly used to make integrated inductor 1, and first layer metal be then used for making as shown in Figure 1 below inductance 1
Passive shelter sealing coat 2, passive sealing coat 2 of sheltering is by a plurality of independent and first layer metal line structure in 90 degree of rectangular shapeds itself
Into.These first layer metal lines are vertical with the vortex flow direction produced by integrated inductor 1, passive shelter sealing coat 2 so as to reach
Cut-out impact of the inductance galvanomagnetic-effect to substrate.Significantly, since the area of inductance generally larger (as 300 microns ×
300 microns), make passive masking layer thereunder and can no doubt play a part of electromagnetic isolation, but but without effectively utilizes electricity
The area of sense lower section.
Content of the invention
Present invention is primarily targeted at overcoming the defect of prior art, the area below induction areas is made full use of, is made
Screen layer has isolation and the effect of electric capacity of voltage regulation concurrently.
For reaching above-mentioned purpose, the present invention provides a kind of induction structure, including on-chip inductor and positioned at described upper electricity
The screen layer of sense lower section, the screen layer include that at least one screen unit, the screen unit are produced with the on-chip inductor
Raw vortex flow direction is orthogonal, and the screen unit is made up of MOM capacitance structure, the MOM capacitance structure include one group mutual
Parallel and the first bonding jumper of square with certain intervals, one end closing of first bonding jumper of group are connected；One group is mutually put down
Row and the second bonding jumper of square with certain intervals, one end closing of second bonding jumper of group are connected, first metal of group
Bar is located at layer metal level with second bonding jumper of group and forms finger-cross structure, and first bonding jumper connects power supply, and described second
Metal strips for grounding, has dielectric medium between first bonding jumper and second bonding jumper.
Preferably, the MOM capacitance structure includes multigroup the first bonding jumper positioned at different metal layer and multigroup positioned at not
The second bonding jumper with metal level.
Preferably, by through-hole interconnection between first bonding jumper of different metal layer, positioned at different metal layer
Second bonding jumper between pass through through-hole interconnection.
Preferably, the MOM capacitance structure includes 4 group of first bonding jumper and the difference position for being located at 4 layers of metal level respectively
In 4 group of second bonding jumper of 4 layers of metal level, first bonding jumper and second bonding jumper positioned at same layer metal level is formed
Finger-cross structure.
Preferably, the material of the dielectric medium is silicon dioxide.
Preferably, the on-chip inductor is square spiral coil, and the number of the screen unit is 4, and described 4
Screen unit is distributed with the centrosymmetry of the on-chip inductor.
Preferably, there is interval between the screen unit.
It is an advantage of the current invention that screen layer can not only play on-chip inductor and substrate, on-chip inductor in induction structure
With the buffer action between other circuits, the screen unit of further screen layer is constituted based on MOM capacitance structure, additionally it is possible to
It is connected between the supply voltage of chip and ground as big voltage stabilizing mos capacitance, serves the pressure stabilization function of supply voltage, so as to fills
Point make use of the larger area below on-chip inductor.
Description of the drawings
Fig. 1 is the schematic diagram of induction structure in prior art.
Fig. 2 is the schematic diagram of MOM capacitance structure in prior art.
Schematic diagrams of the Fig. 3 for embodiment of the present invention induction structure.
Specific embodiment
For making present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Step explanation.The specific embodiment, the general replacement known to those skilled in the art the invention is not limited in certainly
Cover within the scope of the present invention.
The induction structure of the present invention includes on-chip inductor and the screen layer below on-chip inductor.Wherein, on-chip inductor
It is made by top-level metallic and time top-level metallic, screen layer includes at least one screen unit.The arrangement mode of screen unit
The arrangement mode for sheltering first layer metal in sealing coat passive to prior art is similar, that is to say with produced by on-chip inductor
Vortex flow direction is orthogonal such that it is able to cut off impact of the inductance galvanomagnetic-effect to substrate.
Wherein, screen unit is made up of MOM capacitance structure.In modern integrated circuits technique, especially 90nm and with
In lower technology node, the MIM capacitor that commonly uses in original technique is generally replaced by MOM capacitor.For MOM capacitor, such as Fig. 2
Shown, (electric capacity top crown is MOM Cap Metal A, pole under electric capacity used as the pole plate of two-layer up and down of electric capacity to adopt same layer metal
Plate is MOM Cap Metal B), solved highly dense as dielectric material using silicon dioxide between the upper and lower two-layer pole plate of electric capacity
Degree electric capacity and the integration problem of standard technology.In the present invention, the MOM capacitance structure of screen unit is also by standard integrated circuit work
Skill is fabricated by, it is notable that the MOM capacitance structure of the present embodiment includes that one group is parallel to each other and with certain intervals
The first bonding jumper of square, one end closing of first bonding jumper of group are connected；One group is parallel to each other and with the straight of certain intervals
Angular second bonding jumper, one end closing of second bonding jumper of group are connected, first bonding jumper of group and the second bonding jumper of group position
In same layer metal level and finger-cross structure is formed, the first bonding jumper connects power supply, the second metal strips for grounding, the first bonding jumper and the second gold medal
There is dielectric medium between category bar, dielectric medium can be silicon dioxide.
Due to the second metal strips for grounding, therefore formed below a plurality of orthogonal with vortex flow direction equivalent in on-chip inductor
Grounded metal line such that it is able to well in on-chip inductor magnetic field and substrate, and on-chip inductor magnetic field and other circuits it
Between realize cut-off so that substrate loss reduce, while also reducing the signal cross-talk to other circuit devcies.Additionally, being connected to
First bonding jumper of whole chip power voltage is the upper strata pole plate of MOM capacitor, is connected to second gold medal on the ground of whole chip
Category bar is lower floor's pole plate of MOM capacitor, and the dielectric medium between the first bonding jumper and the second bonding jumper is MOM capacitor upper and lower two
With the intermetallic dielectric material of layer between layer pole plate.So as to, the MOM capacitor connect between the supply voltage and ground, equivalent to
A bulky capacitor is connected between the supply voltage and ground of chip, serves the pressure stabilization function of supply voltage.It is worthy of note that,
Traditional supply voltage voltage regulation way usually connects a large-scale mos capacitance between the supply voltage and ground, in order to ensure MOS
Capacitance sufficiently large, it usually needs very big transistor area, and would generally independently occupy quite a few area of chip,
The area cost of chip is caused to increase.And the induction structure of the present invention is formed below on-chip inductor using MOM capacitance structure
Screen layer, therefore take full advantage of the larger area below on-chip inductor region, without the need for again additionally increase chip area arrange
Large-scale mos capacitance, the cost that effectively saves.
Preferably, MOM capacitance structure includes multigroup the first bonding jumper positioned at different metal layer with multigroup positioned at Bu Tong gold
Second bonding jumper of category layer, can pass through between the first bonding jumper of different metal layer and the second bonding jumper of different metal layer between
Through-hole interconnection, increases the area of the upper and lower two-layer pole plate of MOM capacitor so as to realize multiple layer metal parallel connection.An enforcement in the present invention
In example, first bonding jumper and the second bonding jumper of MOM capacitance structure are respectively located in 4 layers of metal level, that is to say MOM capacitor
The side wall that two-layer pole plate is formed by four layers of metal laminate respectively up and down is constituted.
Fig. 3 show the schematic diagram of the induction structure of first embodiment of the invention.Fig. 3 is refer to, on-chip inductor 10 is for just
Square spiral coil, is made by top-level metallic and time top-level metallic.Screen layer has 4 screen units, in on-chip inductor
10 centrosymmetry distribution, forms " ten " font interval between 4 screen units.Each screen unit is by MOM capacitance structure
20 compositions, the MOM capacitance structure that therefore integrated circuit technology in the lower section of on-chip inductor with 4 standards is made, respectively
Upper left corner MOM capacitance structure, upper right corner MOM capacitance structure, lower left corner MOM capacitance structure and lower right corner MOM capacitance structure.Each
MOM capacitance structure includes that one group is parallel to each other and the first bonding jumper of square 21 with certain intervals, one group be parallel to each other and
There is second bonding jumper of square 22 of certain intervals, and the dielectric medium between the first bonding jumper 21 and the second bonding jumper 22.
First bonding jumper 21 and the second bonding jumper 22 of wherein each MOM capacitance structure 20 outwards dissipates arrangement with equidirectional, many
One end closing of individual first bonding jumper 21 is connected, and one end closing of multiple second bonding jumpers 22 is connected；First bonding jumper 21 and
Two bonding jumpers 22 are located at layer metal level and form finger-cross structure, and the first bonding jumper 21 meets power vd D, and the second bonding jumper 22 connects
Ground GND.As the second bonding jumper 22 of MOM capacitance structure 20 is grounded, which is equivalent to the grounded metal line of square, therefore, it is possible to
Shield the magnetic interference of square spiral coil well, and the first bonding jumper 21 is connect after supply voltage then equivalent in power supply
A MOM capacitor is connected between voltage and ground, the pressure stabilization function of supply voltage is played, so as to take full advantage of on-chip inductor area
Larger area below domain, arranges traditional large-scale mos capacitance without the need for additionally increasing chip area again.
To sum up, induction structure proposed by the invention, forms the shielding below on-chip inductor using MOM capacitance structure
Layer, between inductance and substrate, plays the buffer action of inductance and substrate, inductance and peripheral circuits, additionally, MOM capacitance structure
As big voltage stabilizing mos capacitance, it is connected between the supply voltage of chip and ground, serves the pressure stabilization function of supply voltage.Therefore,
Compared to prior art, the present invention takes full advantage of the larger area below on-chip inductor, effectively reduces conventional power source voltage
The area that voltage stabilizing MOS transistor is taken on chip, saves cost.
Although the present invention is disclosed as above with preferred embodiment, so many embodiments are illustrated only for the purposes of explanation
, the present invention is not limited to, those skilled in the art can make without departing from the spirit and scope of the present invention
Some changes and retouching, the protection domain advocated by the present invention should be to be defined described in claims.
Claims (7)
1. a kind of induction structure, including on-chip inductor and the screen layer below the on-chip inductor, the screen layer bag
At least one screen unit is included, the screen unit is orthogonal with the vortex flow direction produced by the on-chip inductor, and its feature exists
In,
The screen unit is made up of MOM capacitance structure, and the MOM capacitance structure includes：
One group is parallel to each other and the first bonding jumper of square with certain intervals, one end closing phase of first bonding jumper of group
Even；
One group is parallel to each other and the second bonding jumper of square with certain intervals, one end closing phase of second bonding jumper of group
Even, first bonding jumper of group is located at layer metal level with second bonding jumper of group and forms finger-cross structure, first bonding jumper
Power supply is connect, second metal strips for grounding has dielectric medium between first bonding jumper and second bonding jumper.
2. induction structure according to claim 1, it is characterised in that the MOM capacitance structure includes multigroup positioned at difference
First bonding jumper of metal level and multigroup the second bonding jumper positioned at different metal layer.
3. induction structure according to claim 2, it is characterised in that positioned at different metal layer first bonding jumper it
Between by through-hole interconnection, pass through through-hole interconnection between second bonding jumper of different metal layer.
4. induction structure according to claim 3, it is characterised in that the MOM capacitance structure includes being located at 4 layers of gold respectively
4 group of first bonding jumper for belonging to layer and 4 group of second bonding jumper for being located at 4 layers of metal level respectively, positioned at described in same layer metal level
First bonding jumper and second bonding jumper form finger-cross structure.
5. induction structure according to claim 1, it is characterised in that the material of the dielectric medium is silicon dioxide.
6. induction structure according to claim 1, it is characterised in that the on-chip inductor is square spiral coil, institute
The number for stating screen unit is 4, and 4 screen units are distributed with the centrosymmetry of the on-chip inductor.
7. induction structure according to claim 6, it is characterised in that there is between the screen unit interval.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210496838.5A CN102956622B (en) | 2012-11-29 | 2012-11-29 | A kind of induction structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210496838.5A CN102956622B (en) | 2012-11-29 | 2012-11-29 | A kind of induction structure |
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| Publication Number | Publication Date |
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| CN102956622A CN102956622A (en) | 2013-03-06 |
| CN102956622B true CN102956622B (en) | 2017-03-15 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337494A (en) * | 2013-06-08 | 2013-10-02 | 上海集成电路研发中心有限公司 | Inductance structure |
| TWI675478B (en) * | 2018-10-30 | 2019-10-21 | 力晶積成電子製造股份有限公司 | Metal-oxide-metal capacitor structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101131998A (en) * | 2006-08-22 | 2008-02-27 | 联华电子股份有限公司 | Conductor screening pattern and semiconductor structure with inductance element |
| US8106479B1 (en) * | 2008-10-01 | 2012-01-31 | Qualcomm Atheros, Inc. | Patterned capacitor ground shield for inductor in an integrated circuit |
| CN102446898A (en) * | 2011-12-27 | 2012-05-09 | 杭州电子科技大学 | Integrated circuit on-chip inductor structure with multiple substrate shielding layers |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3488164B2 (en) * | 2000-02-14 | 2004-01-19 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device |
| US20110133308A1 (en) * | 2009-05-22 | 2011-06-09 | Chan Kuei-Ti | Semiconductor device with oxide define pattern |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101131998A (en) * | 2006-08-22 | 2008-02-27 | 联华电子股份有限公司 | Conductor screening pattern and semiconductor structure with inductance element |
| US8106479B1 (en) * | 2008-10-01 | 2012-01-31 | Qualcomm Atheros, Inc. | Patterned capacitor ground shield for inductor in an integrated circuit |
| CN102446898A (en) * | 2011-12-27 | 2012-05-09 | 杭州电子科技大学 | Integrated circuit on-chip inductor structure with multiple substrate shielding layers |
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