CN107919356A - A kind of domain structure and its implementation for improving capacitance matching degree - Google Patents
A kind of domain structure and its implementation for improving capacitance matching degree Download PDFInfo
- Publication number
- CN107919356A CN107919356A CN201711206393.1A CN201711206393A CN107919356A CN 107919356 A CN107919356 A CN 107919356A CN 201711206393 A CN201711206393 A CN 201711206393A CN 107919356 A CN107919356 A CN 107919356A
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- port
- capacitance
- metal
- matching degree
- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
A kind of domain structure for improving capacitance matching degree, including, upper and lower metal layer level, and intermediate metal layer level, the single longitudinal metal of the upper and lower metal layer level and the intermediate metal layer level, forms port A；The single longitudinal metal of the left and right sides intermetallic metal level of the port A, forms port B；The upper and lower metal layer level, and be attached between the intermediate metal layer level by through hole.The present invention also provides a kind of realization method of layout for improving capacitance matching degree, using horizontal sidewall capacitance, reduces longitudinal capacitance, so as to reduce the matching precision between the parasitic capacitance of port, increase specific capacitance.
Description
Technical field
The present invention relates to EDA technical fields, more particularly to a kind of domain structure for improving capacitance matching degree and its realization
Method.
Background technology
Capacitance is the Important Components in integrated circuit, is widely used in such as sampling hold circuit, analog-digital converter, filter
In ripple device, and the module such as radio circuit.The matching precision of capacitance can directly affect the linearity of whole module, speed, area,
The factors such as power consumption.The capacitance that integrated circuit is realized includes MOM capacitor, MIM capacitor, PIP capacitor etc..Wherein with process not
Disconnected to reduce, the specific capacitance density of MOM capacitor increases, while MOM capacitor has the good linearity and Q values, very much
Occasion is obtained for large-scale application.In the evolution of modern crafts, the size reduction speed of vertical direction will be much smaller than
Horizontal size reduction speed.Therefore, MOM capacitor value is made of two parts in deep submicron process：Lateral sidewalls capacitance with
And plates capacitance above and below longitudinal direction.Due to the capacitance of horizontal and vertical both direction can be produced in industrial manufacturing process it is entirely different
Deviation, the matching precision of specific capacitance can be substantially reduced.
The content of the invention
In order to solve the shortcomings of the prior art, it is an object of the invention to provide a kind of version for improving capacitance matching degree
Graph structure and its implementation, by using lateral capacitance, reduce longitudinal capacitance, so as to reduce the parasitic capacitance of B ports, increase
Matching precision between specific capacitance.
To achieve the above object, the domain structure provided by the invention for improving capacitance matching degree, including, upper and lower metal layer
Level, and intermediate metal layer level, wherein,
The single longitudinal metal of the upper and lower metal layer level and the intermediate metal layer level, forms port A；
The single longitudinal metal of the left and right sides intermetallic metal level of the port A, forms port B；
The upper and lower metal layer level, and be attached between the intermediate metal layer level by through hole.
Further, the upper and lower metal layer level, for shielding parasitic capacitances of the port B to other media.
Further, the intermediate metal layer level, for producing main body wall capacitance.
Further, the port A and port B is the arrangement mode of single port from top to bottom, and it is interdigital to form vertical bar
Shape.
Further, the port A is located at same upright position, and the port B is located at same upright position.
To achieve the above object, the realization method of layout provided by the invention for improving capacitance matching degree, comprises the following steps：
（1）The superiors' metal and orlop metal, and the single longitudinal metal of intermetallic metal level are connected, forms port A.
（2）The single longitudinal metal of the left and right sides intermetallic metal level of connectivity port A, forms port B.
（3）According to the capacitance of capacitance, the metal level of intermetallic metal, and the number of port A and port B are determined.
（4）According to the capacitance of total capacitance, multiple capacitor cell arrays are laid out.
（5）To capacitor array into walking line.
The domain structure and its implementation of the raising capacitance matching degree of the present invention, same upright position is placed on by port A,
Port B is placed on same upright position, and the capacitance of such port A and port B are mainly determined by sidewall capacitance, substantially reduce longitudinal direction
Plates capacitance up and down, so as to improve matching.
Using upper and lower metal layer as port A, parasitic capacitances of the port B to other media is shielded completely, for such as high
Fast analog-digital converter, switched-capacitor circuit etc. have the parasitism of single-port the application scenario of larger sensitiveness, have and improve line
The effect of property degree.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
Obtain it is clear that or being understood by implementing the present invention.
Brief description of the drawings
Attached drawing is used for providing a further understanding of the present invention, and a part for constitution instruction, and with the present invention's
Embodiment together, for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings：
Fig. 1 is the domain structure longitudinal sectional drawing according to the raising capacitance matching degree of the present invention；
Fig. 2 is the M according to the domain structure of the raising capacitance matching degree of the present inventionN、MZ、MYThe transverse, top-down-view of layer；
Fig. 3 is the M according to the domain structure of the raising capacitance matching degree of the present inventionXAnd MKThe transverse, top-down-view of layer；
Fig. 4 is the domain structure implementation method flow chart according to the raising capacitance matching degree of the present invention.
Embodiment
The preferred embodiment of the present invention is illustrated below in conjunction with attached drawing, it will be appreciated that described herein preferred real
Apply example to be merely to illustrate and explain the present invention, be not intended to limit the present invention.
Fig. 1 is that Fig. 2 is according to the present invention's according to the domain structure longitudinal sectional drawing of the raising capacitance matching degree of the present invention
Improve the M of the domain structure of capacitance matching degreeN、MZ、MYThe transverse, top-down-view of layer, Fig. 3 are to be matched according to the raising capacitance of the present invention
The M of the domain structure of degreeXAnd MKThe transverse, top-down-view of layer, as shown in Figs. 1-3, matches the raising capacitance of the invention of the present invention
The domain structure of degree, including：
Upper and lower metal layer level MKAnd MX, to shield parasitic capacitances of the port B to other media；
Intermediate metal layer level MN、MZ、MY, to produce main body wall capacitance；
Through hole, to connect different metal levels；
The superiors metal MKWith orlop metal MX, and intermetallic metal level MN、MZ、MYSingle longitudinal metal A, form end
Mouth A；
The left and right sides intermetallic metal level M of port AN、MZ、MYSingle longitudinal metal B, form port B；
Port A and port B is the arrangement mode of single port from top to bottom, vertical bar interdigitated is formed, for reducing longitudinal parasitism
Capacitance.
Fig. 4 is according to the domain structure implementation method flow chart of the raising capacitance matching degree of the present invention, below with reference to figure
4, the domain structure implementation method of the raising capacitance matching degree of the present invention is described in detail.
In step 101, the superiors metal M is connectedKWith orlop metal MX, and intermetallic metal level MN、MZ、MYIt is single
Longitudinal metal A, forms port A.
In step 102, the left and right sides intermetallic metal level M of connectivity port AN、MZ、MYSingle longitudinal metal B, form
Port B.
In step 103, according to the capacitance of required capacitance, the metal level of intermetallic metal, and port A and port are determined
The number of B.
In step 104, according to the capacitance of required total capacitance, multiple capacitor cell arrays are laid out.
Especially, can the domain structure of the present invention be used as specific capacitance, the number of capacitor cell array be total capacitance value/
Unit capacitance values.
In step 105, to capacitor array into walking line.
The superiors metal MKWith orlop metal MXIt is connected on the A of port, arrives port A, maximum journey by parasitic capacitance is all equivalent
Degree reduces the parasitic capacitance of port B, the application scenario having higher requirements for Approach by inchmeal etc. to single-port, can be with
Improve its linearity.
One of ordinary skill in the art will appreciate that：The foregoing is only a preferred embodiment of the present invention, and does not have to
In the limitation present invention, although the present invention is described in detail with reference to the foregoing embodiments, for those skilled in the art
For, its still can to foregoing embodiments record technical solution modify, or to which part technical characteristic into
Row equivalent substitution.Within the spirit and principles of the invention, any modification, equivalent replacement, improvement and so on, should all include
Within protection scope of the present invention.
Claims (6)
1. a kind of domain structure for improving capacitance matching degree, including, upper and lower metal layer level, and intermediate metal layer level, its
It is characterized in that,
The single longitudinal metal of the upper and lower metal layer level and the intermediate metal layer level, forms port A；
The single longitudinal metal of the left and right sides intermetallic metal level of the port A, forms port B；
The upper and lower metal layer level, and be attached between the intermediate metal layer level by through hole.
2. the domain structure according to claim 1 for improving capacitance matching degree, it is characterised in that the upper and lower metal layer
Level, for shielding parasitic capacitances of the port B to other media.
3. the domain structure according to claim 1 for improving capacitance matching degree, it is characterised in that the intermetallic metal is layer by layer
It is secondary, for producing main body wall capacitance.
4. it is according to claim 1 improve capacitance matching degree domain structure, it is characterised in that the port A with it is described
Port B is the arrangement mode of single port from top to bottom, forms vertical bar interdigitated.
5. the domain structure according to claim 1 for improving capacitance matching degree, it is characterised in that the port A is positioned at same
One upright position, the port B are located at same upright position.
6. a kind of realization method of layout for improving capacitance matching degree, comprises the following steps：
（1）The superiors' metal and orlop metal, and the single longitudinal metal of intermetallic metal level are connected, forms port A；
（2）The single longitudinal metal of the left and right sides intermetallic metal level of connectivity port A, forms port B；
（3）According to the capacitance of required capacitance, the metal level of intermetallic metal, and the number of port A and port B are determined；
（4）According to the capacitance of required total capacitance, multiple capacitor cell arrays are laid out；
（5）To capacitor array into walking line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711206393.1A CN107919356A (en) | 2017-11-27 | 2017-11-27 | A kind of domain structure and its implementation for improving capacitance matching degree |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711206393.1A CN107919356A (en) | 2017-11-27 | 2017-11-27 | A kind of domain structure and its implementation for improving capacitance matching degree |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109214130A (en) * | 2018-10-30 | 2019-01-15 | 成都九芯微科技有限公司 | A kind of layout design method of SARADC systematic sampling MOM capacitor |
| CN116681907A (en) * | 2023-05-08 | 2023-09-01 | 珠海妙存科技有限公司 | Matching precision detection method of metal capacitor, controller and storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107633128A (en) * | 2017-09-15 | 2018-01-26 | 北京华大九天软件有限公司 | The layout and Wiring method of MOM capacitor, MOM capacitor array and MOM capacitor array |
-
2017
- 2017-11-27 CN CN201711206393.1A patent/CN107919356A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107633128A (en) * | 2017-09-15 | 2018-01-26 | 北京华大九天软件有限公司 | The layout and Wiring method of MOM capacitor, MOM capacitor array and MOM capacitor array |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109214130A (en) * | 2018-10-30 | 2019-01-15 | 成都九芯微科技有限公司 | A kind of layout design method of SARADC systematic sampling MOM capacitor |
| CN116681907A (en) * | 2023-05-08 | 2023-09-01 | 珠海妙存科技有限公司 | Matching precision detection method of metal capacitor, controller and storage medium |
| CN116681907B (en) * | 2023-05-08 | 2024-01-09 | 珠海妙存科技有限公司 | Matching precision detection method of metal capacitor, controller and storage medium |
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Application publication date: 20180417 |