CN102956593B - 带有开关装置和触发装置的电力电子系统 - Google Patents

带有开关装置和触发装置的电力电子系统 Download PDF

Info

Publication number
CN102956593B
CN102956593B CN201210285356.5A CN201210285356A CN102956593B CN 102956593 B CN102956593 B CN 102956593B CN 201210285356 A CN201210285356 A CN 201210285356A CN 102956593 B CN102956593 B CN 102956593B
Authority
CN
China
Prior art keywords
printed conductor
power
contact surface
pliotron
electronic system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201210285356.5A
Other languages
English (en)
Other versions
CN102956593A (zh
Inventor
斯特凡·斯库勒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semikron GmbH and Co KG
Original Assignee
Semikron GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron GmbH and Co KG filed Critical Semikron GmbH and Co KG
Publication of CN102956593A publication Critical patent/CN102956593A/zh
Application granted granted Critical
Publication of CN102956593B publication Critical patent/CN102956593B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

带有开关装置和触发装置的电力电子系统。开关装置具有多个功率开关和至少一个带有多个彼此电绝缘的印制导线的基板。至少一个功率开关构造为带有第一接触面的至少一个功率三极管和至少一个功率二极管，其与引导第一负载电势的第一印制导线电导通地连接。在背离基板的侧面上布置的第二接触面借助作为内部连接装置的部件的第一连接装置彼此地并且与至少一个引导第二负载电势的第二印制导线连接，其中，至少一个功率三极管的控制端与引导控制电势的印制导线连接。此外，功率三极管的第二接触面与另外的印制导线连接，该印制导线虽然具有所属的负载电势，但不引导负载电流。在此，触发装置的参考电势是开关装置的基板的另外的印制导线的参考电势。

Description

带有开关装置和触发装置的电力电子系统
技术领域
本发明描述一种电力电子系统，例如公知为带有集成的或者外部的触发装置的功率半导体模块。
背景技术
由DE 298 23 619公知带有多个并联的功率三极管的功率半导体电路系统，其中，在带有多个在该文中构造的印制导线的绝缘的基板上布置有所述功率三极管。在这种功率半导体电路系统运行时，在不同的开关状态中得出高频的振荡，特别是也在负载电路中。为了减少这种振荡，公知直接连接优选相邻的功率三极管的发射极。调整印制导线的几何尺寸同样是公知的。
由上面的文献以及通常地公知，用于功率三极管与配属的印制导线连接的连接装置构造为线焊连接。在这里，此概念概念下，应该包括不同的、基本技术上同类的设计方案，例如带焊连接。同样一般地公知，对线焊连接来说额外地或者备选地，这种连接装置构造为柔性的、例如由导电的和绝缘的能够内部结构化的薄膜的层序列制成的电路板。
除了上面描述的多个功率三极管的振荡倾向，事实证明，由仅一个功率三极管和与其反并联的功率二极管的组合在一定的运行条件下也同样倾向于在高频的范围内振荡。
发明内容
由此，本发明的任务在于介绍一种电力电子系统，该电力电子系统设计并组合至少一个开关装置与至少一个配属的触发装置，从而极有效地抑制即使是仅一个功率三极管的和与其反并联连接的功率二极管的振荡倾向。
依据本发明，该任务通过带有权利要求1的特征的电力电子系统解决。优选的实施方式在从属权利要求中描述。
接下来分别由如下功率开关出发，所述功率开关构造为至少一个带有至少一个反并联的功率二极管的功率三极管。对不同的电路拓扑的(如带有第一和第二功率开关的半桥)或者也对(同样地公知为这样的)多级电路拓扑的推广当然类似地进行。
依据本发明的电力电子系统至少由开关装置和由至少一个配属的触发装置组成。在这种情况中，至少一个各自的开关装置构造为电力电子电路，该电力电子电路具有至少一个带有多个彼此电绝缘的印制导线的基板。在引导第一负载电势的第一印制导线上布置有功率开关。该功率开关构造为至少一个功率三极管和至少一个功率二极管。二者在它们的第一表面上具有至少一个用于负载连接的第一接触面。这些各自的第一接触面与第一印制导线电导通地连接。二者在背离基板的侧面上具有用于负载连接的第二接触面。功率三极管在这侧端上额外地具有用于控制连接的接触面。
功率三极管优选地设计为IGBT(绝缘栅双极型晶体管)，它的第一接触面构造集电极端，而第二接触面构造发射极端。优选地，功率二极管的第一接触面构造其阴极，而第二接触面构造其阳极。
优选地，功率三级管的第二接触面(发射极端)分别与功率二极管的第二接触面(阳极端)借助作为内部的连接装置的部件的第一连接装置彼此地连接和与至少一个引导第二负载电势的第二印制导线连接。该第二印制导线可以例如与外部的负载端元件连接，并且同时地或者备选地也以基本上相同的、如上面所提及的方式承载其它的功率开关。
依据本发明，至少一个功率三极管的第二接触面与另外的印制导线连接，该印制导线虽然具有所属的负载电势，但不引导负载电流。该另外的印制导线形成配属的触发装置的参考电势。为此，触发装置与开关装置的基板的其它的印制导线直接地并且唯一地连接。由此，除了经由功率二极管的间接的连接，触发装置至基板的第二印制导线的直接的连接不存在。
在每个功率开关有多个功率三极管时，可以将正好一个功率三极管以其第二接触面与基板的其它的印制导线连接，或者多个功率三极管可以以其第二接触面与基板的其它的印制导线连接，或者所有的功率三极管可以以其第二接触面与基板的其它的印制导线连接。
此外公知，功率三极管具有多个第二接触面。在这种情况中，可以有利的是，相应地连接仅一个或者多个或者所有的第二接触面。
此外，至少一个功率三极管的控制端(该控制端的接触面同样布置在背离基板的侧端)与引导控制电势的印制导线并且经由此与配属的触发电路连接。由此，由触发装置产生的触发信号与引导控制电势的印制导线连接并且经由此与功率三极管的控制端连接。
所有提及的不借助基板本身构造的连接借助内部的连接装置构造，该连接装置要么构造为多个线焊连接和额外地要么备选地借助至少一个柔性电路板构造。
附图说明
借助实施例，依据图1至3进一步阐明本发明的解决方案。
图1在电力电子的基本电路中示出现有技术，以及示意地示出本发明的基本想法；
图2示出穿过依据本发明的电力电子系统的第一设计方案的一部分的横断面；
图3示出依据本发明的电力电子系统的第二设计方案的一部分的俯视图。
具体实施方式
接下来，借助半桥电路描述依据本发明的电力电子系统。基本上，依据本发明，其它的电路拓扑也是可构造的，例如直流电桥电路或者每个电桥电路带有多于两个的串联的功率开关的多级电桥电路。
图1在电力电子的基本电路中示出现有技术，以及示意地示出本发明的基本想法。为此，画出三个半桥电路。
左侧的第一半桥电路示出一般的示图，带有上面的也称为“TOP”的第一功率开关10和下面的也称为“BOT”的第二功率开关20。这些功率开关10、20与直流电压源连接，而它们的中间抽头形成第一相的交流电压输出。
在中间示出的半桥电路示意地示出依据现有技术的实施方式，而右边的半桥电路画出依据本发明的实施方式。在两个半桥电路中，各功率开关10、20构造为功率三极管110、210，具体为带有反并联功率二极管120、220的IGBT(绝缘栅双极型晶体管)。基本上，每个功率开关10、20自然也可以具有多于一个的功率三极管110、210和多于一个的功率二极管120、220。
依据现有技术，在中间的半桥电路中示意地示出：第一接触面，即TOP功率三极管110的集电极接触面112(参照图2)和第一接触面，即TOP功率二极管120的阴极接触面122(参照图2)布置在基板30(参照图2)的第一印制导线302上(参照图2)。借助内部的连接装置(多构造为线焊连接)，第二接触面，即TOP功率三极管110的发射极接触面114(参照图2)和TOP功率二极管120的阳极接触面124(参照图2)与彼此并且与第二印制导线连接。该第二印制导线在这里承载BOT功率开关20的组件，并且为了这些组件又依据本发明构造第一印制导线。
在这种情况下，在功率三极管的发射极接触面与第二印制导线之间的引导负载电势和负载电流的内部第一连接装置40(参照图2)具有在5nH与40nH之间的、通常在10nH和20nH之间的范围内的寄生电感400、420。该电感与功率三极管110、210的内部电容(特别是那些所谓的栅极-发射极电容)构造振荡回路，该振荡回路在运行中在换向时由于在此出现的快速电流变化而产生高频振荡，该振荡反作用于触发装置50、52，该触发装置的参考电势处于第二印制导线的电势。
在依据本发明的设计方案中，触发装置的参考电势处于其它的印制导线308上(参照图2)，该印制导线具有与第二印制导线相同的负载电势，但没有引导负载电流。通过适当选择发射极接触面与这个其它的印制导线之间的第一内部连接装置的部件，那些引导负载电流的、内部连接装置的所述部件的寄生电感可以部分地(参照右边的半桥的TOP功率开关)或者甚至完全地(参照右边的半桥的BOT功率开关)不在触发装置上产生反作用。当部分地反作用在振荡回路上时，第一内部的连接装置的寄生电感在一定程度上分成第一有效电感部分402、422和第二无效电感部分404、424。
图2示出穿过依据本发明的电力电子系统的第一设计方案的一部分的横断面。在这里示出开关装置2(例如构造为功率半导体模块)以及配属的触发装置50(在这里构造为直接布置在半导体模块2之上的驱动电路)。
半导体模块2具有带有多个彼此电绝缘的印制导线302、306、308的基板30。为此，基板30具有优选地由工业陶瓷构造的绝缘体300，在该绝缘体上优选地平面地布置有所述印制导线。在第一印制导线302上，布置有各功率开关(在这里构造为IGBT 110和功率二极管120)。在这种情况下，IGBT 110的集电极接触面112与功率二极管120的阴极接触面122材料锁合地且电导通地与第一印制导线302连接。
在这里，借助线焊连接构造有连接装置。在这种情况下，多个(仅示出一个)引导负载电流的第一线焊连接40使IGBT 110的发射极接触面114与功率二极管120的阳极接触面124并且与同样未示出的引导负载电势和负载电流的第二印制导线304(参照图3)连接。
控制端，即IGBT 110的栅极接触面116同样借助第二线焊连接46典型地以焊线的较小直径与配属的、引导控制电势的印制导线306连接。
另一线焊连接48将发射极接触面114与基板30的另外的印制导线308连接，其中，该另外的线焊连接48以及配属的另外的印制导线308引导负载电势，但不引导负载电流。
依据本发明，触发电路50仅与引导控制电势的印制导线306和与所述另外的印制导线308连接。在这里，示出在功率半导体模块内常见的借助接触弹簧进行的到通常布置在功率半导体模块2外部的触发装置50的连接。
在电力电子系统的这种尤其有利的设计中，引导负载电流的线焊连接的寄生电感和由此产生的不希望的高频的振荡不反作用于触发装置50。依据图1，这种设计方案相应于右边的半桥的BOT功率开关20。
图3示出依据本发明的电力电子系统的第二设计方案的一部分的俯视图。再次示出基板30，该基板基本上与在图2中描述的基板同样地构造并且在该基板上同样相似地布置有IGBT 110和功率二极管120。触发单元50的连接与依据图2的那种连接基本上同样，区别很小。
但在此不同的是，IGBT 110的发射极接触面114与另外的印制导线308之间的线焊连接40引导负载电势和负载电流。但另外的印制导线308本身依据本发明不引导负载电流。
以虚线示出现有技术，在该现有技术中，触发装置50的参考电势与引导负载电势和负载电流的第二印制导线304连接，并且其中该第二印制导线经由内部连接装置的引导负载电流的区段(这里是相应的第一线焊连接40)与IGBT 110的发射极接触面114连接。
这样的优点是，不需要设置额外的其它的线焊连接48(参照图2)，而是通过在另外的印制导线308上安置额外的焊脚408补充存在的线焊连接。
在这种电力电子系统的设计方案中，引导负载电流的线焊连接的寄生电感和由此产生的不希望的高频的振荡仅部分地反作用在触发装置50上。依据图1，这种设计方案相应于右边的半桥的TOP功率开关10。

Claims (9)

1.电力电子系统，其带有至少一个开关装置(2)和至少一个配属的触发装置(50、52)，其中，各个所述开关装置(2)具有多个功率开关和至少一个带有多个彼此电绝缘的印制导线(302、304、306、308)的基板(30)，其中，至少一个功率开关(10、20)构造为带有各自的第一接触面(112、122)的至少一个功率三极管(110、210)和至少一个功率二极管(120、220)，所述至少一个功率开关与引导第一负载电势的第一印制导线(302)电导通地连接，在至少一个功率三极管(110、210)和至少一个功率二极管(120、220)的背离所述基板的侧面上布置的各第二接触面(114、124)借助作为内部的连接装置(40、46、48)的部件的第一连接装置(40)彼此连接并且与至少一个引导第二负载电势的第二印制导线(304)连接，其中，所述至少一个功率三极管(110)的控制端(116)与引导控制电势的印制导线(306)连接，并且至少一个功率三极管(110、210)的所述第二接触面(114)与另外的印制导线(308)连接，所述另外的印制导线虽然具有所属的负载电势，但不引导负载电流，并且其中，所述配属的触发装置(50、52)的参考电势是开关装置(2)的基板(30)的所述另外的印制导线(308)的参考电势，并且所述触发装置(50、52)直接地并且唯一地与所述另外的印制导线(308)连接，并且至少一个由所述触发装置(50、52)产生的触发信号送到所述引导控制电势的印制导线(306)上。
2.根据权利要求1所述的电力电子系统，其中，所述功率三极管(110、210)是IGBT(绝缘栅双极型晶体管)并且以其第一接触面，即，集电极接触面(112)，与所述基板(30)的第一印制导线(302)连接。
3.根据权利要求1所述的电力电子系统，其中，所述功率二极管(120、220)以其第一接触面，即，阴极接触面(122)，与所述基板(30)的第一印制导线(302)连接。
4.根据权利要求1所述的电力电子系统，其中，在每个功率开关(10、20)有多个功率三极管(110、210)的情况下，恰好一个功率三极管(110、210)以其第二接触面，即，发射极接触面(114)，与所述基板(30)的所述另外的印制导线(308)连接，或者多个功率三极管(110、210)以其第二接触面(114)与基板(30)的所述另外的印制导线(308)连接，或者所有的功率三极管以其第二接触面(114)与所述基板(30)的所述另外的印制导线(308)连接。
5.根据权利要求1所述的电力电子系统，其中，所述内部的连接装置由多个线焊连接构造。
6.根据权利要求5所述的电力电子系统，其中，在功率三极管(110、210)的和功率二极管(120、220)的所述第二接触面(114、124)之间的多个线焊连接，即，所述第一连接装置(40)之一在所述另外的印制导线(308)上具有焊脚(408)。
7.根据权利要求5所述的电力电子系统，其中，在各功率三极管(110、210)的所述第二接触面(114)与所述另外的印制导线(308)之间设置有另外的线焊连接。
8.根据权利要求7所述的电力电子系统，其中，所述另外的线焊连接的焊线的直径比将所述功率三极管(110、210)的和所述功率二极管(120、220)的第二接触面(114、124)相连的线焊连接，即，所述第一连接装置(40)的那些焊线的直径小得多。
9.根据权利要求1所述的电力电子系统，其中，所述连接装置由柔性电路板构造。
CN201210285356.5A 2011-08-12 2012-08-10 带有开关装置和触发装置的电力电子系统 Expired - Fee Related CN102956593B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE201110080861 DE102011080861A1 (de) 2011-08-12 2011-08-12 Leistungselektronisches System mit einer Schalt- und einer Ansteuereinrichtung
DE102011080861.2 2011-08-12

Publications (2)

Publication Number Publication Date
CN102956593A CN102956593A (zh) 2013-03-06
CN102956593B true CN102956593B (zh) 2016-08-17

Family

ID=47073270

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2012203967361U Withdrawn - After Issue CN202930372U (zh) 2011-08-12 2012-08-10 带有开关装置和触发装置的电力电子系统
CN201210285356.5A Expired - Fee Related CN102956593B (zh) 2011-08-12 2012-08-10 带有开关装置和触发装置的电力电子系统

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN2012203967361U Withdrawn - After Issue CN202930372U (zh) 2011-08-12 2012-08-10 带有开关装置和触发装置的电力电子系统

Country Status (3)

Country Link
EP (1) EP2557595A1 (zh)
CN (2) CN202930372U (zh)
DE (1) DE102011080861A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011080861A1 (de) * 2011-08-12 2013-02-14 Semikron Elektronik Gmbh & Co. Kg Leistungselektronisches System mit einer Schalt- und einer Ansteuereinrichtung
DE102013104522B3 (de) * 2013-05-03 2014-06-26 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit Subeinheiten und Anordnung hiermit
DE102013107239B3 (de) * 2013-07-09 2014-03-20 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleiterschaltung
CN103367305A (zh) * 2013-07-31 2013-10-23 西安永电电气有限责任公司 一种用于igbt器件的电连接结构
JP6345361B2 (ja) * 2016-02-18 2018-06-20 三菱電機株式会社 パワー半導体モジュール
DE112016007133B4 (de) 2016-08-10 2021-08-12 Mitsubishi Electric Corporation Halbleitervorrichtung

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101933219A (zh) * 2008-01-31 2010-12-29 大金工业株式会社 电功率转换装置
CN202930372U (zh) * 2011-08-12 2013-05-08 赛米控电子股份有限公司 带有开关装置和触发装置的电力电子系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE29823619U1 (de) 1998-08-21 1999-09-30 Semikron Elektronik Gmbh Leistungshalbleiterschaltungsanordnung mit schwingungsgedämpfter Parallelschaltung
DE10121970B4 (de) * 2001-05-05 2004-05-27 Semikron Elektronik Gmbh Leistungshalbleitermodul in Druckkontaktierung
JP4540884B2 (ja) * 2001-06-19 2010-09-08 三菱電機株式会社 半導体装置
DE102004027186B3 (de) * 2004-06-03 2005-10-20 Eupec Gmbh & Co Kg Steuerkreis für ein elektrisches Modul
DE102005036116B4 (de) * 2005-08-01 2012-03-22 Infineon Technologies Ag Leistungshalbleitermodul
DE102006038479B4 (de) * 2006-08-17 2011-01-27 Infineon Technologies Ag Leistungshalbleitermodul mit zwei Mehrfach-Leistungshalbleiterbauelementen
WO2009150875A1 (ja) * 2008-06-12 2009-12-17 株式会社安川電機 パワーモジュールおよびその制御方法
JP4576448B2 (ja) * 2008-07-18 2010-11-10 三菱電機株式会社 電力用半導体装置
US8497574B2 (en) * 2011-01-03 2013-07-30 International Rectifier Corporation High power semiconductor package with conductive clips and flip chip driver IC

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101933219A (zh) * 2008-01-31 2010-12-29 大金工业株式会社 电功率转换装置
CN202930372U (zh) * 2011-08-12 2013-05-08 赛米控电子股份有限公司 带有开关装置和触发装置的电力电子系统

Also Published As

Publication number Publication date
CN202930372U (zh) 2013-05-08
CN102956593A (zh) 2013-03-06
DE102011080861A1 (de) 2013-02-14
EP2557595A1 (de) 2013-02-13

Similar Documents

Publication Publication Date Title
CN102956593B (zh) 带有开关装置和触发装置的电力电子系统
US11018109B2 (en) Power semiconductor module with low gate path inductance
US9960153B2 (en) Semiconductor device and electronic apparatus of a cascode-coupled system
CN102110680B (zh) 具有降低电感的功率模块组件
CN107851637B (zh) 功率半导体模块
US8487407B2 (en) Low impedance gate control method and apparatus
CN110649918B (zh) 开关电路和制造开关电路的方法
US7969208B2 (en) Control circuit for a power semiconductor assembly and power semiconductor assembly
CN103296016B (zh) 半导体模块
CN106169876B (zh) 电力变换装置
CN100397769C (zh) 小电感的电路结构
US20230187431A1 (en) Semiconductor module
JP2014064377A (ja) 半導体モジュール
JP2017184601A (ja) 電力変換装置
CN106449608A (zh) 半导体模块
JP2007053371A (ja) ライン要素を備えたパワー半導体モジュール
CN102447430B (zh) 电源电路
JP6394459B2 (ja) 半導体装置
CN102456635B (zh) 具有带多个同样构造导体迹线组的基底的功率半导体模块
CN112349657A (zh) 半导体模块装置
CN114270679A (zh) 控制模块以及半导体装置
US20240039421A1 (en) Multi-phase power converter
CN110545029B (zh) 大功率电能变换器的驱动装置
US20240006330A1 (en) High-symmetrical semiconductor arrangement
US20220102291A1 (en) Power module

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160817

Termination date: 20190810

CF01 Termination of patent right due to non-payment of annual fee