CN102956477B - Method for optimizing photoetching registration accuracy of emitting electrode of silicon germanium HBT (heterojunction bipolar transistor) - Google Patents
Method for optimizing photoetching registration accuracy of emitting electrode of silicon germanium HBT (heterojunction bipolar transistor) Download PDFInfo
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- CN102956477B CN102956477B CN201110240918.XA CN201110240918A CN102956477B CN 102956477 B CN102956477 B CN 102956477B CN 201110240918 A CN201110240918 A CN 201110240918A CN 102956477 B CN102956477 B CN 102956477B
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Abstract
The invention discloses a method for optimizing the photoetching registration accuracy of an emitting electrode of silicon germanium HBT ((heterojunction bipolar transistor). A photoetching registration mark and an overlaying accuracy measuring mark OVL mark of an opening layer of the emitting electrode are both placed in a field area. The process procedure includes that an active area photoetches and produces a substrate area of the registration mark and the overlaying accuracy measuring mark OVL mark of an opening of the emitting electrode; a substrate consisting of a SiO2 material of the registration mark and the overlaying accuracy measuring mark OVL mark of the opening of the emitting electrode is formed by depositing of SiO2 deposits and the CMP(chemical mechanical planarization); a base area BP is etched in front of the opening of the emitting electrode, and an opening film layer of the emitting electrode deposits after the base area BP etching; and wet etching is added after the photoetching of the opening of the emitting electrode. By the aid of the method, optical contract can be greatly strengthened, and errors and instability of optical alignment accuracy measurement caused by insufficient signal intensity are avoided.
Description
Technical field
The present invention relates to the technique manufacturing method of the germanium silicon Si/Ge heterojunction bipolar transistor HBT in a kind of electronic chip manufacture field, especially photoetching technological method.
Background technology
Si is one of topmost material of semiconductor device of current large-scale production, and it has raw material and prepares easy, and nature rich content has the fundamental characteristics such as characteristic of semiconductor and is used to prepare semiconductor device.
But high-frequency high-speed is applied, the energy gap of Si is wider, and the migration velocity of charge carrier is restricted, and therefore people usually introduce some other elements and form the alloy of Si to lower energy gap, improve the migration velocity of charge carrier, wherein Ge is one of wherein most important and main material.Ge has the crystal structure similar with Si, form alloy technique with Si easily to realize and matching is high, the introducing of Ge simultaneously can reduce energy gap effectively, realize the application of high speed device, the alloy component of Si/Ge is easy to carry out process integration with conventional Si device simultaneously, and therefore Si/Ge device is that be in daily use a kind of is applied at a high speed and the device of HF communication.Si/Ge is intrinsic semiconductor simultaneously, in order to practical devices application, also can carry out doping and form n, p-type.In addition in order to adjust the stress of film, the mesoscopic particles that also can adulterate is as C.
Based on above characteristic and technique, SI/Ge HBT is one of the most frequently used at present high-frequency element.For high-frequency element, Ft, Fmax are most important device indexs.And Ft, Fmax and base resistance relation are very large, especially Fmax.Reduce base resistance, the Base Transit Time improving charge carrier can improve Fmax greatly.In existing HBT structure, all adopt T-shaped emitter structure, as represented in figure 1.Now emitter (EP-Emitter Poly) cannot be injected by outer base area with the overlapping region 7C of emitter openings (EW-Emitter window) and reduce resistance, resistance can only be reduced by the doping of the outer time delay of SI/Ge, and adulterate by the impact of HBT device property specifically, cannot arbitrarily adjust.Therefore in such devices, in order to improve Fmax, the overlapping region of emitter and emitter openings must be reduced, making the outer base area that can not be doped little as far as possible.And this brings very large challenge to the lithography alignment of emitter.
In order to maintain alignment precision, emitter must be allowed to aim at emitter openings.And traditional alignment mark of emitter openings and overlay are accurately measured mark OVL mark and are produced by direct etching emitter openings, simultaneously in order to prevent substrate variations from affecting, its vertical stratification is that emitter openings layer is directly placed on a silicon substrate, and the height therefore finally forming step is the thickness of emitter openings rete itself.And after emitter deposition, because poly is opaque, therefore optical contrast places one's entire reliance upon its shoulder height, optical contrast=sin (2 × pi × d × n/lamda).Wherein d is shoulder height, and n is medium refraction index, is that air n=1, lamda are for measuring optical wavelength here.When d is 1/4 of lamda, reach interference maximum.For low frequency applications, the usual > of thicknesses of layers of emitter openings
, close to the conventional wave band of lithography alignment and measurement
1/4, therefore can reach interfere extremely strong, this design is feasible.But be in high-frequency element, in order to reduce parasitic capacitance, emitter openings rete is usually all very thin, now cannot form enough optical contrasts, thus cause lithography alignment signal usually very weak, make lithography alignment accuracy be difficult to improve, Simultaneous Stabilization is poor, and scale of mass production is unstable.
Tradition produces the technological process of emitter openings photoetching alignment mark as represented in fig. 3:
1. deposit emitter openings film on a silicon substrate (active area);
2. photoetching;
3. dry etching emitter openings upper layer film, is parked in lower floor SiO
2on;
4. wet etching lower floor SiO
2.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method that germanium silicium HBT emitter lithography alignment accuracy is optimized, and it can add strong optical contrast greatly, avoids because the signal strength signal intensity optical alignment precision measure error that causes of deficiency and instability.
In order to solve above technical problem, the invention provides a kind of method that germanium silicium HBT emitter lithography alignment accuracy is optimized, emitter accurately measures mark OVLmark to the photoetching alignment mark of emitter openings layer and overlay and is all placed on place, and technological process comprises:
Active area chemical wet etching produces emitter accurately measures mark OVL mark substrate zone to emitter openings alignment mark and overlay;
SiO
2deposition and CMP produce emitter and emitter openings alignment mark and overlay are accurately measured to the SiO identifying OVLmark
2the substrate that material is formed;
Before base BP is etched in emitter openings, and emitter openings rete be deposited on base BP etch after;
The wet etching added after emitter openings chemical wet etching.
Beneficial effect of the present invention is: greatly can add strong optical contrast, avoids because the signal strength signal intensity optical alignment precision measure error that causes of deficiency and instability.
Preferably, the deielectric-coating of emitter openings consists of SiO
2+ other materials rete, as monofilms such as SiN, Poly, SiON, SIC, or the combination of multilayer film.
Preferably, top dielectric film and layer dielectric film Selection radio >10 in wet etching.
Preferably, the rete gross thickness < of emitter openings
Preferably, substrate Si O
2the thickness in district is
be preferably
Preferably, wet etching is SiO
2etching, the main HF that uses is for etching liquid.
Preferably, the etch amount > of wet etching
or ensure the rear emitter openings top-to-bottom thickness G reatT.GreaT.GT of etching
Preferably, the etch amount of wet etching is for being etched directly into Si.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is the Si/Ge HBT schematic diagram of existing T-shaped emitter structure;
Fig. 2 a is that conventional lithography alignment mark/overlay accurately measures mark OVL mark vertical structure schematic diagram;
Fig. 2 b is that the first photoetching alignment mark/overlay described in the embodiment of the present invention accurately measures mark OVLmark vertical structure schematic diagram;
Fig. 2 c is that the second photoetching alignment mark/overlay described in the embodiment of the present invention accurately measures mark OVLmark vertical structure schematic diagram;
Fig. 3 a is that conventional lithography alignment mark/overlay accurately measures mark OVL mark formation process schematic flow sheet;
Fig. 3 b is that photoetching alignment mark/overlay of the present invention accurately measures mark OVL mark formation process schematic flow sheet.
Description of reference numerals:
1Si substrate, 2 places, 3 deep trench, 4 buried regions, 5 collector electrodes, 6 collector electrode draw-out areas, base in 7A, outer base area, 7B outer base area 1,7C 2,8 emitter openings deielectric-coating lower floor, 9 emitter openings deielectric-coating upper stratas, 10 emitters.
Embodiment
Its photoetching alignment mark of method of germanium silicium HBT emitter lithography alignment accuracy of the present invention optimization and preparation technology's flow process of OVLmark are:
1. chemical wet etching silicon substrate produces groove, and its degree of depth is
be preferably
2. fill SiO in the trench
2and the SiO in non-groove district is removed in planarization
2;
3. (SiO2+SiN or SiO2+Poly, thickness is SiO2 to deposit resilient coating SC between BP and substrate
upper layer of material
), etching SC layer, open device area, litho pattern district produces two block graphicses of etching and non-etching.
4. deposit BP rete (Si/Ge), and etch, its dry etching barrier layer SiO
2, until SiO
2stop, residual Si O
2for
5. deposit emitter openings film on a silicon substrate (active area), its lower floor is SiO
2, be generally
be preferably
upper strata rete SiN, the monofilms such as Poly, SiON, SIC, or the combination of multilayer film.It is characterized by the wet etching of HF and SiO
2selection radio >10.
6. photoetching;
7. dry etching emitter openings upper layer film, is parked in lower floor SiO
2on;
8. wet etching lower floor SiO
2, the etch amount > of wet etching
or ensure figure and substrate table jump >
Step 1,2 can with traditional active area, and place formation process combines to reduce process costs.Wherein step 6 can form middle wet etching over etching technique with the emitter openings of traditional handicraft and combines, and to save process costs, the photoetching now in step 4 comprises device area and alignment mark/OVLmark region.If but consider that wet etching lateral etching amount is on the impact of device.Then be revised as:
4. photoetching;
5. dry etching emitter openings upper layer film, is parked in lower floor SiO
2on;
6. wet etching lower floor SiO
2, etch amount <
7. photoetching is exposed photoetching alignment mark and overlay and is accurately measured and identify OVL mark;
8. wet etching substrate.The etch amount > of wet etching
or ensure the rear emitter openings of etching
Top-to-bottom thickness G reatT.GreaT.GT
Because step 8 etches not on earth, the heterogeneity of processing procedure may cause measures instability, and therefore the etch amount of wet etching also can be etched directly into Si.
The present invention is not limited to execution mode discussed above.Above the description of embodiment is intended to describe and the technical scheme that the present invention relates to being described.Based on the present invention enlightenment apparent conversion or substitute also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, can apply numerous embodiments of the present invention and multiple alternative to reach object of the present invention to make those of ordinary skill in the art.
Claims (9)
1. a method for germanium silicium HBT emitter lithography alignment accuracy optimization, is characterized by, and emitter accurately measures mark OVL mark to the photoetching alignment mark of emitter openings layer and overlay and is all placed on place, and technological process comprises:
Active area chemical wet etching produces emitter accurately measures mark OVL mark substrate zone to emitter openings alignment mark and overlay;
SiO
2deposition and chemico-mechanical polishing CMP produce emitter and emitter openings alignment mark and overlay are accurately measured to the SiO identifying OVL mark
2the substrate that material is formed;
Before base is etched in emitter openings, and emitter openings rete be deposited on base etching after;
The wet etching added after emitter openings chemical wet etching.
2. the method for germanium silicium HBT emitter lithography alignment accuracy optimization according to claim 1, it is characterized by, the deielectric-coating of emitter openings consists of SiN, polysilicon, SiON or SiC monofilm, or the combination of multilayer film.
3. the method for germanium silicium HBT emitter lithography alignment accuracy optimization according to claim 1 and 2, is characterized by, top dielectric film and layer dielectric film Selection radio >10 in wet etching.
4. the method for germanium silicium HBT emitter lithography alignment accuracy optimization according to claim 1 and 2, is characterized by, the rete gross thickness of emitter openings
5. the method for germanium silicium HBT emitter lithography alignment accuracy optimization according to claim 1, is characterized by, substrate Si O
2the thickness in district is
6. the method for germanium silicium HBT emitter lithography alignment accuracy optimization according to claim 5, is characterized by, substrate Si O
2the thickness in district is
7. the method for germanium silicium HBT emitter lithography alignment accuracy optimization according to claim 1, it is characterized by, wet etching is SiO
2etching, the main HF that uses is for etching liquid.
8. the method for germanium silicium HBT emitter lithography alignment accuracy optimization according to claim 1, is characterized by, the etch amount of wet etching
or ensure the rear emitter openings top-to-bottom thickness of etching
9. the method for germanium silicium HBT emitter lithography alignment accuracy optimization according to claim 1, it is characterized by, the etch amount of wet etching is for being etched directly into Si.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107895696A (en) * | 2017-11-03 | 2018-04-10 | 厦门市三安集成电路有限公司 | A kind of high-precision HBT preparation technologies |
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| CN102129178A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Photoetching mark structure for SiGeC device |
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|---|---|---|---|---|
| US6940149B1 (en) * | 2004-03-11 | 2005-09-06 | International Business Machines Corporation | Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base |
| US7645666B2 (en) * | 2007-07-23 | 2010-01-12 | Infineon Technologies Ag | Method of making a semiconductor device |
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| CN101923296A (en) * | 2009-06-17 | 2010-12-22 | 上海华虹Nec电子有限公司 | Making method of photoetching fiducial mark in process of making NVM (Non-Volatile Memory) device |
| CN102034855A (en) * | 2009-09-29 | 2011-04-27 | 上海华虹Nec电子有限公司 | Silicon-germanium heterojunction bipolar transistor and manufacturing method thereof |
| CN102044560A (en) * | 2009-10-16 | 2011-05-04 | 上海华虹Nec电子有限公司 | Ultrahigh frequency silicon and germanium heterojunction bipolar transistor |
| CN102129178A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | Photoetching mark structure for SiGeC device |
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| CN107895696A (en) * | 2017-11-03 | 2018-04-10 | 厦门市三安集成电路有限公司 | A kind of high-precision HBT preparation technologies |
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