CN102931167A - Method for transmitting large driving current signal between stacked chips - Google Patents
Method for transmitting large driving current signal between stacked chips Download PDFInfo
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- CN102931167A CN102931167A CN2012104130880A CN201210413088A CN102931167A CN 102931167 A CN102931167 A CN 102931167A CN 2012104130880 A CN2012104130880 A CN 2012104130880A CN 201210413088 A CN201210413088 A CN 201210413088A CN 102931167 A CN102931167 A CN 102931167A
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- current signal
- stacked chips
- large current
- transmission
- driving current
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Abstract
The invention discloses a method for transmitting a large driving current signal between stacked chips. The method comprises the following steps of: choosing at least two interconnecting wires connected from up and down from the wires of the stacked chips, wherein the wires of the stacked chips are used for transmitting the large driving current signal; and simultaneously transmitting the large driving current signal on the interconnecting wires in parallel. The method provided by the invention lowers the transmission loss of the large driving current signal, and improves the current driving capability between the stacked chips.
Description
Technical field
The present invention relates to the stacked chips technical field, relate in particular to a kind of method that drives large current signal of between stacked chips, transmitting.
Background technology
Drive traditionally large current signal, if during with gold thread or copper cash wire bonding interconnect stack chip, because the cross-sectional area of gold thread generally is 0.7 square millimeter, the cross-sectional area of copper cash generally is 0.8 square millimeter, transmit large electric current with such line and can not produce very large voltage drop, be conducive to the transmission of large electric current.The silicon through hole connects (TSV, Through-Silicon-Via) interconnect technology is as an emerging technology, be widely used in the chip-stacked technology, but because the line diameter of TSV is followed minimum process, if in deep submicron process, use the large current signal of silicon through hole technical transmission, because the metal live width is very little, so that the resistance of line is very large, can produce very large voltage drop, not reach the effect of the large electric current of transmission, as shown in Figure 3.So the resistance value of TSV line will be very large, transmission will bring very large problem for the signal of the large electric current of those demand motives, causes driving force to descend, thereby the performance of chip has been reduced.
Summary of the invention
The present invention has overcome can't effectively transmit the defective that drives large current signal in the stacked chips in the background technology, proposed a kind of method that drives large current signal of transmitting between stacked chips.
The present invention proposes a kind of method that drives large current signal of between stacked chips, transmitting, comprising:
Step 1: drive in the transmission of described stacked chips between the wire of large current signal and select at least two interconnection lines to connect up and down;
Step 2: the large current signal of described driving is parallel transmission on described interconnection line simultaneously;
Wherein, the drive current of the large current signal of described driving is more than the 10mA.
Wherein, the interconnection line between the described stacked chips is that the silicon through hole connects interconnection line.
The present invention carries out the multidiameter delay transmission by driving large current signal between stacked chips, effectively reduce and drive the loss that large current signal transmits at the interconnection line of stacked chips, improved the driving force when driving large current signal and between stacked chips, transmitting, Effective Raise the performance of chip.
Description of drawings
Fig. 1 is the method that drives large current signal is transmitted in the present invention between stacked chips flow chart.
Fig. 2 is the schematic diagram that transmission drives large current signal among the present invention.
Fig. 3 is the schematic diagram that transmission drives large current signal in the background technology.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail.Implement process of the present invention, condition, experimental technique etc., except the following content of mentioning specially, be universal knowledege and the common practise of this area, the present invention is not particularly limited content.
As shown in Figure 1, a kind of method that drives large current signal of transmitting between stacked chips of the present invention comprises:
Step 1: drive in the transmission of stacked chips between the wire of large current signal and select at least two interconnection lines to connect up and down;
Step 2: drive simultaneously parallel transmission on interconnection line of large current signal.
The drive current that drives large current signal among the present invention is more than the 10mA.
It is that the silicon through hole connects interconnection line that the interconnection line that adopts when driving large current signal is transmitted in the present invention.
Embodiment:
As shown in Figure 1, when the silicon through hole connects the large current signal of (Through-Silicon-Via) interconnection line transmission driving, drive large current signal and pass through a plurality of interconnecting silicon through holes lines at stacked on top chip chamber parallel transmission, so that the electric current that flows through of chip chamber increases up and down, reduced to drive the loss of large current signal in transmission course, improved drive efficiency, thereby can realize that connecting the transmission of (Through-Silicon-Via) interconnection line at the silicon through hole drives large current signal.
As shown in Figure 2, selecting four silicon through holes to connect interconnection lines between the wire of the large current signal of transmission driving between the stacked on top chip in the present embodiment connects.The large current signal of driving that can drive the above large electric current of 10mA connects the interconnection line parallel transmission by four silicon through holes.Because transmission course adopts the mode of parallel transmission, the loss that drives large current signal reduces, in receiving the upper strata chip that drives large current signal, the large current signal of driving of the parallel transmission of four silicon through holes connections of wire integration interconnection lines of the large current signal of transmission driving is used for the electronic component power supply to the upper strata chip.Compared with prior art, the efficiency of transmission that drives large electric current in the present embodiment improves 3 times at least.
Protection content of the present invention is not limited to above embodiment.Under the spirit and scope that do not deviate from inventive concept, those skilled in the art can to variation and advantage all be included in the present invention, and take appending claims as protection range.
Claims (3)
1. the method for the large current signal of transmission driving between stacked chips is characterized in that, comprising:
Step 1: drive in the transmission of described stacked chips between the wire of large current signal and select at least two interconnection lines to connect up and down;
Step 2: the large current signal of described driving is parallel transmission on described interconnection line simultaneously.
2. the method that drives large current signal of transmitting between stacked chips as claimed in claim 1 is characterized in that, the drive current of the large current signal of described driving is more than the 10mA.
3. the method that drives large current signal of transmitting between stacked chips as claimed in claim 1 is characterized in that, the interconnection line between the described stacked chips is that the silicon through hole connects interconnection line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104130880A CN102931167A (en) | 2012-10-25 | 2012-10-25 | Method for transmitting large driving current signal between stacked chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104130880A CN102931167A (en) | 2012-10-25 | 2012-10-25 | Method for transmitting large driving current signal between stacked chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102931167A true CN102931167A (en) | 2013-02-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012104130880A Pending CN102931167A (en) | 2012-10-25 | 2012-10-25 | Method for transmitting large driving current signal between stacked chips |
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| CN (1) | CN102931167A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10381330B2 (en) | 2017-03-28 | 2019-08-13 | Silicon Storage Technology, Inc. | Sacrificial alignment ring and self-soldering vias for wafer bonding |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1438703A (en) * | 2002-02-12 | 2003-08-27 | 日立超大规模集成电路系统株式会社 | Semiconductor integrated circuit device |
| CN101783334A (en) * | 2010-02-08 | 2010-07-21 | 江阴长电先进封装有限公司 | Packaging carrier plate structure and realizing method thereof |
| US20120139103A1 (en) * | 2010-12-03 | 2012-06-07 | Xilinx, Inc. | Semiconductor device with stacked power converter |
-
2012
- 2012-10-25 CN CN2012104130880A patent/CN102931167A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1438703A (en) * | 2002-02-12 | 2003-08-27 | 日立超大规模集成电路系统株式会社 | Semiconductor integrated circuit device |
| CN101783334A (en) * | 2010-02-08 | 2010-07-21 | 江阴长电先进封装有限公司 | Packaging carrier plate structure and realizing method thereof |
| US20120139103A1 (en) * | 2010-12-03 | 2012-06-07 | Xilinx, Inc. | Semiconductor device with stacked power converter |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10381330B2 (en) | 2017-03-28 | 2019-08-13 | Silicon Storage Technology, Inc. | Sacrificial alignment ring and self-soldering vias for wafer bonding |
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Application publication date: 20130213 |