CN102931098B - Chip packaging method - Google Patents
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- CN102931098B CN102931098B CN201210444096.1A CN201210444096A CN102931098B CN 102931098 B CN102931098 B CN 102931098B CN 201210444096 A CN201210444096 A CN 201210444096A CN 102931098 B CN102931098 B CN 102931098B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Disclosed is a chip packaging method. The method comprises providing a semiconductor substrate which is provided with a metal pad and an insulation layer, wherein the insulation layer is provided with an opening exposing the metal pad; forming an under-ball metal electrode on the metal pad, wherein the metal electrode is provided with an electrode body portion and an electrode tail portion, the electrode body portion is arranged at the bottom of the under-ball metal electrode and connected with the metal pad, and the electrode tail portion is arranged at the top of the under-ball metal electrode; and forming a solder ball on the surface of the under-ball metal electrode. The chip packaging method improves the product reliability and is low in manufacture cost.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of chip packaging method.
Background technology
In conventional art, the connection of IC chip and external circuit is realized by the mode of metal lead wire bonding (WireBonding).Along with the expansion with footprint of reducing of IC chip feature sizes, Wire Bonding Technology is no longer applicable.Crystal wafer chip dimension encapsulation (Wafer Level Chip ScalePackaging, WLCSP) technology is that after carrying out packaging and testing to full wafer wafer, cutting obtains the technology of single finished product chip again, the chip size after encapsulation and nude film completely the same.Crystal wafer chip dimension encapsulation technology has thoroughly overturned the pattern of conventional package as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier), organic leadless chip carrier (Organic Leadless Chip Carrier), has complied with that market is day by day light, little, short to microelectronic product, thinning and low priceization requirement.Chip size after the encapsulation of crystal wafer chip dimension encapsulation technology reaches highly microminiaturized, and chip cost significantly reduces along with the reduction of chip size and the increase of wafer size.Crystal wafer chip dimension encapsulation technology be IC can be designed, wafer manufacture, packaging and testing, the technology that integrates, be the focus in current encapsulation field and the trend of future development.
Prior art discloses a kind of crystal wafer chip dimension encapsulation technology, please refer to Fig. 1, Fig. 1 is the generalized section of prior art wafer level chip scale package structure, comprising: Semiconductor substrate 101; Be positioned at the metal pad 103 of described Semiconductor substrate 101 inside; Be positioned at the insulating barrier 102 on described Semiconductor substrate 101 surface, described insulating barrier 102 has the opening exposing described metal pad 103; Be positioned at described opening and metal electrode 104 under the ball of metal pad 103 described in cover part; Be positioned at the soldered ball 105 on metal electrode 104 under described ball, the upper surface of metal electrode 104 under described soldered ball 105 ball covering on soil.
In prior art, soldered ball 105 is positioned under ball on metal electrode 104, and soldered ball 105 contacts with the upper surface of metal electrode under ball 104, and contact area is little, the poor adhesive force under soldered ball 105 and ball between metal electrode 104.In addition, under ball, the material of metal electrode 104 is generally copper, the material of soldered ball 105 is generally tin, when copper electrode surface forms tin ball, tin atom can diffuse in copper electrode and go, and copper atom also can diffuse in tin ball simultaneously, forms interface alloy compound (IMC:Intermetallic Compound) and cavity altogether, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.
The chip packaging method poor reliability of prior art.
The method for filling of other related chips can also be the Chinese invention patent application of CN101211791 with reference to publication number, it discloses a kind of wafer-grade chip packaging process and chip-packaging structure.
Summary of the invention
The problem that the present invention solves is poor adhesive force between metal electrode under prior art soldered ball and ball, poor reliability.
For solving the problem, the invention provides a kind of chip packaging method, comprising: providing Semiconductor substrate, described Semiconductor substrate has metal pad and insulating barrier, described insulating barrier has the opening exposing described metal pad; Described metal pad is formed metal electrode under ball, under described ball, metal electrode has electrode body and electrode afterbody, described electrode body portion to be positioned under described ball bottom metal electrode and to connect with described metal pad, and described electrode afterbody is positioned at metal electrode top under described ball; Under described ball, surface of metal electrode forms soldered ball.
Optionally, the material of described metal pad is gold, copper, aluminium or silver.
Optionally, described metal pad is again distributed pad.
Optionally, forming the method for metal electrode under described ball is wire bonding (Wire Bonding), comprising: metal lead wire and metal pad bonding form electrode body; The metal lead wire starting the arc is to electrode tail height to be formed; Wire clamp cuts off metal lead wire, metal electrode under formation ball.
Optionally, described electrode tail height is 0.005 ~ 1.5 times of described electrode body height.
Optionally, under described ball, the material of metal electrode is the one in gold, copper, silver, or under described ball, the material of metal electrode is the alloy containing gold, copper or silver.
Optionally, described metal pad to be formed under ball before metal electrode, be also included in the step that described metal pad surface forms transition metal layer.
Optionally, under described ball, surface of metal electrode is formed with cover layer, and described cover layer also covers the metal pad of metal electrode bottom periphery under described ball.
Optionally, described cover layer is the stacked structure of barrier layer and soakage layer, and described barrier layer is positioned at surface of metal electrode under described ball, and described soakage layer is positioned at described barrier layer surface.
Optionally, the material of described barrier layer is nickel.
Optionally, the thickness of described barrier layer is 0.05 μm to 5 μm.
Optionally, the formation method of described barrier layer is chemical plating.
Optionally, the material of described soakage layer is the one in tin, gold, silver, or the material of described soakage layer is alloy that is stanniferous, golden or silver.
Optionally, the thickness of described soakage layer is 0.05 μm to 10 μm.
Optionally, the formation method of described soakage layer is chemical plating.
Optionally, described soldered ball is formed by typography.
Optionally, the material of described soldered ball is tin or ashbury metal.
Compared with prior art, the present invention has the following advantages:
Under described ball, metal electrode has electrode body and electrode afterbody, and described electrode body portion to be positioned under described ball bottom metal electrode and to connect with described metal pad, and described electrode afterbody is positioned at metal electrode top under described ball.Forming the method for metal electrode under described ball is wire bonding, comprising: metal lead wire and metal pad bonding form electrode body; The metal lead wire starting the arc is to electrode tail height to be formed; Wire clamp cuts off metal lead wire, metal electrode under formation ball.After follow-up formation soldered ball, described electrode afterbody embeds in soldered ball, increases the contact area of metal electrode and soldered ball under ball, therefore the Adhesion enhancement of metal electrode and soldered ball under ball, make soldered ball when by External Force Acting, more difficultly to come off from surface of metal electrode ball.The method adopting wire bonding method to form metal electrode under ball in addition and prior art adopt compared with the method for electroplating and forming metal electrode under ball, and flow process is short, low cost of manufacture.
Under described ball, surface of metal electrode forms cover layer, and described cover layer is the stacked structure of barrier layer and soakage layer, and described barrier layer is positioned at surface of metal electrode under described ball, and described soakage layer is positioned at described barrier layer surface.In prior art, soldered ball is located immediately under ball on metal electrode, and can form interface alloy compound and cavity altogether by the diffusion of atom between metal electrode and soldered ball under ball, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.In the present invention, under ball, surface of metal electrode first forms barrier layer, the material of described barrier layer is nickel, barrier layer and soldered ball form the common compound of interface alloy and want slow a lot of compared with metal electrode under ball, can, as the barrier layer under ball between metal electrode and soldered ball, prevent from forming interface alloy compound and cavity altogether.And be easily oxidized due to barrier layer, further form on barrier layer surface the oxidation that soakage layer prevents barrier layer, in addition, the material of the soldered ball of soakage layer and follow-up formation infiltrates, adhesive force is better, the material of described soakage layer is the one in tin, gold, silver, or the material of described soakage layer is alloy that is stanniferous, golden or silver.Compared with prior art, under ball, surface of metal electrode forms cover layer and improves interface alloy compound problem altogether, improves the reliability of chip package.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of prior art chip-packaging structure;
Fig. 2 is the flow chart of the chip packaging method that first embodiment of the invention provides;
Fig. 3 to Fig. 7 is the cross-sectional view of the chip package process of first embodiment of the invention;
Fig. 8 and Fig. 9 is the cross-sectional view of the chip package procedure division step of second embodiment of the invention;
Figure 10 is the chip packaging method flow chart that third embodiment of the invention provides;
Figure 11 and Figure 12 is the cross-sectional view of the chip package procedure division step of third embodiment of the invention.
Embodiment
From background technology, in prior art, soldered ball is located immediately under ball on metal electrode, and under soldered ball and ball, the contact area of metal electrode is little, poor adhesive force.In addition, under ball, the material of metal electrode is generally copper, the material of soldered ball is generally tin, when copper electrode surface forms tin ball, tin atom can diffuse in copper electrode and go, and copper atom also can diffuse in tin ball simultaneously, forms interface alloy compound and cavity altogether, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.Prior art forms the method for metal electrode under ball for plating, and need the technique of photoetching to define position and the shape of metal electrode under ball, complex process, cost is high.
The present inventor, through creative work, proposes a kind of new chip packaging method, comprising: provide Semiconductor substrate, described Semiconductor substrate has metal pad and insulating barrier, and described insulating barrier has the opening exposing described metal pad; Described metal pad is formed metal electrode under ball, under described ball, metal electrode has electrode body and electrode afterbody, described electrode body portion to be positioned under described ball bottom metal electrode and to connect with described metal pad, and described electrode afterbody is positioned at metal electrode top under described ball; Under described ball, surface of metal electrode forms soldered ball.
Describe three specific embodiments provided by the invention below in conjunction with Figure of description, above-mentioned object and advantage of the present invention will clearly.It should be noted that, provide the object of these accompanying drawings to be contribute to understanding embodiments of the invention, and should not be construed as and limit improperly of the present invention.For the purpose of clearer, size shown in figure not drawn on scale, may make and amplify, to reduce or other change.A lot of detail has been set forth to fully understand the present invention in description below.But the present invention can implement to be much different from other modes described here, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
first embodiment
Please refer to Fig. 2, Fig. 2 is the flow chart of first embodiment of the invention, comprising:
Step S101, provides Semiconductor substrate, described Semiconductor substrate has metal pad and insulating barrier, and described insulating barrier has the opening exposing described metal pad;
Step S102, described metal pad is formed metal electrode under ball, under described ball, metal electrode has electrode body and electrode afterbody, and described electrode body portion to be positioned under described ball bottom metal electrode and to connect with described metal pad, and described electrode afterbody is positioned at metal electrode top under described ball;
Step S103, under described ball, surface of metal electrode forms cover layer;
Step S104, is being formed with surface of metal electrode formation soldered ball under tectal ball.
First, please refer to Fig. 3, provide Semiconductor substrate 201, described Semiconductor substrate 201 has metal pad 203 and insulating barrier 202, described insulating barrier 202 has the opening exposing described metal pad 203.
Described Semiconductor substrate 201 can be monocrystalline silicon, SOI(silicon-on-insulator), SiGe or III-V wafer, described Semiconductor substrate 201 comprises one deck or some layers of dielectric layer of being positioned at its inside and surface, and described Semiconductor substrate 201 can also comprise making semiconductor device thereon, metal interconnected and other semiconductor structures.Described insulating barrier 202 comprises passivation layer and polymeric layer (not shown), described passivation layer exposes the opening of described metal pad 203 for the protection of metal pad 203, electric isolation and formation, and the material of described passivation layer can be silica, silicon nitride or low-K material; Described polymeric layer is positioned on described passivation layer, described polymeric layer has the opening exposing described metal pad 203, and the material of described polymer can be polyimides (Polyimide), epoxy resin (Epoxy) or benzocyclobutane olefine resin (Benzocyclobutene).Described metal pad 203 is the top layer interconnecting metal electrode of described Semiconductor substrate 201, and the material of described metal pad 203 can be gold, copper, aluminium or silver.
In one embodiment, described Semiconductor substrate 201 is monocrystalline silicon, and described Semiconductor substrate 201 further comprises making semiconductor device thereon, metal interconnection and other semiconductor structures.Described insulating barrier 202 comprises passivation layer that material is silica and material is the polymeric layer of polyimides, described insulating barrier 202 has the opening of exposing metal pad 203, described metal pad 203 is the interconnected metal electrode of top layer of described Semiconductor substrate 201, and the material of described metal pad 203 is copper.
Then, please refer to Fig. 4, described metal pad 203 is formed metal electrode 204 under ball, under described ball, metal electrode 204 has electrode body 204a and electrode afterbody 204b, described electrode body 204a to be positioned under described ball bottom metal electrode 204 and to connect with described metal pad 203, and described electrode afterbody 204b is positioned at metal electrode 204 top under described ball.Wherein, the soldered ball of described electrode body 204a connection metal pad 203 and follow-up formation also supports described electrode afterbody 204b, described electrode afterbody 204b embeds in the soldered ball of follow-up formation, increase the contact area of metal electrode 204 and soldered ball under ball, therefore the Adhesion enhancement of metal electrode 204 and soldered ball under ball, make soldered ball when by External Force Acting, more difficultly to come off from metal electrode ball 204 surface.
Forming the method for metal electrode 204 under described ball is wire bonding (Wire Bonding), comprising: metal lead wire and metal pad bonding form electrode body 204a; The metal lead wire starting the arc is to electrode afterbody 204b height to be formed; Wire clamp cuts off metal lead wire, metal electrode 204 under formation ball.
An embodiment, form the technique of metal electrode 204 under described ball to be specially: metal lead wire arrives metal pad 203 top by bonding head, utilize oxyhydrogen flame or electrical discharge system to produce electric spark to go between with deposite metal, under capillary effect, motlten metal solidifies and forms spherical (bulb diameter is generally 1.5 times of metal lead wire diameter to 4 times), fall bonding head, at suitable pressure, temperature, in kinetic energy and time, Metal Ball is pressed on metal pad 203, in the process, pressure is applied to Metal Ball by bonding head, promote that phase counterdiffusion between plastic deformation and atom occurs for lead-in wire metal and metal pad 203 simultaneously, form electrode body 204a, then, bonding head lifts, and the metal lead wire starting the arc, to certain height (electrode afterbody 204b height to be formed), utilizes bonding wire clamp to cut off metal lead wire, metal lead wire and electrode afterbody 204b on electrode body 204a, metal electrode 204 under formation ball.It should be noted that, wire bonding is usually used in the technique connected between semiconductor packaged inner chip and external terminal and chip, and the present inventor is by improving lead key closing process, be applied in the formation process of metal electrode 204 under ball, after can bonding head being adopted to lift while formation electrode body 204a, the metal lead wire starting the arc forms electrode afterbody 204b, technique is simple, and formation efficiency is high.
Under described ball, the material of metal electrode 204 is the one in gold, copper, silver, or under described ball, the material of metal electrode 204 is the alloy containing gold, copper or silver.The height of described electrode afterbody 204b is 0.005 ~ 1.5 times of described electrode body 204a height, when electrode afterbody 204b height lower than electrode body 204a height 0.005 times time, electrode afterbody 204b embeds the limited length of the soldered ball of follow-up formation, limited to the Adhesion enhancement of metal electrode under ball 204 and soldered ball; And when 1.5 times of height higher than electrode body 204a of the height of electrode afterbody 204b, because electrode afterbody 204b is formed by the starting the arc after wire bonding, electrode afterbody 204b is thinner with electrode body 204a phase diameter group, and metal quality is softer, easy bending in manufacture process also affects the shape of soldered ball, rate of finished products reduces, and is unfavorable for down chip package.
In one embodiment, under described ball, the material of metal electrode 204 is copper, and the height of described electrode afterbody 204b is identical with the height of described electrode body 204a.
Then, please refer to Fig. 5 and Fig. 6, under described ball, metal electrode 204 surface forms cover layer, and described cover layer also covers the metal pad 203 of metal electrode 204 bottom periphery under described ball.Described cover layer is the stacked structure of barrier layer 205 and soakage layer 206, and under described barrier layer 205 is positioned at described ball, metal electrode 204 is surperficial, and described soakage layer 206 is positioned at described barrier layer 205 surface.
Fig. 5 is the cross-sectional view that metal electrode 204 surface forms barrier layer 205 under described ball.The material of described barrier layer 205 is nickel, compared with metal electrode under ball 204 barrier layer 205 and soldered ball is formed interface alloy altogether compound want slowly a lot, can, as the barrier layer between metal electrode under ball 204 and soldered ball, prevent from forming interface alloy compound and cavity altogether.Interface alloy altogether compound and cavity can affect mechanical strength and the life-span of solder joint, so form barrier layer effectively can improve interface alloy compound problem altogether, improves the reliability of chip package.The formation method of described barrier layer 205 is chemical plating.Chemical plating, is also called electroless plating, and it is in cold situation, and utilize redox reaction to obtain the method for the coat of metal on plating piece surface, institute forms coating evenly, and chemical plating plant simply, do not need power supply and anode.The thickness of described barrier layer 205 is 0.05 μm to 5 μm, and the thickness of described barrier layer 205 is relevant with the technique of chip package process, and when the technological temperature of chip package process is lower, the thickness of described barrier layer 205 can reduce.
In one embodiment, first metal electrode under ball 204 is processed before chemical plating, remove the oxide-film on its surface, to reduce contact resistance; Then under ball, metal electrode 204 surface chemical plating forms nickel dam, and the thickness of described nickel dam is 0.1 μm to 3 μm.
Fig. 6 is the cross-sectional view forming soakage layer 206 on described barrier layer 205 surface.The material of described barrier layer 205 is generally nickel, nickel is easily oxidized, interfacial resistivity is caused to increase, so further form soakage layer 206 to prevent the oxidation of barrier layer 205 on described barrier layer 205 surface, in addition, described soakage layer 206 infiltrates with the material of the soldered ball of follow-up formation, and adhesive force is better.The material of described soakage layer 206 is the one in tin, gold, silver, or the material of described soakage layer 206 is alloy that is stanniferous, golden or silver.The formation method of described soakage layer 206 is chemical plating.The thickness of described soakage layer 206 is 0.05 μm to 10 μm, and the thickness of described soakage layer 206 is also relevant with the technique of chip package.
In one embodiment, described soakage layer 206 is tin layers, and tin layers is not easy oxidized in atmosphere, and infiltrates with the soldered ball material of follow-up formation, and adhesive force is better, and the formation method of described tin layers is chemical plating, and the thickness of described tin layers is 0.1 μm to 5 μm.
Then, please refer to Fig. 7, be formed with formation soldered ball 207 in metal electrode 204 surface under tectal ball.Described soldered ball 207 is formed by typography, and the material of described soldered ball 207 is tin or ashbury metal.Forming the concrete technology of soldered ball 207 is: be coated on by web plate by solder and be formed under tectal ball on metal electrode 204, then carry out high temperature reflux, under surface tension effects, make described solder change soldered ball 207 into.
second embodiment
The present embodiment is compared with the first embodiment, and difference is: described metal pad is again distributed pad (RDL).The formation method of described distributed pad is again well known to those skilled in the art, and does not repeat them here.
Please refer to Fig. 8, provide Semiconductor substrate 301, described Semiconductor substrate 301 comprises: the metal electrode 308 being positioned at described Semiconductor substrate 301; Be positioned at described Semiconductor substrate 301 and the first insulating barrier 309 of metal electrode 308 described in cover part, described first insulating barrier 309 has the first opening exposing described metal electrode 308; Cover the sidewall of described first opening and the transition metal layer 310 of basal surface, described transition metal layer 310 forms the second opening along described first open surfaces; Be positioned on transition metal layer 310, and fill the metal pad 303 of described second opening; Be positioned at the second insulating barrier 302 on described metal pad 303, described second insulating barrier 302 has the 3rd opening exposing described metal pad 303.
Metal pad 303 described in the present embodiment is again distributed pad (RDL).Described distributed pad is again formed by increasing the first insulating barrier 309, transition metal layer 310 and the second insulating barrier 302 at chip surface, can to arrange as the position of distributed pad again according to the design rule of packaging technology in the position of the metal electrode 308 in Semiconductor substrate 301 by again.Distributed pad can reduce chip package size greatly again, reaches the demand of high-density packages, and improves speed and the stability of transfer of data.
Please refer to Fig. 9, described metal pad 303 is formed metal electrode 304 under ball, under described ball, metal electrode 304 has electrode body and electrode afterbody, described electrode body portion to be positioned under described ball bottom metal electrode 304 and to connect with described metal pad 303, and described electrode afterbody is positioned at metal electrode 304 top under described ball; Under described ball, metal electrode 304 surface forms cover layer, described cover layer also covers the metal pad 303 of metal electrode 304 bottom periphery under described ball, described cover layer is the stacked structure of barrier layer 305 and soakage layer 306, under described barrier layer 305 is positioned at described ball, metal electrode 304 is surperficial, and described soakage layer 306 is positioned at described barrier layer 305 surface; Be formed with formation soldered ball 307 in metal electrode 304 surface under tectal ball.
Above-mentioned concrete forming process and associated description please refer to the appropriate section of the first embodiment, do not repeat them here.
3rd embodiment
Figure 10 is the schematic flow sheet of third embodiment of the invention, Figure 11 and Figure 12 is the schematic diagram of part steps in above-mentioned flow process, is described in detail below in conjunction with Figure 10.
Please refer to Figure 10, Figure 10 is the flow chart of third embodiment of the invention, comprising:
Step S201, provides Semiconductor substrate, described Semiconductor substrate has metal pad and insulating barrier, and described insulating barrier has the opening exposing described metal pad;
Step S203, forms transition metal layer on described metal pad surface;
Step S203, described metal pad is formed metal electrode under ball, under described ball, metal electrode has electrode body and electrode afterbody, and described electrode body portion to be positioned under described ball bottom metal electrode and to connect with described metal pad, and described electrode afterbody is positioned at metal electrode top under described ball;
Step S204, under described ball, surface of metal electrode forms cover layer;
Step S205, is being formed with surface of metal electrode formation soldered ball under tectal ball.
Figure 10 and Fig. 2 compares, and the difference of the present embodiment and the first embodiment is: to be formed under ball before metal electrode on described metal pad, be also included in the step that described metal pad surface forms transition metal layer.
There is provided Semiconductor substrate 401, described Semiconductor substrate 401 has metal pad 403 and insulating barrier 402, described insulating barrier 402 has the opening exposing described metal pad 403.In the present embodiment, described metal pad 403 can be the top layer interconnecting metal electrode of Semiconductor substrate 401, also can be again distributed pad.
Please refer to Figure 11, form transition metal layer 408 on described metal pad 403 surface.Described transition metal layer 408 plays non-proliferation, increases the effect of adhesion and protection metal pad 403.The technique forming described transition metal layer 408 can be physical vapour deposition (PVD), chemical vapour deposition (CVD), electrochemical deposition and electroplating technology.Described transition metal layer 408 can be NiPdAu layer, Ag layer, the lamination of one or more in Ti layer, Ta layer, TiN layer, TaN layer, Cu layer or Cu alloy-layer.The thickness of described transition metal layer 408 is 0.1 μm to 3 μm.Choosing of described transition metal layer 408 thickness, relevant with the process of chip package, the thickness of the less described transition metal layer 408 of process of chip package is less.
In one embodiment, the material of described transition metal layer 408 is TiN, and the thickness of described transition metal layer 408 is 0.2 μm to 1.5 μm.
Please refer to Figure 12, the described metal pad 403 being formed with transition metal layer 408 is formed metal electrode 404 under ball, under described ball, metal electrode 404 has electrode body and electrode afterbody, described electrode body portion to be positioned under described ball bottom metal electrode 404 and to connect with described distributed pad 403 again, and described electrode afterbody is positioned at metal electrode 404 top under described ball; Under described ball, metal electrode 404 surface forms cover layer, described cover layer is the stacked structure of barrier layer 405 and soakage layer 406, under described barrier layer 405 is positioned at described ball, metal electrode 404 is surperficial, and described soakage layer 406 is positioned at described barrier layer 405 surface; Be formed with formation soldered ball 407 in metal electrode 404 surface under tectal ball.
Above-mentioned concrete forming process and associated description please refer to the appropriate section of the first embodiment, do not repeat them here.
In sum, compared with prior art, the present invention has the following advantages:
Metal electrode under the technique formation ball of use wire bonding, under described ball, metal electrode has electrode body and electrode afterbody.In prior art, soldered ball is located immediately at surface of metal electrode under ball, under soldered ball and ball, the contact area of metal electrode is limited, and in the present invention, after under follow-up ball, surface of metal electrode forms soldered ball, described electrode afterbody embeds in soldered ball, increase the contact area of metal electrode and soldered ball under ball, therefore the Adhesion enhancement of metal electrode and soldered ball under ball, makes soldered ball when by External Force Acting, more difficultly comes off from surface of metal electrode ball.Wire bonding is usually used in the technique connected between semiconductor packaged inner chip and external terminal and chip, and the present inventor is by improving lead key closing process, be applied in the formation process of metal electrode under ball, after can bonding head being adopted to lift while formation electrode body, the metal lead wire starting the arc forms electrode afterbody, technique is simple, and formation efficiency is high.
Under described ball, surface of metal electrode forms cover layer, and described cover layer is the stacked structure of barrier layer and soakage layer.In prior art, soldered ball is located immediately under ball on metal electrode, and can form interface alloy compound and cavity altogether by the diffusion of atom between metal electrode and soldered ball under ball, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.In the present invention, under ball, surface of metal electrode first forms barrier layer, the material of described barrier layer is nickel, barrier layer and soldered ball form the common compound of interface alloy and want slow a lot of compared with metal electrode under ball, can, as the barrier layer under ball between metal electrode and soldered ball, prevent from forming interface alloy compound and cavity altogether.And be easily oxidized due to barrier layer, further form on barrier layer surface the oxidation that soakage layer prevents barrier layer, in addition, the material of the soldered ball of soakage layer and follow-up formation infiltrates, adhesive force is better, the material of described soakage layer is the one in tin, gold, silver, or the material of described soakage layer is alloy that is stanniferous, golden or silver.Compared with prior art, under ball, surface of metal electrode forms cover layer and improves interface alloy compound problem altogether, improves the reliability of chip package.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (14)
1. a chip packaging method, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate has metal pad and insulating barrier, described insulating barrier has the opening exposing described metal pad;
Described metal pad is formed metal electrode under ball, under described ball, metal electrode has electrode body and electrode afterbody, described electrode body portion to be positioned under described ball bottom metal electrode and to connect with described metal pad, described electrode afterbody is positioned at metal electrode top under described ball, wherein, form the method for metal electrode under described ball to comprise: metal lead wire and metal pad bonding form electrode body; The described metal lead wire starting the arc is to electrode tail height to be formed; Wire clamp cuts off described metal lead wire, and form metal electrode under described ball, described electrode tail height is 0.005 ~ 1.5 times of described electrode body height;
Under described ball, surface of metal electrode is formed with cover layer, and described cover layer also covers the metal pad of metal electrode bottom periphery under described ball;
Soldered ball is formed in described cover surface.
2. chip packaging method as claimed in claim 1, it is characterized in that, the material of described metal pad is gold, copper, aluminium or silver.
3. chip packaging method as claimed in claim 1, it is characterized in that, described metal pad is again distributed pad.
4. chip packaging method as claimed in claim 1, it is characterized in that, under described ball, the material of metal electrode is the one in gold, copper, silver, or under described ball, the material of metal electrode is the alloy containing gold, copper or silver.
5. chip packaging method as claimed in claim 1, is characterized in that, described metal pad to be formed under ball before metal electrode, is also included in the step that described metal pad surface forms transition metal layer.
6. chip packaging method as claimed in claim 1, it is characterized in that, described cover layer is the stacked structure of barrier layer and soakage layer, and described barrier layer is positioned at surface of metal electrode under described ball, and described soakage layer is positioned at described barrier layer surface.
7. chip packaging method as claimed in claim 6, it is characterized in that, the material of described barrier layer is nickel.
8. chip packaging method as claimed in claim 6, it is characterized in that, the thickness of described barrier layer is 0.05 μm to 5 μm.
9. chip packaging method as claimed in claim 6, it is characterized in that, the formation method of described barrier layer is chemical plating.
10. chip packaging method as claimed in claim 6, it is characterized in that, the material of described soakage layer is the one in tin, gold, silver, or the material of described soakage layer is alloy that is stanniferous, golden or silver.
11. chip packaging methods as claimed in claim 6, is characterized in that, the thickness of described soakage layer is 0.05 μm to 10 μm.
12. chip packaging methods as claimed in claim 6, is characterized in that, the formation method of described soakage layer is chemical plating.
13. chip packaging methods as claimed in claim 1, it is characterized in that, described soldered ball is formed by typography.
14. chip packaging methods as claimed in claim 1, is characterized in that, the material of described soldered ball is tin or ashbury metal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210444096.1A CN102931098B (en) | 2012-11-08 | 2012-11-08 | Chip packaging method |
| US14/074,598 US9589815B2 (en) | 2012-11-08 | 2013-11-07 | Semiconductor IC packaging methods and structures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210444096.1A CN102931098B (en) | 2012-11-08 | 2012-11-08 | Chip packaging method |
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| Publication Number | Publication Date |
|---|---|
| CN102931098A CN102931098A (en) | 2013-02-13 |
| CN102931098B true CN102931098B (en) | 2015-06-03 |
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| CN102915986B (en) | 2012-11-08 | 2015-04-01 | 南通富士通微电子股份有限公司 | Chip packaging structure |
| WO2014071814A1 (en) * | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | Chip packaging structure and packaging method |
| WO2014071813A1 (en) | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | Semiconductor device package and packaging method |
| WO2014071815A1 (en) | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | Semiconductor device and manufacturing method thereof |
| US9922951B1 (en) * | 2016-11-12 | 2018-03-20 | Sierra Circuits, Inc. | Integrated circuit wafer integration with catalytic laminate or adhesive |
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| CN1132003A (en) * | 1994-08-15 | 1996-09-25 | 西铁城时计株式会社 | Semiconductor device |
| CN102496580A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Method for forming solder bump |
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| TW490821B (en) * | 2000-11-16 | 2002-06-11 | Orient Semiconductor Elect Ltd | Application of wire bonding technique on manufacture of wafer bump and wafer level chip scale package |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1132003A (en) * | 1994-08-15 | 1996-09-25 | 西铁城时计株式会社 | Semiconductor device |
| CN102496580A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Method for forming solder bump |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |