CN102931098A - Chip packaging method - Google Patents
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- CN102931098A CN102931098A CN2012104440961A CN201210444096A CN102931098A CN 102931098 A CN102931098 A CN 102931098A CN 2012104440961 A CN2012104440961 A CN 2012104440961A CN 201210444096 A CN201210444096 A CN 201210444096A CN 102931098 A CN102931098 A CN 102931098A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
Disclosed is a chip packaging method. The method comprises providing a semiconductor substrate which is provided with a metal pad and an insulation layer, wherein the insulation layer is provided with an opening exposing the metal pad; forming an under-ball metal electrode on the metal pad, wherein the metal electrode is provided with an electrode body portion and an electrode tail portion, the electrode body portion is arranged at the bottom of the under-ball metal electrode and connected with the metal pad, and the electrode tail portion is arranged at the top of the under-ball metal electrode; and forming a solder ball on the surface of the under-ball metal electrode. The chip packaging method improves the product reliability and is low in manufacture cost.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of chip packaging method.
Background technology
In the conventional art, IC chip and being connected of external circuit are that the mode by metal lead wire bonding (WireBonding) realizes.Along with the expansion with the integrated circuit scale dwindled of IC chip features size, Wire Bonding Technology is no longer applicable.Crystal wafer chip dimension encapsulation (Wafer Level Chip ScalePackaging, WLCSP) technology is that the full wafer wafer is carried out cutting the technology that obtains the single finished product chip after the packaging and testing again, and chip size and nude film after the encapsulation are in full accord.The crystal wafer chip dimension encapsulation technology has thoroughly been overturned the pattern of conventional package such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier), organic leadless chip carrier (Organic Leadless Chip Carrier), has complied with that market is day by day light, little, short to microelectronic product, thinning and low priceization requirement.It is highly microminiaturized that chip size after crystal wafer chip dimension encapsulation technology encapsulation has reached, chip cost along with chip size reduce significantly reduce with the increase of wafer size.The crystal wafer chip dimension encapsulation technology be IC can be designed, wafer manufacturing, packaging and testing, the technology that integrates, be the focus of current encapsulation field and the trend of future development.
Prior art discloses a kind of crystal wafer chip dimension encapsulation technology, please refer to Fig. 1, and Fig. 1 is the generalized section of prior art wafer level chip scale package structure, comprising: Semiconductor substrate 101; Be positioned at the metal pad 103 of described Semiconductor substrate 101 inside; Be positioned at the insulating barrier 102 on described Semiconductor substrate 101 surfaces, described insulating barrier 102 has the opening that exposes described metal pad 103; Be positioned at metal electrode 104 under the ball of the described metal pad 103 in described opening and cover part; Be positioned at the soldered ball on the metal electrode 104 105 under the described ball, the upper surface of metal electrode 104 under described soldered ball 105 ball covering on soils.
In the prior art, soldered ball 105 is positioned under the ball on the metal electrode 104, and the upper surface of metal electrode 104 contacts under soldered ball 105 and the ball, and contact area is little, the poor adhesive force under soldered ball 105 and the ball between the metal electrode 104.In addition, the material of metal electrode 104 is generally copper under the ball, the material of soldered ball 105 is generally tin, when the copper electrode surface forms the tin ball, tin atom can diffuse in the copper electrode and go, and copper atom also can diffuse in the tin ball simultaneously, forms interface alloy altogether compound (IMC:Intermetallic Compound) and cavity, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.
The chip packaging method poor reliability of prior art.
The method for filling of other relevant chips can also be the Chinese invention patent application of CN101211791 with reference to publication number, and it discloses a kind of wafer-grade chip packaging process and chip-packaging structure.
Summary of the invention
The problem that the present invention solves is poor adhesive force between the metal electrode under prior art soldered ball and the ball, poor reliability.
For addressing the above problem, the invention provides a kind of chip packaging method, comprising: Semiconductor substrate is provided, has metal pad and insulating barrier on the described Semiconductor substrate, described insulating barrier has the opening that exposes described metal pad; Form metal electrode under the ball at described metal pad, metal electrode has electrode body and electrode afterbody under the described ball, described electrode body section is positioned under the described ball metal electrode bottom and joins with described metal pad, and described electrode afterbody is positioned at metal electrode top under the described ball; Surface of metal electrode forms soldered ball under described ball.
Optionally, the material of described metal pad is gold, copper, aluminium or silver.
Optionally, described metal pad is distributed pad again.
Optionally, the method that forms metal electrode under the described ball is Bonding (Wire Bonding), comprising: metal lead wire and metal pad bonding form the electrode body; The metal lead wire starting the arc is to electrode tail height to be formed; Wire clamp cuts off metal lead wire, forms metal electrode under the ball.
Optionally, described electrode tail height is 0.005 ~ 1.5 times of described electrode body height.
Optionally, the material of metal electrode is a kind of in gold, copper, the silver under the described ball, and perhaps the material of metal electrode is the alloy that contains gold, copper or silver under the described ball.
Optionally, under described metal pad formation ball, before the metal electrode, also be included in the step that described metal pad surface forms transition metal layer.
Optionally, surface of metal electrode is formed with cover layer under described ball, and described cover layer also covers the metal pad of metal electrode bottom periphery under the described ball.
Optionally, described cover layer is the stacked structure of barrier layer and soakage layer, and described barrier layer is positioned at surface of metal electrode under the described ball, and described soakage layer is positioned at described barrier layer surface.
Optionally, the material of described barrier layer is nickel.
Optionally, the thickness of described barrier layer is 0.05 μ m to 5 μ m.
Optionally, the formation method of described barrier layer is chemical plating.
Optionally, the material of described soakage layer is a kind of in tin, the gold, silver, and perhaps the material of described soakage layer is the alloy of stanniferous, gold or silver.
Optionally, the thickness of described soakage layer is 0.05 μ m to 10 μ m.
Optionally, the formation method of described soakage layer is chemical plating.
Optionally, described soldered ball forms by typography.
Optionally, the material of described soldered ball is tin or ashbury metal.
Compared with prior art, the present invention has the following advantages:
Metal electrode has electrode body and electrode afterbody under the described ball, and described electrode body section is positioned under the described ball metal electrode bottom and joins with described metal pad, and described electrode afterbody is positioned at metal electrode top under the described ball.The method that forms metal electrode under the described ball is Bonding, comprising: metal lead wire and metal pad bonding form the electrode body; The metal lead wire starting the arc is to electrode tail height to be formed; Wire clamp cuts off metal lead wire, forms metal electrode under the ball.Behind follow-up formation soldered ball, described electrode afterbody embeds in the soldered ball, increased the contact area of metal electrode and soldered ball under the ball, so the Adhesion enhancement of metal electrode and soldered ball under the ball, so that soldered ball is when being subjected to External Force Acting, more difficult under the ball surface of metal electrode come off.The method that adopts in addition wire bonding method to form metal electrode under the ball adopts the method for electroplating metal electrode under the formation ball to compare with prior art, and flow process is short, low cost of manufacture.
Surface of metal electrode forms cover layer under described ball, and described cover layer is the stacked structure of barrier layer and soakage layer, and described barrier layer is positioned at surface of metal electrode under the described ball, and described soakage layer is positioned at described barrier layer surface.In the prior art, soldered ball is located immediately under the ball on the metal electrode, under the ball between metal electrode and the soldered ball diffusion by atom can form interface alloy altogether compound and cavity, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.In the present invention, surface of metal electrode forms first barrier layer under ball, the material of described barrier layer is nickel, compare barrier layer and soldered ball formation interface alloy compound is slow a lot of altogether with metal electrode under the ball, can be used as the barrier layer between the metal electrode and soldered ball under the ball, prevent from forming interface alloy altogether compound and cavity.And because the easy oxidation of barrier layer, further form the oxidation that soakage layer prevents barrier layer on the barrier layer surface, in addition, the material of the soldered ball of soakage layer and follow-up formation infiltrates, adhesive force is better, the material of described soakage layer is a kind of in tin, the gold, silver, and perhaps the material of described soakage layer is the alloy of stanniferous, gold or silver.Compared with prior art, surface of metal electrode forms cover layer and has improved altogether compound problem of interface alloy under ball, has promoted the reliability of chip package.
Description of drawings
Fig. 1 is the cross-sectional view of prior art chip-packaging structure;
Fig. 2 is the flow chart of the chip packaging method that provides of first embodiment of the invention;
Fig. 3 to Fig. 7 is the cross-sectional view of the chip package process of first embodiment of the invention;
Fig. 8 and Fig. 9 are the cross-sectional view of the chip package procedure division step of second embodiment of the invention;
Figure 10 is the chip packaging method flow chart that third embodiment of the invention provides;
Figure 11 and Figure 12 are the cross-sectional view of the chip package procedure division step of third embodiment of the invention.
Embodiment
By background technology as can be known, in the prior art, soldered ball is located immediately under the ball on the metal electrode, and the contact area of metal electrode is little under soldered ball and the ball, poor adhesive force.In addition, the material of metal electrode is generally copper under the ball, the material of soldered ball is generally tin, when the copper electrode surface forms the tin ball, tin atom can diffuse in the copper electrode and go, and copper atom also can diffuse in the tin ball simultaneously, forms interface alloy altogether compound and cavity, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.Prior art forms the method for metal electrode under the ball for electroplating, and needs the technique of photoetching to define position and the shape of metal electrode under the ball, complex process, and cost is high.
The present inventor proposes a kind of new chip packaging method through creative work, comprising: Semiconductor substrate is provided, has metal pad and insulating barrier on the described Semiconductor substrate, described insulating barrier has the opening that exposes described metal pad; Form metal electrode under the ball at described metal pad, metal electrode has electrode body and electrode afterbody under the described ball, described electrode body section is positioned under the described ball metal electrode bottom and joins with described metal pad, and described electrode afterbody is positioned at metal electrode top under the described ball; Surface of metal electrode forms soldered ball under described ball.
Describe three specific embodiments provided by the invention below in conjunction with Figure of description, above-mentioned purpose and advantage of the present invention will be clearer.Need to prove that the purpose that these accompanying drawings are provided is to help to understand embodiments of the invention, and should not be construed as improperly restriction of the present invention.For the purpose of clearer, size shown in the figure and not drawn on scale may be made amplification, be dwindled or other changes.A lot of details have been set forth in order to fully understand the present invention in the following description.But the present invention can implement much to be different from other modes described here, and those skilled in the art can do similar popularization in the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
The first embodiment
Please refer to Fig. 2, Fig. 2 is the flow chart of first embodiment of the invention, comprising:
Step S101 provides Semiconductor substrate, has metal pad and insulating barrier on the described Semiconductor substrate, and described insulating barrier has the opening that exposes described metal pad;
Step S102, form metal electrode under the ball at described metal pad, metal electrode has electrode body and electrode afterbody under the described ball, and described electrode body section is positioned under the described ball metal electrode bottom and joins with described metal pad, and described electrode afterbody is positioned at metal electrode top under the described ball;
Step S103, surface of metal electrode forms cover layer under described ball;
Step S104 is being formed with surface of metal electrode formation soldered ball under the tectal ball.
At first, please refer to Fig. 3, Semiconductor substrate 201 is provided, have metal pad 203 and insulating barrier 202 on the described Semiconductor substrate 201, described insulating barrier 202 has the opening that exposes described metal pad 203.
Described Semiconductor substrate 201 can be monocrystalline silicon, SOI(silicon-on-insulator), SiGe or III-V compounds of group wafer, described Semiconductor substrate 201 comprises one deck or the some layers of dielectric layer that are positioned at its inside and surface, and described Semiconductor substrate 201 can also comprise making semiconductor device, metal interconnected and other semiconductor structures thereon.Described insulating barrier 202 comprises passivation layer and polymeric layer (not shown), described passivation layer exposes the opening of described metal pad 203 for the protection of metal pad 203, electric isolation and formation, and the material of described passivation layer can be silica, silicon nitride or low-K material; Described polymeric layer is positioned on the described passivation layer, described polymeric layer has the opening that exposes described metal pad 203, and the material of described polymer can be polyimides (Polyimide), epoxy resin (Epoxy) or benzocyclobutane olefine resin (Benzocyclobutene).The top layer interconnecting metal electrode that described metal pad 203 is described Semiconductor substrate 201, the material of described metal pad 203 can be gold, copper, aluminium or silver.
In one embodiment, described Semiconductor substrate 201 is monocrystalline silicon, and described Semiconductor substrate 201 has also comprised semiconductor device, metal interconnection and other semiconductor structures of making thereon.Described insulating barrier 202 comprises that material is that passivation layer and the material of silica is the polymeric layer of polyimides, described insulating barrier 202 has the opening of exposing metal pad 203, the interconnected metal electrode of top layer that described metal pad 203 is described Semiconductor substrate 201, the material of described metal pad 203 is copper.
Then, please refer to Fig. 4, form metal electrode 204 under the ball at described metal pad 203, metal electrode 204 has electrode body 204a and electrode afterbody 204b under the described ball, described electrode body 204a is positioned under the described ball metal electrode 204 bottoms and joins with described metal pad 203, and described electrode afterbody 204b is positioned at metal electrode 204 tops under the described ball.Wherein, the soldered ball of described electrode body 204a connection metal pad 203 and follow-up formation also supports described electrode afterbody 204b, described electrode afterbody 204b embeds in the soldered ball of follow-up formation, increased the contact area of metal electrode 204 and soldered ball under the ball, therefore the Adhesion enhancement of metal electrode 204 and soldered ball under the ball, so that soldered ball is when being subjected to External Force Acting, more difficult under the ball metal electrode 204 surfaces come off.
The method that forms metal electrode 204 under the described ball is Bonding (Wire Bonding), comprising: metal lead wire and metal pad bonding form electrode body 204a; The metal lead wire starting the arc is to electrode afterbody 204b height to be formed; Wire clamp cuts off metal lead wire, forms metal electrode 204 under the ball.
At an embodiment, the technique that forms metal electrode 204 under the described ball is specially: metal lead wire arrives metal pad 203 tops by bonding head, utilizing oxyhydrogen flame or electrical discharge system to produce electric spark goes between with the deposite metal, under capillary effect, motlten metal solidifies and forms spherical (bulb diameter generally is 1.5 times to 4 times of metal lead wire diameter), fall bonding head, at suitable pressure, temperature, in kinetic energy and time Metal Ball is pressed on the metal pad 203, in this process, exert pressure to Metal Ball by bonding head, promote simultaneously lead-in wire metal and metal pad 203 that phase counterdiffusion between plastic deformation and the atom occurs, form electrode body 204a; Then, bonding head lifts, and the metal lead wire starting the arc utilizes the bonding wire clamp to cut off metal lead wire to certain height (electrode afterbody 204b height to be formed), and the upper metal lead wire of electrode body 204a is electrode afterbody 204b, forms metal electrode 204 under the ball.Need to prove, Bonding is usually used in the technique that connects between semiconductor packaged inner chip and external terminal and the chip, and the present inventor is by improving lead key closing process, be applied in the formation technique of metal electrode 204 under the ball, the metal lead wire starting the arc forms electrode afterbody 204b after can adopting bonding head to lift when forming electrode body 204a, technique is simple, and it is high to form efficient.
The material of metal electrode 204 is a kind of in gold, copper, the silver under the described ball, and perhaps the material of metal electrode 204 is the alloy that contains gold, copper or silver under the described ball.The height of described electrode afterbody 204b is 0.005 ~ 1.5 times of described electrode body 204a height, when the height of electrode afterbody 204b is lower than 0.005 times of electrode body 204a height, electrode afterbody 204b embeds the limited length of the soldered ball of follow-up formation, and is limited to the Adhesion enhancement of metal electrode under the ball 204 and soldered ball; And when the height of electrode afterbody 204b is higher than 1.5 times of height of electrode body 204a, because electrode afterbody 204b forms by the starting the arc behind the Bonding, electrode afterbody 204b is thinner with electrode body 204a phase diameter group, and the metal quality is softer, easy bending and affect the shape of soldered ball in the manufacture process, rate of finished products reduces, and is unfavorable for down chip package.
In one embodiment, the material of metal electrode 204 is copper under the described ball, and the height of described electrode afterbody 204b is identical with the height of described electrode body 204a.
Then, please refer to Fig. 5 and Fig. 6, metal electrode 204 surfaces form cover layer under described ball, and described cover layer also covers the metal pad 203 of metal electrode 204 bottom peripheries under the described ball.Described cover layer is the stacked structure of barrier layer 205 and soakage layer 206, and described barrier layer 205 is positioned at metal electrode 204 surfaces under the described ball, and described soakage layer 206 is positioned at described barrier layer 205 surfaces.
Fig. 5 is the cross-sectional view that metal electrode 204 surfaces form barrier layer 205 under described ball.The material of described barrier layer 205 is nickel, compare barrier layer 205 compound is slow a lot of altogether with soldered ball formation interface alloy with metal electrode under the ball 204, can be used as the barrier layer between the metal electrode 204 and soldered ball under the ball, prevent from forming interface alloy altogether compound and cavity.The interface alloy is compound and empty mechanical strength and the life-span that can affect solder joint altogether, can effectively improve altogether compound problem of interface alloy so form barrier layer, has promoted the reliability of chip package.The formation method of described barrier layer 205 is chemical plating.Chemical plating also is called electroless plating, and it is in cold situation, utilizes redox reaction to obtain the method for the coat of metal on plating piece surface, the coating that forms even, and chemical plating plant is simple, does not need power supply and anode.The thickness of described barrier layer 205 is 0.05 μ m to 5 μ m, and the thickness of described barrier layer 205 is relevant with the technique of chip package process, and when the technological temperature of chip package process was lower, the thickness of described barrier layer 205 can reduce.
In one embodiment, first metal electrode under the ball 204 is processed before the chemical plating, removed its surperficial oxide-film, to reduce contact resistance; Then metal electrode 204 surface chemical platings form nickel dam under ball, and the thickness of described nickel dam is 0.1 μ m to 3 μ m.
Fig. 6 is the cross-sectional view that forms soakage layer 206 on described barrier layer 205 surfaces.The material of described barrier layer 205 is generally nickel, the easy oxidation of nickel, cause interfacial resistivity to increase, so further form soakage layer 206 to prevent the oxidation of barrier layer 205 on described barrier layer 205 surfaces, in addition, described soakage layer 206 infiltrates with the material of the soldered ball of follow-up formation, and adhesive force is better.The material of described soakage layer 206 is a kind of in tin, the gold, silver, and perhaps the material of described soakage layer 206 is the alloy of stanniferous, gold or silver.The formation method of described soakage layer 206 is chemical plating.The thickness of described soakage layer 206 is 0.05 μ m to 10 μ m, and the thickness of described soakage layer 206 is also relevant with the technique of chip package.
In one embodiment, described soakage layer 206 is the tin layer, and the tin layer is not easy oxidized in air, and infiltrates with the soldered ball material of follow-up formation, and adhesive force is better, and the formation method of described tin layer is chemical plating, and the thickness of described tin layer is 0.1 μ m to 5 μ m.
Then, please refer to Fig. 7, be formed with metal electrode 204 surface formation soldered balls 207 under the tectal ball.Described soldered ball 207 forms by typography, and the material of described soldered ball 207 is tin or ashbury metal.The concrete technology that forms soldered ball 207 is: scolder is coated on by web plate is formed with under the tectal ball on the metal electrode 204, then carry out high temperature reflux, under the surface tension effects, so that described scolder changes soldered ball 207 into.
The second embodiment
Present embodiment is compared with the first embodiment, and difference is: described metal pad is distributed pad (RDL) again.The formation method of described more distributed pad is well known to those skilled in the art, and does not repeat them here.
Please refer to Fig. 8, Semiconductor substrate 301 is provided, described Semiconductor substrate 301 comprises: the metal electrode 308 that is positioned at described Semiconductor substrate 301; Be positioned at the first insulating barrier 309 of the described metal electrode 308 of described Semiconductor substrate 301 and cover part, described the first insulating barrier 309 has the first opening that exposes described metal electrode 308; Cover the sidewall of described the first opening and the transition metal layer 310 of basal surface, described transition metal layer 310 forms the second opening along described the first open surfaces; Be positioned on the transition metal layer 310, and fill the metal pad 303 of described the second opening; Be positioned at the second insulating barrier 302 on the described metal pad 303, described the second insulating barrier 302 has the 3rd opening that exposes described metal pad 303.
Metal pad described in the present embodiment 303 is distributed pad (RDL) again.Described more distributed pad is by increasing the first insulating barrier 309, transition metal layer 310 and the second insulating barrier 302 forms at chip surface, it can again be arranged the position of the metal electrode 308 in the Semiconductor substrate 301 according to the design rule of packaging technology and be the position of distributed pad again.Distributed pad can dwindle the chip package size greatly again, reaches the demand of high-density packages, and has promoted speed and the stability of transfer of data.
Please refer to Fig. 9, form metal electrode 304 under the ball at described metal pad 303, metal electrode 304 has electrode body and electrode afterbody under the described ball, described electrode body section is positioned under the described ball metal electrode 304 bottoms and joins with described metal pad 303, and described electrode afterbody is positioned at metal electrode 304 tops under the described ball; Metal electrode 304 surfaces form cover layer under described ball, described cover layer also covers the metal pad 303 of metal electrode 304 bottom peripheries under the described ball, described cover layer is the stacked structure of barrier layer 305 and soakage layer 306, described barrier layer 305 is positioned at metal electrode 304 surfaces under the described ball, and described soakage layer 306 is positioned at described barrier layer 305 surfaces; Metal electrode 304 surfaces form soldered ball 307 under the tectal ball being formed with.
The appropriate section that above-mentioned concrete forming process and associated description please refer to the first embodiment does not repeat them here.
The 3rd embodiment
Figure 10 is the schematic flow sheet of third embodiment of the invention, and Figure 11 and Figure 12 are the schematic diagram of part steps in the above-mentioned flow process, are elaborated below in conjunction with Figure 10.
Please refer to Figure 10, Figure 10 is the flow chart of third embodiment of the invention, comprising:
Step S201 provides Semiconductor substrate, has metal pad and insulating barrier on the described Semiconductor substrate, and described insulating barrier has the opening that exposes described metal pad;
Step S203 forms transition metal layer on described metal pad surface;
Step S203, form metal electrode under the ball at described metal pad, metal electrode has electrode body and electrode afterbody under the described ball, and described electrode body section is positioned under the described ball metal electrode bottom and joins with described metal pad, and described electrode afterbody is positioned at metal electrode top under the described ball;
Step S204, surface of metal electrode forms cover layer under described ball;
Step S205 is being formed with surface of metal electrode formation soldered ball under the tectal ball.
Figure 10 compares with Fig. 2, and the difference of present embodiment and the first embodiment is: before the metal electrode, also be included in the step that described metal pad surface forms transition metal layer under described metal pad formation ball.
Please refer to Figure 11, form transition metal layer 408 on described metal pad 403 surfaces.Described transition metal layer 408 plays non-proliferation, increases the effect of adhesion and protection metal pad 403.The technique that forms described transition metal layer 408 can be physical vapour deposition (PVD), chemical vapour deposition (CVD), electrochemical deposition and electroplating technology.Described transition metal layer 408 can be NiPdAu layer, Ag layer, the lamination of one or more in Ti layer, Ta layer, TiN layer, TaN layer, Cu layer or the Cu alloy-layer.The thickness of described transition metal layer 408 is 0.1 μ m to 3 μ m.Choosing of described transition metal layer 408 thickness, relevant with the process of chip package, the thickness of the less described transition metal layer 408 of the process of chip package is less.
In one embodiment, the material of described transition metal layer 408 is TiN, and the thickness of described transition metal layer 408 is 0.2 μ m to 1.5 μ m.
Please refer to Figure 12, form metal electrode 404 under the ball at the described metal pad 403 that is formed with transition metal layer 408, metal electrode 404 has electrode body and electrode afterbody under the described ball, described electrode body section is positioned under the described ball metal electrode 404 bottoms and joins with described more distributed pad 403, and described electrode afterbody is positioned at metal electrode 404 tops under the described ball; Metal electrode 404 surfaces form cover layer under described ball, described cover layer is the stacked structure of barrier layer 405 and soakage layer 406, described barrier layer 405 is positioned at metal electrode 404 surfaces under the described ball, and described soakage layer 406 is positioned at described barrier layer 405 surfaces; Metal electrode 404 surfaces form soldered ball 407 under the tectal ball being formed with.
The appropriate section that above-mentioned concrete forming process and associated description please refer to the first embodiment does not repeat them here.
In sum, compared with prior art, the present invention has the following advantages:
Use the technique of Bonding to form metal electrode under the ball, metal electrode has electrode body and electrode afterbody under the described ball.In the prior art, soldered ball is located immediately at surface of metal electrode under the ball, the contact area of metal electrode is limited under soldered ball and the ball, and in the present invention, after surface of metal electrode under the follow-up ball formed soldered ball, described electrode afterbody embedded in the soldered ball, increased the contact area of metal electrode and soldered ball under the ball, therefore the Adhesion enhancement of metal electrode and soldered ball under the ball so that soldered ball is when being subjected to External Force Acting, more difficult under the ball surface of metal electrode come off.Bonding is usually used in the technique that connects between semiconductor packaged inner chip and external terminal and the chip, and the present inventor is by improving lead key closing process, be applied in the formation technique of metal electrode under the ball, the metal lead wire starting the arc forms the electrode afterbody after can adopting bonding head to lift when forming the electrode body, technique is simple, and it is high to form efficient.
Surface of metal electrode forms cover layer under described ball, and described cover layer is the stacked structure of barrier layer and soakage layer.In the prior art, soldered ball is located immediately under the ball on the metal electrode, under the ball between metal electrode and the soldered ball diffusion by atom can form interface alloy altogether compound and cavity, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.In the present invention, surface of metal electrode forms first barrier layer under ball, the material of described barrier layer is nickel, compare barrier layer and soldered ball formation interface alloy compound is slow a lot of altogether with metal electrode under the ball, can be used as the barrier layer between the metal electrode and soldered ball under the ball, prevent from forming interface alloy altogether compound and cavity.And because the easy oxidation of barrier layer, further form the oxidation that soakage layer prevents barrier layer on the barrier layer surface, in addition, the material of the soldered ball of soakage layer and follow-up formation infiltrates, adhesive force is better, the material of described soakage layer is a kind of in tin, the gold, silver, and perhaps the material of described soakage layer is the alloy of stanniferous, gold or silver.Compared with prior art, surface of metal electrode forms cover layer and has improved altogether compound problem of interface alloy under ball, has promoted the reliability of chip package.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (17)
1. a chip packaging method is characterized in that, comprising:
Semiconductor substrate is provided, has metal pad and insulating barrier on the described Semiconductor substrate, described insulating barrier has the opening that exposes described metal pad;
Form metal electrode under the ball at described metal pad, metal electrode has electrode body and electrode afterbody under the described ball, described electrode body section is positioned under the described ball metal electrode bottom and joins with described metal pad, and described electrode afterbody is positioned at metal electrode top under the described ball;
Surface of metal electrode forms soldered ball under described ball.
2. chip packaging method as claimed in claim 1 is characterized in that, the material of described metal pad is gold, copper, aluminium or silver.
3. chip packaging method as claimed in claim 1 is characterized in that, described metal pad is distributed pad again.
4. chip packaging method as claimed in claim 1 is characterized in that, the method that forms metal electrode under the described ball is Bonding, comprising:
Metal lead wire and metal pad bonding form the electrode body;
The metal lead wire starting the arc is to electrode tail height to be formed;
Wire clamp cuts off metal lead wire, forms metal electrode under the ball.
5. chip packaging method as claimed in claim 1 is characterized in that, described electrode tail height is 0.005 ~ 1.5 times of described electrode body height.
6. chip packaging method as claimed in claim 1 is characterized in that, the material of metal electrode is a kind of in gold, copper, the silver under the described ball, and perhaps the material of metal electrode is the alloy that contains gold, copper or silver under the described ball.
7. chip packaging method as claimed in claim 1 is characterized in that, before the metal electrode, also is included in the step that described metal pad surface forms transition metal layer under described metal pad formation ball.
8. chip packaging method as claimed in claim 1 is characterized in that, surface of metal electrode is formed with cover layer under described ball, and described cover layer also covers the metal pad of metal electrode bottom periphery under the described ball.
9. chip packaging method as claimed in claim 8 is characterized in that, described cover layer is the stacked structure of barrier layer and soakage layer, and described barrier layer is positioned at surface of metal electrode under the described ball, and described soakage layer is positioned at described barrier layer surface.
10. chip packaging method as claimed in claim 9 is characterized in that, the material of described barrier layer is nickel.
11. chip packaging method as claimed in claim 9 is characterized in that, the thickness of described barrier layer is 0.05 μ m to 5 μ m.
12. chip packaging method as claimed in claim 9 is characterized in that, the formation method of described barrier layer is chemical plating.
13. chip packaging method as claimed in claim 9 is characterized in that, the material of described soakage layer is a kind of in tin, the gold, silver, and perhaps the material of described soakage layer is the alloy of stanniferous, gold or silver.
14. chip packaging method as claimed in claim 9 is characterized in that, the thickness of described soakage layer is 0.05 μ m to 10 μ m.
15. chip packaging method as claimed in claim 9 is characterized in that, the formation method of described soakage layer is chemical plating.
16. chip packaging method as claimed in claim 1 is characterized in that, described soldered ball forms by typography.
17. chip packaging method as claimed in claim 1 is characterized in that, the material of described soldered ball is tin or ashbury metal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210444096.1A CN102931098B (en) | 2012-11-08 | 2012-11-08 | Chip packaging method |
| US14/074,598 US9589815B2 (en) | 2012-11-08 | 2013-11-07 | Semiconductor IC packaging methods and structures |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014071814A1 (en) * | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | Chip packaging structure and packaging method |
| US9293432B2 (en) | 2012-11-08 | 2016-03-22 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for chip packaging structure |
| US9379077B2 (en) | 2012-11-08 | 2016-06-28 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for semiconductor device |
| US9548282B2 (en) | 2012-11-08 | 2017-01-17 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for semiconductor device |
| CN110169210A (en) * | 2016-11-12 | 2019-08-23 | 塞拉电路公司 | It is integrated using the IC wafer of catalysis layered product or adhesive |
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| CN1132003A (en) * | 1994-08-15 | 1996-09-25 | 西铁城时计株式会社 | Semiconductor device |
| US20020056741A1 (en) * | 2000-11-16 | 2002-05-16 | Shieh Wen Lo | Application of wire bonding technology on wafer bump, wafer level chip scale package structure and the method of manufacturing the same |
| CN102496580A (en) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | Method for forming solder bump |
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| CN1132003A (en) * | 1994-08-15 | 1996-09-25 | 西铁城时计株式会社 | Semiconductor device |
| US20020056741A1 (en) * | 2000-11-16 | 2002-05-16 | Shieh Wen Lo | Application of wire bonding technology on wafer bump, wafer level chip scale package structure and the method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014071814A1 (en) * | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | Chip packaging structure and packaging method |
| US9293432B2 (en) | 2012-11-08 | 2016-03-22 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for chip packaging structure |
| US9379077B2 (en) | 2012-11-08 | 2016-06-28 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for semiconductor device |
| US9548282B2 (en) | 2012-11-08 | 2017-01-17 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for semiconductor device |
| CN110169210A (en) * | 2016-11-12 | 2019-08-23 | 塞拉电路公司 | It is integrated using the IC wafer of catalysis layered product or adhesive |
| CN110169210B (en) * | 2016-11-12 | 2020-12-08 | 卡特拉姆有限责任公司 | Integrated circuit wafer integration using catalytic laminates or adhesives |
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| CN102931098B (en) | 2015-06-03 |
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