CN102916053A - Storage device and fabrication method of storage device - Google Patents
Storage device and fabrication method of storage device Download PDFInfo
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- CN102916053A CN102916053A CN201210413642.5A CN201210413642A CN102916053A CN 102916053 A CN102916053 A CN 102916053A CN 201210413642 A CN201210413642 A CN 201210413642A CN 102916053 A CN102916053 A CN 102916053A
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- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
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Abstract
The invention discloses a storage device and a fabrication method of the storage device. The storage device at least comprises a semiconductor substrate, a grid structure and a source or drain area at one side of the grid structure and further comprises an epitaxial conducting layer and an isolation oxide layer, wherein the epitaxial conducting layer is arranged on the surface of a substrate at the other side of the grid structure and corresponds to the grid structure, and the isolation oxide layer is arranged at the same side of the epitaxial conducting layer and covers the sidewall of the grid structure on the same side and the surface of the epitaxial conducting layer. Due to the epitaxial conducting layer provided to the storage device, the migration path of thermions can be changed, so that the programming performance of the device can be effectively improved.
Description
Technical field
The present invention relates to semiconductor device and technique, and be particularly related to memory device that comprises separate gate and preparation method thereof.
Background technology
At present, common floating gate flash memory device is divided into two classes usually by structure, and a class has floating stacking gate structure, and another kind of then have a separate gate structure.The former has the high characteristics of integration density, is usually used in the jumbo data storage of needs, such as USB flash disk, and S/D card etc.Latter's integrated level is lower, but because operating voltage is lower, periphery circuit design is simple, eliminated the problem of wiping, the aspects such as PC BIOS, network communication, various Embedded Application that are applied in more.
With reference to figure 1, traditional memory device that comprises separate gate comprises at least: dielectric layer 103, control gate 104, upper strata insulating medium layer 105, active area 106 and be positioned at substrate 100, upper strata insulating medium layer 105 and the selection grid 107 of bit line top between silicon substrate 100, the tunneling medium layer 101 that is positioned at substrate surface, floating boom 102, grid.Wherein, be provided with side wall 110 at the sidewall of floating boom 102 and control gate 104, active area 106 is isolated respectively at floating boom 102 and control gate 104 by side wall 110.In the course of work of above-mentioned memory device, when for example writing (or programming) operation in execution, by applying voltage at control gate, so that produce hot electron in the substrate 100, and collect and store by floating boom 102.That is to say that these thermionic collections and storage are subject to the impact of the electric field on horizontal direction and the vertical direction simultaneously.Because these two electric fields are mutually vertical, these hot electrons carry out moving of horizontal direction along raceway groove first, then carry out the motion of vertical direction towards floating boom again, thereby are collected and store by floating boom, and then realize that memory device write (or programming) operates.
The Chinese invention patent application that the patent No. is that ZL02140327.9, name are called that the Chinese invention patent of " separated grid electrode type quick flashing storage and manufacture method thereof " and application number are 200910201351.8, name is called " separate gate flash memory and manufacture method thereof " discloses respectively a kind of technical scheme, by traditional memory device that comprises separate gate is improved, in the hope of the higher electron transfer rate of acquisition, and then improve device performance.In these disclosed technical schemes, bottom by floating boom is set to acute angle, perhaps by making floating boom only have the drift angle of protrusion in a side of closing on erase gate, thereby so that memory device can when execution writes or wipes, have higher operating efficiency.
Yet, even in the technical scheme after above-mentioned these improvement, hot electron is producing from source electrode the process of being collected by floating boom, still must at first carry out horizontal movement to the floating boom below along raceway groove, thereby then under the effect of vertical electric field, carry out moving of vertical direction and enter floating boom, this undoubtedly will be greatly causes restriction to the program speed of device, thereby affects the overall performance performance of memory device.
Summary of the invention
The invention provides a kind of memory device and preparation method thereof, by between substrate and tunnel oxide, increasing the extension conductive layer, so that hot electron can directly enter floating boom after producing, thereby improve device performance.
In order to realize above-mentioned technical purpose, the invention provides a kind of memory device, at least comprise: Semiconductor substrate, grid structure, be positioned at source or the drain region of described grid structure one side, also comprise: be positioned at described grid structure opposite side substrate surface and the extension conductive layer corresponding with described grid structure, be positioned at described extension conductive layer homonymy and cover the isolating oxide layer of this side sidewall of described grid structure and described extension conductive layer surface.
Optionally, corresponding described extension conductive layer and the described floating boom of referring to described grid structure of described extension conductive layer is corresponding.
Optionally, the thickness of described extension conductive layer is 1/2 to 4/5 of described tunnel oxide and described floating boom thickness sum.
Optionally, the thickness of described extension conductive layer is 2/3 of described tunnel oxide and described floating boom thickness sum.
In addition, the present invention also provides a kind of memory device manufacture method, comprises at least: Semiconductor substrate is provided, and described substrate comprises grid structure at least; Sidewall in described grid structure one side forms side wall by self-registered technology; Side epitaxial growth at described side wall forms the extension conductive layer corresponding with described grid structure; Deposit forms isolating oxide layer successively above described extension conductive layer, and forms the word line.
Optionally, corresponding described extension conductive layer and the described floating boom of referring to described grid structure of described extension conductive layer is corresponding.
Optionally, the thickness of described extension conductive layer is 1/2 to 4/5 of described tunnel oxide and described floating boom thickness sum.
Optionally, the thickness of described extension conductive layer is 2/3 of described tunnel oxide and described floating boom thickness sum.
Optionally, describedly form side wall by self-registered technology and comprise: adopt chemical vapor deposition method in the sidewall growth oxide layer of described grid structure one side; Adopt self-registered technology that described oxide layer is carried out etching, form the side wall of being close to described grid structure sidewall.
Optionally, adopt the described extension conductive layer of selective epitaxial growth, so that described extension conductive layer is only grown at silicon face.
Optionally, the described growth formation extension conductive layer corresponding with grid structure also comprises: form after the described extension conductive layer, described side wall before wet method is removed is to expose the floating boom upper side.
Compared to prior art, increase the extension conductive layer corresponding with grid structure between memory device substrate of the present invention and the isolating oxide layer, change thermionic migration path, thereby effectively improved device performance.In addition, memory device manufacture method of the present invention adopts self-registered technology, has avoided the extra increase to reticle, has saved production cost.
Description of drawings
Fig. 1 is a kind of structural representation that comprises the memory device of separate gate of prior art;
Fig. 2 is the structural representation of a kind of execution mode of memory device of the present invention;
Fig. 3 is the schematic flow sheet of a kind of execution mode of memory device manufacture method of the present invention;
Fig. 4 to Fig. 7 is for adopting the device architecture schematic diagram of each step of memory device manufacture method of the present invention.
Embodiment
Below in conjunction with specific embodiments and the drawings, the present invention is described in detail.Set forth detail in the following description so that fully understand the present invention, but the present invention can with multiple from describe other different modes at this and implement, those skilled in the art can do approximate the popularization in the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public embodiment.
With reference to figure 2, the invention provides a kind of memory device, comprise: Semiconductor substrate 200, grid structure 210, be positioned at the extension conductive layer 220 of grid structure 210 1 side substrate surfaces, with extension conductive layer 220 homonymies and the isolating oxide layer 230 that is positioned at grid structure 210 sidewalls and is positioned at extension conductive layer 220 surfaces, be positioned at the word wiregrating 240 on part isolating oxide layer 330 surfaces that cover extension conductive layer 220 surfaces, and the source or the drain region 250 that are positioned at grid structure 210 opposite sides.Wherein, described grid structure 210 can comprise: lay respectively at dielectric layer 203, control gate 204, insulating medium layer 205 between the tunnel oxide 201, floating boom 202, grid on described substrate 200 surfaces with the storehouse form.
Above-mentioned memory device comprises the extension conductive layer 220 that is positioned at substrate 200 surfaces, this extension conductive layer 220 and word wiregrating 240 are positioned at the homonymy of grid structure 210, and corresponding with the floating boom 202 in the grid structure 210 in the horizontal direction, so that in the process that this memory device is programmed, when respectively when word wiregrating and control gate apply voltage, the hot electron that produces can be via extension conductive layer 220, directly horizontal movement transfers to floating boom 202, thereby need not through first horizontal direction being folded to motion of vertical direction and enter floating boom 202 again, effectively reduced the energy and momentum loss in the motion, correspondingly strengthen thermionic injection efficiency, and then improved widely the program performance of memory device.In specific embodiment, the height of described extension conductive layer 220 can be 1/2 to 4/5 of tunnel oxide 201 and floating boom 202 thickness sums, and concrete for example can be 2/3.
In addition, because this extension conductive layer 220 is corresponding with floating boom 202 in the horizontal direction, hot electron is directly from 220 horizontal movements of extension conductive layer to floating boom 202, thereby can regulate the effective thickness of floating boom by the thickness of adjusting extension conductive layer 220, thereby can under the prerequisite of not loss device performance, increase process window.
To Fig. 7, the present invention also provides a kind of manufacture method of memory device with reference to figure 3.Wherein, Fig. 3 is the flow chart of memory device manufacture method of the present invention, and Fig. 4 to Fig. 7 is the structural section figure of memory device that each step forms when using a kind of execution mode of memory device manufacture method of the present invention.
Need to prove that in the semiconductor technology of reality, the making of memory is the large-scale memory cell array of disposable formation usually, only for needs are described, take illustrated cell as example, but actual unit number should not be subjected to the restriction of accompanying drawing.The purpose that these accompanying drawings are provided is to help to understand embodiments of the invention, and should not be construed as improper restriction of the present invention.For the sake of clarity, size shown in the figure and not drawn on scale may be done to amplify, dwindle or other change.
The below combines Fig. 4 to Fig. 7 and Fig. 3 embodiment of the present invention is further set forth.
Step S1 provides the Semiconductor substrate that has at least grid structure.With reference to figure 4, wherein, described grid structure is positioned at described substrate 400 surfaces, can comprise: dielectric layer 403, control gate 404 and insulating medium layer 405 between the tunnel oxide 401 of piling up with the storehouse form, floating boom 402, grid.In other embodiments, the Semiconductor substrate 400 that provides also can comprise the source that is formed at described grid structure one side/drain electrode 450.
Step S2 forms side wall at the sidewall of described grid structure one side by self-registered technology.Specifically, with reference to figure 5, at first can adopt chemical vapor deposition method in the sidewall growth oxide layer of described grid structure one side; Then, can adopt self-registered technology that described oxide layer is carried out etching, thereby form the side wall 411 of being close to gate lateral wall.Wherein, described side wall can be silica.
Step S3 is at the side epitaxial growth formation extension conductive layer corresponding with described floating boom of described side wall.With reference to figure 6, side wall 411 1 sides are close to grid structure 410, at side wall 411 opposite side selective epitaxial growth extension conductive layers 420, so that extension conductive layer 420 is only in silicon face growth, and can not grow at silicon oxide surface.Wherein, the thickness of formed extension conductive layer 420 can be 1/2 to 4/5 of tunnel oxide 401 and floating boom 402 thickness sums in the grid structure, concrete for example can be 2/3, in order to can regulate the effective thickness of floating boom 402 by the thickness of adjusting extension conductive layer 420, thereby can under the prerequisite of not loss device performance, increase process window.
In addition, step S3 also can comprise: form after the described extension conductive layer 420, adopt wet etching to remove and play the side wall 411 of buffer action before, thereby expose the part that floating boom 402 exceeds extension conductive layer 420.
Step S4, deposit forms isolating oxide layer and polysilicon successively above described extension conductive layer, and forms the word line.With reference to figure 7, formed isolating oxide layer 430 is positioned at extension conductive layer 420 surface and described grid structure sidewalls.Then, in the part isolating oxide layer 430 surface deposition doped polycrystalline silicon that are positioned at extension conductive layer 420 surfaces, form the word line.
Compared to prior art, memory device of the present invention has the extension conductive layer corresponding with floating boom at the substrate surface of grid one side, so that the hot electron that produces can be directly from the horizontal movement of extension conductive layer to floating boom, the motion that is folded to of having avoided elder generation vertically to enter again floating boom by the raceway groove horizontal movement to the floating boom below, thereby improved the speed that device writes or programmes, improved performance of devices.In addition, by self-registered technology and epitaxial growth, avoided increasing extra mask, thereby reduced process costs in the memory device manufacture method of the present invention.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (11)
1. memory device, at least comprise: Semiconductor substrate, grid structure, be positioned at source or the drain region of described grid structure one side, it is characterized in that, also comprise: be positioned at described grid structure opposite side substrate surface and the extension conductive layer corresponding with described grid structure, be positioned at described extension conductive layer homonymy and cover the isolating oxide layer of this side sidewall of described grid structure and described extension conductive layer surface.
2. memory device as claimed in claim 1 is characterized in that, described extension conductive layer is corresponding with described grid structure to refer to that described extension conductive layer and described floating boom are corresponding.
3. memory device as claimed in claim 1 is characterized in that, the thickness of described extension conductive layer is 1/2 to 4/5 of described tunnel oxide and described floating boom thickness sum.
4. memory device as claimed in claim 1 is characterized in that, the thickness of described extension conductive layer is 2/3 of described tunnel oxide and described floating boom thickness sum.
5. a memory device manufacture method is characterized in that, comprises at least:
Semiconductor substrate is provided, and described substrate comprises grid structure at least;
Sidewall in described grid structure one side forms side wall by self-registered technology;
Side epitaxial growth at described side wall forms the extension conductive layer corresponding with described grid structure;
Deposit forms isolating oxide layer successively above described extension conductive layer, and forms the word line.
6. memory device manufacture method as claimed in claim 5 is characterized in that, described extension conductive layer is corresponding with described grid structure to refer to that described extension conductive layer and described floating boom are corresponding.
7. memory device as claimed in claim 5 is characterized in that, the thickness of described extension conductive layer is 1/2 to 4/5 of described tunnel oxide and described floating boom thickness sum.
8. memory device manufacture method as claimed in claim 5 is characterized in that, the thickness of described extension conductive layer is 2/3 of described tunnel oxide and described floating boom thickness sum.
9. memory device manufacture method as claimed in claim 5 is characterized in that, describedly forms side wall by self-registered technology and comprises: adopt chemical vapor deposition method in the sidewall growth oxide layer of described grid structure one side; Adopt self-registered technology that described oxide layer is carried out etching, form the side wall of being close to described grid structure sidewall.
10. memory device manufacture method as claimed in claim 5 is characterized in that, adopts the described extension conductive layer of selective epitaxial growth, so that described extension conductive layer is only grown at silicon face.
11. memory device manufacture method as claimed in claim 5, it is characterized in that, the described growth formation extension conductive layer corresponding with grid structure also comprises: form after the described extension conductive layer, described side wall before wet method is removed is to expose the floating boom upper side.
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| CN201210413642.5A CN102916053A (en) | 2012-10-25 | 2012-10-25 | Storage device and fabrication method of storage device |
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| CN201210413642.5A CN102916053A (en) | 2012-10-25 | 2012-10-25 | Storage device and fabrication method of storage device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465525A (en) * | 2014-12-30 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Forming method for embedded flash memory |
| CN108028255A (en) * | 2015-10-30 | 2018-05-11 | 桑迪士克科技有限责任公司 | The selection gate transistor with monocrystalline silicon for three-dimensional storage |
-
2012
- 2012-10-25 CN CN201210413642.5A patent/CN102916053A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465525A (en) * | 2014-12-30 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Forming method for embedded flash memory |
| CN108028255A (en) * | 2015-10-30 | 2018-05-11 | 桑迪士克科技有限责任公司 | The selection gate transistor with monocrystalline silicon for three-dimensional storage |
| CN108028255B (en) * | 2015-10-30 | 2022-03-15 | 桑迪士克科技有限责任公司 | Select gate transistor with single crystal silicon for three-dimensional memory |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140423 |
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Effective date of registration: 20140423 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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Application publication date: 20130206 |