CN102904572A - Method and device for correcting interleaved four-channel ADC (Analogue-to-Digital Converter) - Google Patents
Method and device for correcting interleaved four-channel ADC (Analogue-to-Digital Converter) Download PDFInfo
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- CN102904572A CN102904572A CN2012103615899A CN201210361589A CN102904572A CN 102904572 A CN102904572 A CN 102904572A CN 2012103615899 A CN2012103615899 A CN 2012103615899A CN 201210361589 A CN201210361589 A CN 201210361589A CN 102904572 A CN102904572 A CN 102904572A
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Abstract
The invention provides a method and a device for correcting an interleaved four-channel ADC (Analogue-to-Digital Converter). The corresponding method comprises the following steps of: adjusting the offsets of data acquired by four ADC cores to the numeric field 512; adjusting the gains of the data acquired by the four ADC cores to -1dBFS; and adjusting the phase differences between the data acquired by the four ADC cores to Pi/2, Pi and 3Pi/2, respectively. The method and the device realize correction of the interleaved four-channel ADC by sequentially adjusting the offsets, the gains and the phase differences of the four ADC cores, thereby avoiding the degradation of the performance indexes of the signal formed by recombining the four pieces of data.
Description
Technical field
The present invention relates to bearing calibration and the device of a kind of type four-way ADC that interweaves, belong to the Signal Collection Technology field.
Background technology
High-speed data acquisition is widely used in the fields such as radar, ultra broadband satellite communication at present, therefore picking rate and the performance index of ADC is had higher requirement.At present relatively the inside of a kind of high-speed ADC chip commonly used is by four 10bit ADC core compositions independently, and the SPI interface by standard can be configured to drainage pattern four-way, binary channels and single.
Under the four-way sampling configuration, 4 inner ADC are fully independent, finish separately the sampling of 1.25Gsps speed; Under the binary channels sampling configuration, carry out ALTERNATE SAMPLING at the rising edge of positive inversion clock, two ADC kernels combinations are finished the sampling of 2.5Gsps speed; Under the single channel sampling configuration, positive inversion clock carries out ALTERNATE SAMPLING by phase delay, four ADC kernel combinations is finished the sampling of 5Gsps speed.
But in single channel 5Gsps sample rate situation, after inner four ADC kernels are finished sampling separately, biasing between them (OFFSET), gain (GAIN) and phase place (PHASE) there are differences, and will worsen the performance index (signal to noise ratio snr, number of significant digit ENOB etc.) of signal after the data recombination.
Summary of the invention
The present invention there are differences because of biasing, gain and phase place for solving existing high-speed ADC chip inner four ADC kernels sampled data separately under the single channel sampling configuration by a plurality of ADC core compositions, cause to worsen the problem of the performance index of signal after the data recombination, and then bearing calibration and the device of a kind of type four-way ADC that interweaves are provided.For this reason, the invention provides following technical scheme:
The bearing calibration of a kind of type four-way ADC that interweaves comprises:
Numeric field 512 is all adjusted in the biasing of the data of four ADC kernels collection;
The gain of the data of described four ADC kernels collection is all adjusted to-1dBFS;
Phase difference between the data of described four ADC kernels collection is adjusted to respectively ∏/2, ∏ and 3 ∏/2.
The means for correcting of a kind of type four-way ADC that interweaves comprises:
Bias adjusting module is used for numeric field 512 is all adjusted in the biasing of the data of four ADC kernels collection;
Gain regulation module is used for the gain of the data of described four ADC kernels collection is all adjusted to-1dBFS;
Phase adjusting module is used for the phase difference between the data of described four ADC kernels collection is adjusted to respectively ∏/2, ∏ and 3 ∏/2.
Biasing, gain and the phase difference of the present invention by adjusting in order four ADC kernels realized the correction of type four-way ADC that interweaves, thereby avoids the rear performance index that worsen signal of four circuit-switched data restructuring.
Description of drawings
In order to be illustrated more clearly in the technical scheme of the embodiment of the invention, the accompanying drawing of required use was done to introduce simply during the below will describe embodiment, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the schematic flow sheet of the bearing calibration of the type four-way ADC that interweaves that provides of the specific embodiment of the present invention;
Fig. 2 is the structural representation of the means for correcting of the type four-way ADC that interweaves that provides of the specific embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
This embodiment provides the bearing calibration of a kind of type four-way ADC that interweaves, as shown in Figure 1, comprising:
Concrete, single channel 5Gsps sample rate pattern has following several:
Concrete, finish correction to the ADC biasing by the SPI interface, at first select the passage that will proofread and correct, shown in the table specific as follows:
Secondly, select biasing control register and set suitable parameter take the biasing that guarantees each passage as 512.The address of biasing control register is 0x20, and the reference value of correction is as shown in the table:
0x000 ~ 0x3FF can be quantized into little unit, the accuracy that is conducive to proofread and correct.
After the complete compensating parameter of each path setting, correcting register must be enabled, the address of enable register is 0x10, and configuration parameter is unified biasing, gain, the phase place of enabling of 0x00A8().
Concrete, finish the correction that ADC is gained by the SPI interface, secondly at first finish the selection of wanting correction channel according to step 13, select gain control register and set suitable parameter take the gain that guarantees each passage as-1dBFS, overflow when preventing the input tape bandwidth signals.The address of gain control register is 0x22, and the reference value of correction is as shown in the table:
0x000 ~ 0x3FF can be quantized into little unit, the accuracy that is conducive to proofread and correct.
After the complete compensating parameter of each path setting, correcting register must be enabled, the address of enable register is 0x10, and configuration parameter is unified biasing, gain, the phase place of enabling of 0x00A8().
If pursue simply the optimization of single frequency signal index, yield value can be configured near full scale, if when in certain specific bandwidth, using, can select centre frequency to go to proofread and correct by-1dBFS.
Concrete, finish correction to the ADC phase place by the SPI interface, at first finish the selection of wanting correction channel according to step 13, secondly selected phase control register is also set the phase difference of suitable parameter to guarantee to keep between four passages to fix.The address of phase control register is 0x24, and the reference value of correction is as shown in the table:
0x000 ~ 0x3FF can be quantized into little unit, the accuracy that is conducive to proofread and correct.
After the complete compensating parameter of each path setting, correcting register must be enabled, the address of enable register is 0x10, and configuration parameter is unified biasing, gain, the phase place of enabling of 0x00A8().
In the time of the phase calibration parameter, preferably select the highest frequency in the bandwidth, the parameter of proofreading and correct out like this can be more accurate.
In order to finish the Data correction to four ADC kernels, need a large amount of register of configuration, and after resetting, the register of ADC inside all recovers default value at every turn, therefore the FPGA RAM the inside that the parameter after proofreading and correct need to be solidified, the rear triggering software that perhaps at every turn resets reconfigures flow process.
At last, after biasing, gain, phasing are arrived above-mentioned corresponding numerical value, the analysis result after by MATLAB A, C, B, D channel data being recombinated again, errorless with the Data correction of guaranteeing four ADC kernels.
The technical scheme that adopts this embodiment to provide by biasing, gain and the phase difference of adjusting in order four ADC kernels, realizes the correction of type four-way ADC that interweaves, thereby avoids the rear performance index that worsen signal of four circuit-switched data restructuring.
Need to prove, one of ordinary skill in the art will appreciate that all or part of step that realizes in above-mentioned each embodiment of the method is to come the relevant hardware of instruction to finish by program, corresponding program can be stored in a kind of computer-readable storage medium.
The specific embodiment of the present invention also provides the means for correcting of a kind of type four-way ADC that interweaves, as shown in Figure 2, comprising:
Optionally, this device can also comprise: parameter configuration module is used for finishing the configuration of sampling configuration by standard SPI interface.
The specific implementation of the processing capacity of each module that comprises in the means for correcting of the above-mentioned type four-way ADC that interweaves is described in embodiment of the method before, no longer is repeated in this description at this.
The technical scheme that adopts this embodiment to provide by biasing, gain and the phase difference of adjusting in order four ADC kernels, realizes the correction of type four-way ADC that interweaves, thereby avoids the rear performance index that worsen signal of four circuit-switched data restructuring.
It should be noted that among the said apparatus embodiment, included modules is just divided according to function logic, but is not limited to above-mentioned division, as long as can realize corresponding function; In addition, the concrete title of each functional module also just for the ease of mutual differentiation, is not limited to protection scope of the present invention.
The above; only be the better embodiment of the present invention; but protection scope of the present invention is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the embodiment of the invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (4)
1. the bearing calibration of type four-way ADC that interweaves is characterized in that, comprising:
Numeric field 512 is all adjusted in the biasing of the data of four ADC kernels collection;
The gain of the data of described four ADC kernels collection is all adjusted to-1dBFS;
Phase difference between the data of described four ADC kernels collection is adjusted to respectively ∏/2, ∏ and 3 ∏/2.
2. the bearing calibration of the type four-way ADC that interweaves according to claim 1 is characterized in that, comprises before the biasing adjustment with the data of four ADC kernels collection:
By standard SPI interface, finish the configuration of sampling configuration.
3. the means for correcting of type four-way ADC that interweaves is characterized in that, comprising:
Bias adjusting module is used for numeric field 512 is all adjusted in the biasing of the data of four ADC kernels collection;
Gain regulation module is used for the gain of the data of described four ADC kernels collection is all adjusted to-1dBFS;
Phase adjusting module is used for the phase difference between the data of described four ADC kernels collection is adjusted to respectively ∏/2, ∏ and 3 ∏/2.
4. the means for correcting of the type four-way ADC that interweaves according to claim 3 is characterized in that, this device also comprises:
Parameter configuration module is used for finishing the configuration of sampling configuration by standard SPI interface.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113434318A (en) * | 2021-06-23 | 2021-09-24 | 山东浪潮科学研究院有限公司 | FPGA-based sampling data correction method and system |
| CN113659986A (en) * | 2021-07-20 | 2021-11-16 | 五邑大学 | ADC clock system and distribution method, eight-channel number acquisition system and control method |
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| CN1412994A (en) * | 2001-10-12 | 2003-04-23 | 华为技术有限公司 | Radio communication base band modulation circuit and its multichannel gain matching control method |
| CN101315397A (en) * | 2008-06-25 | 2008-12-03 | 中国海洋石油总公司 | Amplitude phase measuring method |
| US20090021406A1 (en) * | 2007-06-15 | 2009-01-22 | Zimmerman George A | Sub-channel distortion mitigation in parallel digital systems |
| CN102386918A (en) * | 2010-08-27 | 2012-03-21 | 英特希尔美国公司 | Calibration of impairments in a multichannel time-interleaved ADC |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1412994A (en) * | 2001-10-12 | 2003-04-23 | 华为技术有限公司 | Radio communication base band modulation circuit and its multichannel gain matching control method |
| US20090021406A1 (en) * | 2007-06-15 | 2009-01-22 | Zimmerman George A | Sub-channel distortion mitigation in parallel digital systems |
| CN101315397A (en) * | 2008-06-25 | 2008-12-03 | 中国海洋石油总公司 | Amplitude phase measuring method |
| CN102386918A (en) * | 2010-08-27 | 2012-03-21 | 英特希尔美国公司 | Calibration of impairments in a multichannel time-interleaved ADC |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113434318A (en) * | 2021-06-23 | 2021-09-24 | 山东浪潮科学研究院有限公司 | FPGA-based sampling data correction method and system |
| CN113434318B (en) * | 2021-06-23 | 2022-08-23 | 山东浪潮科学研究院有限公司 | FPGA-based sampled data correction method and system |
| CN113659986A (en) * | 2021-07-20 | 2021-11-16 | 五邑大学 | ADC clock system and distribution method, eight-channel number acquisition system and control method |
| CN113659986B (en) * | 2021-07-20 | 2024-01-09 | 五邑大学 | ADC clock system and distribution method, eight-channel number acquisition system and control method |
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