CN112187269B

CN112187269B - Variable rate analog-digital (AD) high-speed sampling circuit

Info

Publication number: CN112187269B
Application number: CN202011042969.7A
Authority: CN
Inventors: 张晓波; 赵小刚; 唐洪军; 宋云鹏
Original assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Current assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2023-02-28
Anticipated expiration: 2040-09-28
Also published as: CN112187269A

Abstract

The invention discloses a variable-rate analog-to-digital (AD) high-speed sampling circuit, and relates to the field of high-speed data transmission receivers and the like. The invention is realized by the following technical scheme: the two-channel high-speed AD chip is connected with a clock distributor and a comparator, a transformer, a filter and a DDS chip which are sequentially connected in series through the clock distributor, the two-channel high-speed AD chip finishes sampling at the rising edge of a clock, a 12-bit conversion data signal is output by adopting a direct binary code, an I/Q baseband signal of an output analog-to-digital conversion result is output to an FPGA, the FPGA updates a frequency word control write signal in real time according to requirements and then sends the updated frequency word control write signal to the DDS chip to generate a reference clock with continuously variable phase, the clock distributor converts a digital clock into a multi-channel clock and provides the multi-channel clock to the two-channel high-speed AD chip, the analog signal is sampled and converted into 4-channel digital baseband signals IA, IB, QA and QB through D/A, and the sampled data are sent to the FPGA to be demodulated.

Description

Variable rate analog-digital (AD) high-speed sampling circuit

Technical Field

The invention relates to the fields of satellite measurement and control, high-speed data transmission receivers in a communication system and the like, in particular to a variable-rate analog-digital (AD) high-speed sampling circuit.

Background

High sample rate analog-to-digital converters (ADCs) are commonly used in modern wireless receiver designs, devices that acquire complex modulated signals at Intermediate Frequency (IF) sample rates, but such ADCs employ a bufferless front end connected directly to the sampling network, which presents the problem of the input tracking and holding impedance of the amplifier driving the ADC changing over time. With the continuous development of digital communication technology, various high-speed digital communication systems have increasingly high requirements on the performance of analog-to-digital converters (ADCs), especially on the conversion accuracy and conversion time in speed.

In electronic technology, a/D converter sampling is an important part of signal processing in designing an a/D sampling circuit, and a converter a/D converter that digitally quantizes an analog signal is very complicated in kind. The core circuit of the converter of the ADC used as an interface in a control system determines the dynamic performance of the whole converter on one hand, and is directly influenced by the performance of a sampling switch on a signal path on the other hand, and the factors influencing the outside of a chip mainly comprise: the stability of power supply voltage and reference voltage, the stability of operational amplifier, ambient temperature etc. receive the chip itself to influence factors and have: resolution, quantization error, relative error. The sampling switch can introduce a large amount of nonlinear distortion due to the change of the on-resistance of the sampling switch along with the input signal, and the sampling precision of the circuit is directly influenced. While the charge injection effect and the presence of clock feedthrough in turn affect the retention accuracy of the switched load capacitance. The traditional AD sampling circuit has fixed speed and can not be changed in real time. Because the signal source of the input signal is not necessarily low impedance, the input end of the AD is likely to divide the voltage of the signal source signal, thereby affecting the precision of the acquisition and conversion signal. The AD input terminal has a capacitive load characteristic, and usually requires a resistor and a capacitor to form an external compensation circuit, and the circuit is used to add a capacitive load to the signal source. Because the precision of the voltage reference parameters of the AD integration is low, the conversion precision has a great relationship with the precision of the reference voltage, the reference voltage reference output voltage value is used for determining the full-scale input range of the data conversion system, and meanwhile, any error of the reference voltage can seriously affect the linearity and the spurious-free dynamic range of the ADC. High speed ADCs require a high duty cycle on the clock when in use. AD requires a duty cycle of CLK between 45% and 55%, which is difficult to meet if CLK is also directly used as a write signal. The selection of the channel and the range of the data acquisition circuit is determined by writing control words into the data port when the conversion is started, and the control is simple.

In the wireless broadband communication field, a high-speed data transmission receiver is a signal receiving and demodulating device for a high-speed satellite data transmission system, satellite communication usually adopts a communication mode of multiple modes and multiple data coding modes, the receiver needs to demodulate after converting analog signals into digital signals through high-speed AD sampling, the current receiver generally adopts a fixed sampling rate to sample, and AD sampling data are extracted according to different bandwidths and different coding modes and then demodulated and decoded. With the rapid development of electronic technology, new generation high speed data transmission receivers and other systems have increasingly high requirements for the number of channels, the signal transmission rate and the transmission error rate. The requirements on the bandwidth and performance of analog signal acquisition are increasing day by day, however, high-speed sampling, real-time conversion, large-capacity storage, transmission bandwidth, signal integrity and the like are bottleneck problems which restrict the design of a high-speed data transmission receiver. The increase in the speed of the acquisition system means that the sample-and-hold time, the conversion time, and the logic pulse rise-and-fall time of the high-speed digital transmission receiver signal are as short as possible, which is in conflict with the high expectations of sampling accuracy and sampled signal amplitude. Acquisition software is complex to realize, and more logic resources of devices are consumed. The conversion is started by the falling edge of a write control word write signal, and the INT end becomes low after the conversion is finished, so that the reading can be interrupted, and the reading can also be inquired. The control word can conveniently set the operating mode, including the reference mode and the sampling clock mode, and the control word is rewritten before each conversion.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides the high-speed AD sampling circuit device which has the advantages of simple circuit composition structure, real-time variable sampling rate, continuous phase and high sampling rate and supports multi-path synchronous sampling, thereby obtaining higher sampling precision and lower harmonic distortion and overcoming the problems that the traditional AD sampling circuit has fixed rate and can not be changed in real time.

The above object of the present invention can be achieved by a variable rate analog-to-digital (AD) high speed sampling circuit comprising: the high-speed AD chip of binary channels that has connected transconductance operational amplifier, the large-scale programmable gate array FPGA who connects through baseband processor, its characterized in that: a clock distributor and a comparator, a transformer, a filter and a DDS chip which are connected in series in sequence through the clock distributor are connected between two double-channel high-speed AD chips, a preceding-stage two-path operational amplifier sampling holding circuit of the two double-channel high-speed AD chips is used for voltage following, the double-channel high-speed AD chips finish sampling at the rising edge of a clock, a 12-bit conversion data signal is output by adopting a direct binary code, an I/Q baseband signal of an output analog-to-digital conversion result is output to an FPGA, the FPGA updates a frequency word control write signal in real time according to requirements and then sends the updated frequency word control write signal to the DDS chip, the DDS chip generates a continuously variable phase reference clock according to different frequency words and inputs the reference clock to the filter, a mixed frequency signal output by the DDS chip is filtered, a single-end signal is converted into a differential signal through the transformer and sent to the comparator, the analog clock is converted into a digital clock by the comparator, the clock is converted into a multi-path clock by the clock which is provided for the double-channel high-speed AD chips, the ADC is synchronously converted into a sampling clock, the double-channel AD chips are used for sampling, the analog signal sampling, the sampling of the double-channel AD chips, and the D/A is converted into a 4-channel digital baseband signal, IB, the IB, QA, the IB, the FPGA for demodulation.

Compared with the prior art, the invention has the beneficial effects that:

the circuit composition structure is simple. The invention adopts a dual-channel high-speed AD chip connected with a transconductance operational amplifier, an FPGA connected with a baseband processor, a clock distributor, a comparator, a transformer, a filter and a DDS chip which are connected in series sequentially through the clock distributor are connected between the two dual-channel high-speed AD chips, a preceding-stage two-path operational amplifier sampling and holding circuit of the two dual-channel high-speed AD chips follows the voltage, and the dual-channel high-speed AD chips finish sampling at the rising edge of the clock. The circuit composition structure is simple. The operational amplifier common mode feedback circuit adopts a switched capacitor feedback structure, the output voltage swing of the operational amplifier cannot be limited by the common mode voltage feedback circuit, and the circuit has no direct current power consumption because the operational amplifier common mode feedback circuit is completely composed of a passive device and a switch.

The sampling rate is real-time variable, and the phase is continuous. The invention adopts direct binary code to output 12-bit conversion data signals, the output analog-to-digital conversion result is sent to an IQ regulator to modulate a baseband signal I/Q (IA, IB, QA and QB) simulated by a baseband processor to an intermediate frequency spectrum, the digital signals converted by the A/D are sent to an FPGA to write control words, the control words are sent to a DD chip S after being controlled to write signals/updated by frequency words, the DDS chip generates a reference clock input filter with continuously variable phases according to different frequency words and filters a mixing signal output by the DDS chip, the digital configuration is flexible and convenient, the sampling rate is variable in real time, the phases are continuous, the acquisition precision is high, the speed is high, and the problems that the speed of the traditional AD sampling circuit is fixed and cannot be changed in real time are overcome.

The sampling rate is high. Aiming at the requirements of high precision, multi-channel signal monitoring and real-time acquisition, the invention adopts a comparator to convert an analog clock into a digital clock, a clock distributor converts the digital clock into the multi-channel clock and provides the multi-channel clock to a two-channel high-speed AD chip channel ADC for synchronous conversion to be used as a sampling clock, the two-channel high-speed AD chip samples the analog signal, the analog signal is converted into 4 channels of digital baseband signals IA, IB, QA and QB through D/A, and the sampling data is sent to an FPGA for demodulation. The FPGA controls the frequency control word of the DDS in real time according to requirements to enable the DDS to output a required clock, the clock output by the DDS eliminates interference from high frequency through a filter, a comparator compares input analog voltage with reference voltage, the analog voltage is converted into digital quantity to be output, the digital quantity is sent into a clock distributor chip to generate 2 paths of clock signals to be respectively sent to 2 high-speed ADs after the conversion speed of an A/D converter is compared, the clock signals are used as sampling clocks, and finally 4 paths of digital baseband signals I/Q (IA, IB, QA and QB) with stable amplitude are output to a baseband processor, so that the difficulty is reduced for realizing a demodulation algorithm in the FPGA. Because the speed of the satellite analog signal is continuously variable, the circuit with the sampling speed adjustable in real time is realized on hardware, the AD sampling clock can be changed in real time according to the speed of the input analog signal, the integral multiple sampling of the current analog signal speed is always kept, the extraction operation in algorithm software is not needed, and the satellite analog signal sampling circuit has lower temperature coefficient, thermal hysteresis and long-term drift. Compared with the fixed sampling clock, the method greatly saves the design time of algorithm software.

And multiple synchronous sampling is supported. The invention adopts the double-channel high-speed AD chip connected with the transconductance operational amplifier, the FPGA connected with the baseband processor is adopted, the clock distributor and the comparator, the transformer, the filter and the DDS chip which are sequentially connected in series through the clock distributor are connected between the two double-channel high-speed AD chips, the two-channel pre-stage operational amplifier sample holding circuits of the two double-channel high-speed AD chips carry out voltage following, 12-channel high-speed AD sampling is realized, the control and data processing of the chips are completed by combining the high-performance FPGA, the system requirement is realized, the acquisition of multi-channel signals can be simultaneously completed, the 6-channel ADC synchronous conversion can be realized, and the multi-channel ADC conversion sampling time is reduced.

Drawings

The invention is further described with reference to the following figures and examples.

Fig. 1 is a schematic diagram of a variable rate, high AD sampling circuit of the present invention.

The technical scheme of the invention is further described in detail in the following with reference to the attached drawings.

Detailed Description

See fig. 1. In an embodiment described below, a variable rate analog-to-digital (AD) high speed sampling circuit includes: the dual-channel high-speed AD chip connected with the transconductance operational amplifier is a large-scale programmable gate array FPGA connected through a baseband processor, and is characterized in that: a clock distributor and a comparator, a transformer, a filter and a DDS chip which are connected in series sequentially through the clock distributor are connected between two double-channel high-speed AD chips, a preceding-stage two-path operational amplifier sampling holding circuit of the two double-channel high-speed AD chips carries out voltage following, the double-channel high-speed AD chips finish sampling at the rising edge of a clock, a 12-bit conversion data signal is output by adopting a direct binary code, an I/Q baseband signal of an output analog-to-digital conversion result is output to an FPGA, the FPGA updates a frequency word control write signal in real time according to requirements and then sends the updated signal to the DDS chip, the DDS chip generates a reference clock with continuously variable phases according to different frequency words and inputs the reference clock into the filter, a mixed frequency signal output by the DDS chip is filtered, a single-end signal is converted into a differential signal through the transformer and sent to the comparator, the analog clock is converted into a digital clock, the clock by the clock distributor, the digital clock is converted into a multi-path clock and is provided to the double-channel high-speed AD chips, the ADC synchronous conversion clock is used as a sampling clock, the double-channel high-speed AD chips sample the analog signals are sampled by the double-channel AD chips, the analogue signals are converted into 4-channel digital baseband signals, and the D/A are converted into 4-D signals, and sent to the FPGA to be demodulated.

The direct digital frequency synthesizer DDS outputs a 0-1500 MHz clock according to a 3.1GHz reference clock provided by the outside and a 32-bit frequency control word input by the FPGA1, sends the clock into a filter for filtering, outputs a filtered mixing signal, and generates a sampling clock provided for a dual-channel high-speed AD analog-to-digital converter AD through a transformer, a comparator and a clock distributor.

After being amplified by the operational amplifier, the two paths of analog signals are respectively sampled by the two-channel high-speed analog-to-digital converters AD connected with the two paths of analog signals, the analog signals are converted into digital signals, meanwhile, the digital clocks are converted and divided into 2 paths of synchronous clocks by the clock distributor, the 2 paths of synchronous clocks are respectively supplied to the 2 connected two-channel high-speed AD analog-to-digital converters as sampling clocks clk, and the sampling data are internally provided with a data distributor DMUX1 through the analog-to-digital converters AD: and 2, after the speed is reduced, inputting the obtained 4 paths of IA, IB, QA and QB baseband signals and a sampling clock clk into the FPGA for demodulation through a 12-bit interface.

While the foregoing is directed to the preferred embodiment for implementing a variable rate high speed AD sampling circuit, it is to be understood that the invention is not limited to the form disclosed herein, but is not intended to be exhaustive of other embodiments and that it may be used in various other combinations, modifications, and environments and is capable of modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A variable rate analog-to-digital, AD, high speed sampling circuit, comprising: the high-speed AD chip of binary channels that has connected transconductance operational amplifier, the large-scale programmable gate array FPGA who connects through baseband processor, its characterized in that: a clock distributor and a comparator, a transformer, a filter and a DDS chip which are connected in series sequentially through the clock distributor are connected between two double-channel high-speed AD chips, a preceding-stage two-path operational amplifier sampling holding circuit of the two double-channel high-speed AD chips is used for voltage following, the double-channel high-speed AD chips finish sampling at the rising edge of a clock, a 12-bit conversion data signal is output by adopting a direct binary code, an I/Q baseband signal of an output analog-to-digital conversion result is output to an FPGA, the FPGA updates a frequency word control write signal in real time according to requirements and then sends the updated frequency word control write signal to the DDS chip, the DDS chip generates a reference clock with continuously variable phases according to different frequency words and inputs the reference clock into the filter, a mixed frequency signal output by the DDS chip is filtered, a single-end signal is converted into a differential signal through the transformer and sent to the comparator, the analog clock is converted into a digital clock, the clock by the clock distributor, the digital clock is converted into a multi-path clock which is provided to the double-channel high-speed AD chip, the ADC synchronous conversion is used as a sampling clock, the double-channel AD chip is used for sampling clock, the double-channel AD chip for sampling, the sampling of the analogue signal, the double-channel AD chip is used for sampling, and is converted into a 4-channel digital baseband signal, and then the D/A is converted into a 4-D signal, IB, QB, and the FPGA for demodulating the sampling data.

2. The variable rate analog-to-digital (AD) high speed sampling circuit of claim 1, wherein: the DDS outputs a 0-1500 MHz clock to be sent to a filter for filtering according to an externally provided and input 3.1GHz reference clock and 32-bit frequency control words input by the FPGA1, outputs a filtered mixed frequency signal, and generates a sampling clock which is provided for a two-channel high-speed AD analog-to-digital converter (AD) through a transformer, a comparator and a clock distributor.

3. The variable rate analog-to-digital (AD) high speed sampling circuit of claim 1, wherein: after being amplified by the operational amplifier, the two paths of analog signals are respectively sampled by the two-channel high-speed analog-to-digital converters AD connected with the two paths of analog signals, the analog signals are converted into digital signals, meanwhile, the digital clocks are converted and divided into 2 paths of synchronous clocks by the clock distributor, the 2 paths of synchronous clocks are respectively supplied to the 2 connected two-channel high-speed AD analog-to-digital converters as sampling clocks clk, and the sampling data are internally provided with a data distributor DMUX1 through the analog-to-digital converters AD: and 2, after the speed is reduced, inputting the obtained 4 paths of IA, IB, QA and QB baseband signals and a sampling clock clk into the FPGA for demodulation through a 12-bit interface.