CN113553291A - System, method, device, equipment and storage medium for data sampling - Google Patents
System, method, device, equipment and storage medium for data sampling Download PDFInfo
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Abstract
The embodiment of the invention discloses a system, a method, a device, equipment and a storage medium for data sampling, wherein the system comprises a Field Programmable Gate Array (FPGA), a first clock generation module and an analog-to-digital conversion module; the FPGA is used for receiving a first configuration instruction, generating a clock generation signal according to the first configuration instruction and sending the clock generation signal to the first clock generation module; the first clock generation module is used for generating a first target clock signal according to the clock generation signal and sending the first target clock signal to the analog-to-digital conversion module; and the analog-to-digital conversion module is used for sampling based on the frequency of the first target clock signal. The embodiment of the invention can flexibly adjust the sampling rate based on the requirement of a user and meet the condition of sampling by using a special sampling rate.
Description
Technical Field
The present invention relates to the field of data acquisition, and in particular, to a system, method, apparatus, device, and storage medium for data sampling.
Background
With the development of information technology, especially the improvement of processing speed of various digital processors, people have higher and higher requirements on data acquisition systems, and especially in some occasions where a large amount of data acquisition needs to be completed in a very short time, very high requirements are put forward on the speed and the acquisition precision of the data acquisition systems.
At present, the acquisition and monitoring of some weak signals are finished by a high-precision digital-to-analog conversion chip, so that powerful guarantee is provided for the real-time performance and the accuracy of measured data.
However, the existing data acquisition system has a small output sampling rate, and can only use a fixed sampling rate for sampling, and the sampling rate cannot be flexibly adjusted based on the requirements of users.
Disclosure of Invention
The embodiment of the invention provides a system, a method, a device, equipment and a storage medium for data sampling, which solve the problem that the sampling rate can not be flexibly adjusted based on the requirements of users at present.
In order to solve the technical problems, the invention comprises the following steps:
in a first aspect, a system for data sampling is provided, which includes a Field Programmable Gate Array (FPGA), a first clock generation module, and an analog-to-digital conversion module;
the FPGA is used for receiving the first configuration instruction, generating a clock generation signal according to the first configuration instruction and sending the clock generation signal to the first clock generation module;
the first clock generation module is used for generating a first target clock signal according to the clock generation signal and sending the first target clock signal to the analog-to-digital conversion module;
and the analog-to-digital conversion module is used for sampling based on the frequency of the first target clock signal.
In some implementations of the first aspect, the FPGA includes a second clock generation module; the FPGA is also used for receiving a second configuration instruction;
the second clock generation module is used for generating a second target clock signal according to the second configuration instruction and sending the second target clock signal to the analog-to-digital conversion module;
and the analog-to-digital conversion module is also used for sampling based on the frequency of the second target clock signal.
In some implementations of the first aspect, the FPGA further comprises a data storage module;
and the data storage module is used for storing the data acquired by the analog-to-digital conversion module.
In some implementations of the first aspect, the FPGA further comprises a reset module;
and the reset module is used for resetting the clock generation signal, the second target clock signal and the data stored by the data storage module.
In a second aspect, a method for sampling data is provided, which is applied to an FPGA, and the method includes:
receiving a first configuration instruction;
and generating a clock generation signal according to the first configuration instruction, sending the clock generation signal to the first clock generation module, and generating a first target clock signal according to the clock generation signal by the first clock generation module and sending the first target clock signal to the analog-to-digital conversion module so that the analog-to-digital conversion module performs sampling based on the frequency of the first target clock signal.
In some implementations of the second aspect, the method includes:
receiving a second configuration instruction;
and generating a second target clock signal according to the second configuration instruction, and sending the second target clock signal to the analog-to-digital conversion module for sampling by the analog-to-digital conversion module based on the frequency of the second target clock signal.
In some implementations of the second aspect, the method further comprises:
and storing the data collected by the analog-to-digital conversion module.
In a third aspect, an apparatus for sampling data is provided, the apparatus comprising:
the receiving module is used for receiving a first configuration instruction;
the clock generation signal generation module is used for generating a clock generation signal according to the first configuration instruction, sending the clock generation signal to the first clock generation module, generating a first target clock signal according to the clock generation signal by the first clock generation module, and sending the first target clock signal to the analog-to-digital conversion module so that the analog-to-digital conversion module performs sampling based on the frequency of the first target clock signal.
In some implementations of the third aspect, the apparatus further includes a clock generation module;
the receiving module is also used for receiving a second configuration instruction;
the clock generating module is further configured to generate a second target clock signal according to the second configuration instruction, and send the second target clock signal to the analog-to-digital conversion module, so that the analog-to-digital conversion module performs sampling based on the frequency of the second target clock signal.
In some implementations of the third aspect, the apparatus further includes a storage module;
and the storage module is used for storing the data acquired by the analog-to-digital conversion module.
In a fourth aspect, an electronic device is provided, the device comprising: a processor and a memory storing computer program instructions;
the second aspect is implemented when a processor executes computer program instructions, and a method of data sampling in some implementations of the second aspect.
In a fifth aspect, there is provided a computer storage medium having computer program instructions stored thereon that, when executed by a processor, implement the second aspect, and methods of data sampling in some implementations of the second aspect.
The embodiment of the invention provides a system, a method, a device, equipment and a storage medium for data sampling. The system comprises an FPGA, a first clock generation module and an analog-to-digital conversion module; the FPGA is used for receiving a first configuration instruction, generating a clock generation signal according to the first configuration instruction and sending the clock generation signal to the first clock generation module; the first clock generation module is used for generating a first target clock signal according to the clock generation signal and sending the first target clock signal to the analog-to-digital conversion module; and the analog-to-digital conversion module is used for sampling based on the frequency of the first target clock signal. The FPGA can control the first clock generation module to generate the first target clock signal corresponding to the first configuration instruction according to the received first configuration instruction so that the analog-to-digital conversion module samples based on the frequency of the first target clock signal, and therefore the clock signal corresponding to the analog-to-digital conversion module can be generated according to the configuration instruction to sample, the sampling rate can be flexibly adjusted based on the requirement of a user, and the condition that sampling is carried out by using a special sampling rate can be met.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a system for sampling data according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a system for sampling data according to a normal sampling rate according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a system for sampling data according to a specific sampling rate according to an embodiment of the present invention;
FIG. 4 is a flow chart illustrating a method for sampling data according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an apparatus for data sampling according to an embodiment of the present invention;
fig. 6 is a block diagram of a computing device provided by an embodiment of the invention.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
With the development of information technology, especially the improvement of the processing speed of various digital processors, people have higher and higher requirements on a data acquisition system, and especially in some occasions needing to finish the acquisition of a large amount of data in a very short time, very high requirements on the speed of the data acquisition system are put forward; in addition, very high requirements are placed on the data acquisition accuracy.
At present, acquisition and monitoring of some weak signals are completed by a high-precision Digital-to-Digital (AD) conversion chip, so that strong guarantee is provided for real-time performance and accuracy of measured data.
However, the existing data acquisition system has a low output sampling rate, and can only use a common sampling rate for sampling, for example, 25.6 kilo Samples per Second (Ksps), but cannot use a special sampling rate, for example, 25.7Ksps for sampling, and therefore, only can satisfy some application occasions, and cannot satisfy some special application occasions. In other words, the prior art can only use a fixed sampling rate for sampling, and cannot flexibly adjust the sampling rate based on the requirements of users, and the sampling rate is single.
In order to solve the problem that a data acquisition system cannot flexibly adjust the sampling rate based on the requirements of users in the existing scheme, the embodiment of the invention provides a data sampling system, a method, a device, equipment and a storage medium, wherein the system comprises an FPGA, a first clock generation module and an analog-to-digital conversion module; the FPGA is used for receiving a first configuration instruction, generating a clock generation signal according to the first configuration instruction and sending the clock generation signal to the first clock generation module; the first clock generation module is used for generating a first target clock signal according to the clock generation signal and sending the first target clock signal to the analog-to-digital conversion module; and the analog-to-digital conversion module is used for sampling based on the frequency of the first target clock signal. Because the FPGA can control the first clock generation module to generate the first target clock signal corresponding to the first configuration instruction according to the received first configuration instruction, so that the analog-to-digital conversion module performs sampling based on the frequency of the first target clock signal, the data acquisition system can generate the corresponding clock signal according to the configuration instruction to perform sampling, and therefore, the sampling rate can be flexibly adjusted based on the user's requirement, and the situation of performing sampling by using a special sampling rate can be satisfied.
The technical solutions provided by the embodiments of the present invention are described below with reference to the accompanying drawings.
Fig. 1 is a structural diagram of a data sampling system according to an embodiment of the present invention, and as shown in fig. 1, the system includes an FPGA, a first clock generation module, and an analog-to-digital conversion module.
The FPGA is used for receiving a first configuration instruction, generating a clock generation signal according to the first configuration instruction, and sending the clock generation signal to the first clock generation module.
And the first clock generation module is used for generating a first target clock signal according to the clock generation signal and sending the first target clock signal to the analog-to-digital conversion module.
And the analog-to-digital conversion module is used for sampling based on the frequency of the first target clock signal.
According to the data sampling system comprising the FPGA, the first clock generation module and the analog-to-digital conversion module, the FPGA can control the first clock generation module to generate the first target clock signal corresponding to the first configuration instruction according to the received first configuration instruction so that the analog-to-digital conversion module can perform sampling based on the frequency of the first target clock signal and send the acquired data to the FPGA, so that the system can generate the corresponding clock signal according to the configuration instruction to perform sampling, the sampling rate can be flexibly adjusted based on the requirement of a user, and the condition of performing sampling by using a special sampling rate can be met.
In order to enable the data sampling system to perform sampling not only by using a special sampling rate but also by using a normal sampling rate, in one embodiment, the data sampling system may perform sampling according to the normal sampling rate, and in the normal sampling system, the FPGA further includes a second clock generation module.
And the FPGA is also used for receiving a second configuration instruction.
And the second clock generation module is used for generating a second target clock signal according to the second configuration instruction and sending the second target clock signal to the analog-to-digital conversion module.
And the analog-to-digital conversion module is also used for sampling based on the frequency of the second target clock signal so as to realize sampling by using a normal sampling rate.
In one embodiment, in order to store the data collected by the analog-to-digital conversion module, a data storage module may be further included in the data sampling system.
And the data storage module can be used for storing the data acquired by the analog-to-digital conversion module.
In a specific example, the analog-to-Digital conversion module may be an AD7768 chip, the first clock generation module may be a Direct Digital Synthesis (DDS) chip, and the second clock generation module may be a clock unit in the FPGA processor, that is, a system clock built in the FPGA processor.
In order to reset the data in the data sampling system, the data sampling system may further include a reset module configured to reset the clock generation signal, the second target clock signal, and the data stored in the data storage module.
Under the condition that the first clock generation module is a DDS chip, actually generating a clock generation signal in the FPGA is a DDS chip configuration unit in the FPGA, and the DDS chip configuration unit is mainly used for realizing that the DDS chip outputs different clock frequencies for an AD7768 chip system clock; under the condition that the analog-to-digital conversion module is an AD7768 chip, the FPGA receiving the data acquired by the analog-to-digital conversion module is an AD7768 acquisition unit in the FPGA, and the AD7768 acquisition unit is mainly used for realizing data acquisition, data bit width conversion and asynchronous clock domain processing functions of the AD7768 chip.
In a specific example, to understand the sampling principle of the analog-to-digital conversion module, the sampling principle of the AD7768 chip is described based on the example that the analog-to-digital conversion module is the AD7768 chip.
According to the data manual of the AD7768 chip, the AD7768 chip can output a sampling rate of 256KSPS at most, and the sampling rate control formula of the AD7768 chip is as follows: ODR (sampling rate) ═ modulator rate/decimation rate, modulator rate: ADC _ MCLK/ADC _ MODE.
In the sampling rate control formula of the AD7768 chip, ADC _ MCLK is the system clock of the AD7768 chip, ADC _ MODE is the AD7768 working MODE, and the AD7768 working MODE is shown in Table 1; decimation rates ADC _ DE, AD7768 the decimation rates are shown in table 2.
TABLE 1
| Mode of operation | Working MODE control pin MODE | Modulation rate |
| Gao Su | 0x0 | MCLK/4 |
| Medium speed | 0x4 | MCLK/8 |
| Low speed | 0x8 | MCLK/32 |
TABLE 2
In the process that a data sampling system samples according to a normal sampling rate, the AD7768 chip is controlled to output different sampling rates mainly by changing the clock frequency, the working mode and the extraction rate of the AD7768 chip system. In a specific embodiment, 3 clocks can be output by using the internal clock of the FPGA for clock selection of the AD7768 chip, as shown in fig. 2, the 3 clocks can be 32.768MHz, 16.384MHz, and 8.192MHz, respectively; and then, selecting a clock by a clock selector in the FPGA to output to an AD7768 chip for sampling, wherein different sampling rates output by the AD7768 controlled by the FPGA are shown in a table 3.
TABLE 3
In actual project or product application, the AD7768 chip is required to output a non-integer sampling rate for sampling, for example, sampling rates such as 1.6KSPS, 2.56KSPS, 6.4KSPS, 12.8KSPS, 25.6KSPS, and 51.2KSPS, but in the above sampling process according to the normal sampling rate, only a normal (integer) sampling rate can be output for sampling. Therefore, in an embodiment, the data sampling system may perform sampling according to a special sampling rate, and in a specific process of performing sampling according to the special sampling rate, as shown in fig. 3, the FPGA processor in the data sampling system configures a DDS chip through a Serial Peripheral Interface (SPI) bus, so that the DDS chip outputs clocks with different frequencies to allow an AD7768 chip to output analog-to-digital conversion data with different sampling rates to perform data acquisition, so as to implement that the data sampling system flexibly adjusts the sampling rate based on a user's requirement to perform sampling, and meet a condition of performing sampling using the special sampling rate.
In a specific example, the FPGA processor in the data sampling system controls the AD7768 chip to output a specific sampling rate for sampling, and may output sampling rates of 6.4KSPS, 6.5KSPS, 12.8KSPS, 25.6KSPS, and the like for sampling.
It should be additionally explained that the DDS chip can be used in this design as long as it can output different clock frequencies, for example, the AD9951 chip, but the DDS chip is not limited to the AD9951 chip.
According to the data sampling system provided by the embodiment of the invention, the FPGA can control the first clock generation module to generate the first target clock signal corresponding to the first configuration instruction according to the received first configuration instruction, so that the analog-to-digital conversion module samples based on the frequency of the first target clock signal and sends the acquired data to the FPGA, and therefore, the system can generate the corresponding clock signal according to the configuration instruction to sample, the sampling rate can be flexibly adjusted based on the requirement of a user, and the condition of sampling by using a special sampling rate can be met. In addition, a second clock generation module included in the FPGA can be used for generating a second target clock signal, so that the analog-to-digital conversion module performs sampling based on the frequency of the second target clock signal, and the sampling based on the normal sampling rate can be compatibly realized.
Corresponding to the data sampling system in fig. 1, the embodiment of the present invention further provides a data sampling method.
Fig. 4 is a schematic flowchart of a method for data sampling according to an embodiment of the present invention, where the method is applied to a field programmable gate array FPGA, and as shown in fig. 4, the method for data sampling may include:
s101: a first configuration instruction is received.
S102: and generating a clock generation signal according to the first configuration instruction, sending the clock generation signal to the first clock generation module, and generating a first target clock signal according to the clock generation signal by the first clock generation module and sending the first target clock signal to the analog-to-digital conversion module so that the analog-to-digital conversion module performs sampling based on the frequency of the first target clock signal.
According to the data sampling method provided by the embodiment of the invention, the FPGA can control the first clock generation module to generate the first target clock signal corresponding to the first configuration instruction according to the received first configuration instruction so as to be used for the analog-to-digital conversion module to sample based on the frequency of the first target clock signal, so that the method can generate the corresponding clock signal according to the configuration instruction to sample, the sampling rate can be flexibly adjusted based on the requirement of a user, and the condition of sampling by using a special sampling rate can be met.
In order to make the method of sampling data compatible with sampling using not only a special sampling rate but also a normal sampling rate, in one embodiment, the method further comprises:
receiving a second configuration instruction;
and generating a second target clock signal according to the second configuration instruction, and sending the second target clock signal to the analog-to-digital conversion module for sampling by the analog-to-digital conversion module based on the frequency of the second target clock signal.
In one embodiment, to store the collected data, the method further comprises:
and storing the data collected by the analog-to-digital conversion module.
According to the data sampling method provided by the embodiment of the invention, the FPGA can control the first clock generation module to generate the first target clock signal corresponding to the first configuration instruction according to the received first configuration instruction, so that the analog-to-digital conversion module performs sampling based on the frequency of the first target clock signal and sends the acquired data to the FPGA, and therefore, the method can generate the corresponding clock signal according to the configuration instruction to perform sampling, the sampling rate can be flexibly adjusted based on the requirement of a user, and the condition of performing sampling by using a special sampling rate can be met. In addition, a second target clock signal can be generated according to a second configuration instruction, so that the analog-to-digital conversion module performs sampling based on the frequency of the second target clock signal, and the sampling based on the normal sampling rate can be compatibly realized.
Corresponding to the data sampling method in fig. 4, the embodiment of the present invention further provides a data sampling apparatus.
Fig. 5 is a schematic structural diagram of an apparatus for data sampling according to an embodiment of the present invention, and as shown in fig. 5, the apparatus for data sampling may include: a receiving module 201 and a clock generation signal generation module 202.
The receiving module 201 may be configured to receive a first configuration instruction.
The clock generation signal generation module 202 may be configured to generate a clock generation signal according to the first configuration instruction, send the clock generation signal to the first clock generation module, and generate a first target clock signal according to the clock generation signal and send the first target clock signal to the analog-to-digital conversion module, so that the analog-to-digital conversion module performs sampling based on the frequency of the first target clock signal.
According to the data sampling device provided by the embodiment of the invention, the first clock generation module can be controlled to generate the first target clock signal corresponding to the first configuration instruction according to the received first configuration instruction, so that the analog-to-digital conversion module can perform sampling based on the frequency of the first target clock signal, and therefore, the device can generate the corresponding clock signal according to the configuration instruction to perform sampling, the sampling rate can be flexibly adjusted based on the requirement of a user, and the condition of performing sampling by using a special sampling rate can be met.
In one embodiment, the data sampling device further comprises a clock generation module;
the receiving module 201 is further configured to receive a second configuration instruction.
The clock generating module is further configured to generate a second target clock signal according to the second configuration instruction, and send the second target clock signal to the analog-to-digital conversion module, so that the analog-to-digital conversion module performs sampling based on the frequency of the second target clock signal.
In one embodiment, the data sampling apparatus further includes a storage module (not shown in the figure) for storing the data collected by the analog-to-digital conversion module.
According to the data sampling device provided by the embodiment of the invention, the first clock generation module can be controlled to generate the first target clock signal corresponding to the first configuration instruction according to the received first configuration instruction, so that the analog-to-digital conversion module can perform sampling based on the frequency of the first target clock signal, and therefore, the method can generate the corresponding clock signal according to the configuration instruction to perform sampling, the sampling rate can be flexibly adjusted based on the requirement of a user, and the condition of performing sampling by using a special sampling rate can be met. In addition, a second target clock signal can be generated according to a second configuration instruction, so that the analog-to-digital conversion module performs sampling based on the frequency of the second target clock signal, and the sampling based on the normal sampling rate can be compatibly realized.
Fig. 6 is a block diagram of a hardware architecture of a computing device according to an embodiment of the present invention. As shown in fig. 6, computing device 600 includes an input interface 601, an FPGA-based data acquisition system 602, and a display device 603. The input interface 601, the FPGA-based data acquisition system 602, and the display device 603 are connected to each other via a bus 610.
Specifically, the input interface 601 receives a first configuration instruction input by an external user, and transmits the first configuration instruction to the data acquisition system 602; the FPGA in the data acquisition system 602 generates a clock generation signal according to the first configuration instruction, and sends the clock generation signal to the first clock generation module in the data acquisition system 602, so that the first clock generation module generates a first target clock signal according to the clock generation signal and sends the first target clock signal to the analog-to-digital conversion module in the data acquisition system 602, so that the analog-to-digital conversion module performs sampling based on the frequency of the first target clock signal, and then performs display through the display device 603 for a user to use.
That is, the computing device shown in fig. 6 may also be implemented as a data sampling device that may include: a processor and a memory storing computer executable instructions; the processor, when executing the computer-executable instructions, may implement the method of data sampling provided by embodiments of the present invention.
An embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium has computer program instructions stored thereon; the computer program instructions, when executed by a processor, implement a method of data sampling as provided by embodiments of the present invention.
It is to be understood that the invention is not limited to the specific arrangements and instrumentality described above and shown in the drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present invention are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications and additions or change the order between the steps after comprehending the spirit of the present invention.
The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic Circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the invention are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of machine-readable media include electronic circuits, semiconductor Memory devices, Read-Only memories (ROMs), flash memories, Erasable Read-Only memories (EROMs), floppy disks, Compact disk Read-Only memories (CD-ROMs), optical disks, hard disks, optical fiber media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.
It should also be noted that the exemplary embodiments mentioned in this patent describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.
Aspects of the present disclosure are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware for performing the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As described above, only the specific embodiments of the present invention are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention.
Claims (12)
1. A data sampling system is characterized by comprising a Field Programmable Gate Array (FPGA), a first clock generation module and an analog-to-digital conversion module;
the FPGA is used for receiving a first configuration instruction, generating a clock generation signal according to the first configuration instruction and sending the clock generation signal to the first clock generation module;
the first clock generation module is configured to generate a first target clock signal according to the clock generation signal, and send the first target clock signal to the analog-to-digital conversion module;
the analog-to-digital conversion module is used for sampling based on the frequency of the first target clock signal.
2. The system of claim 1, wherein the FPGA comprises a second clock generation module; the FPGA is also used for receiving a second configuration instruction;
the second clock generation module is configured to generate a second target clock signal according to the second configuration instruction, and send the second target clock signal to the analog-to-digital conversion module;
the analog-to-digital conversion module is further configured to sample based on the frequency of the second target clock signal.
3. The system of claim 1 or 2, wherein the FPGA further comprises a data storage module;
and the data storage module is used for storing the data acquired by the analog-to-digital conversion module.
4. The system of claim 3, wherein the FPGA further comprises a reset module;
the reset module is used for resetting the clock generation signal, the second target clock signal and the data stored in the data storage module.
5. A method for sampling data is applied to a Field Programmable Gate Array (FPGA), and the method comprises the following steps:
receiving a first configuration instruction;
and generating a clock generation signal according to the first configuration instruction, and sending the clock generation signal to a first clock generation module, where the first clock generation module generates a first target clock signal according to the clock generation signal and sends the first target clock signal to an analog-to-digital conversion module, so that the analog-to-digital conversion module performs sampling based on the frequency of the first target clock signal.
6. The method of claim 5, wherein the method comprises:
receiving a second configuration instruction;
and generating a second target clock signal according to the second configuration instruction, and sending the second target clock signal to the analog-to-digital conversion module for the analog-to-digital conversion module to perform sampling based on the frequency of the second target clock signal.
7. The method of claim 5 or 6, further comprising:
and storing the data collected by the analog-to-digital conversion module.
8. An apparatus for sampling data, the apparatus comprising:
the receiving module is used for receiving a first configuration instruction;
and the clock generation signal generation module is used for generating a clock generation signal according to the first configuration instruction, sending the clock generation signal to the first clock generation module, and generating a first target clock signal according to the clock generation signal and sending the first target clock signal to the analog-to-digital conversion module by the first clock generation module so that the analog-to-digital conversion module performs sampling based on the frequency of the first target clock signal.
9. The apparatus of claim 8, further comprising a clock generation module;
the receiving module is further configured to receive a second configuration instruction;
the clock generating module is further configured to generate a second target clock signal according to the second configuration instruction, and send the second target clock signal to the analog-to-digital conversion module, so that the analog-to-digital conversion module performs sampling based on the frequency of the second target clock signal.
10. The apparatus of claim 8 or 9, further comprising a storage module;
and the storage module is used for storing the data acquired by the analog-to-digital conversion module.
11. An electronic device, characterized in that the device comprises: a processor and a memory storing computer program instructions;
the processor, when executing the computer program instructions, implements a method of data sampling as claimed in any of claims 5-7.
12. A computer storage medium having computer program instructions stored thereon which, when executed by a processor, implement a method of data sampling as claimed in any one of claims 5 to 7.
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