CN105429642B - A method of improving data collecting system dynamic range - Google Patents
A method of improving data collecting system dynamic range Download PDFInfo
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- CN105429642B CN105429642B CN201510891681.XA CN201510891681A CN105429642B CN 105429642 B CN105429642 B CN 105429642B CN 201510891681 A CN201510891681 A CN 201510891681A CN 105429642 B CN105429642 B CN 105429642B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/188—Multi-path, i.e. having a separate analogue/digital converter for each possible range
Abstract
The invention belongs to data acquisition technology field, the method for being related specifically to analog-digital converter ADC dynamic ranges in raising data collecting system.A method of data collecting system dynamic range is improved, is included the following steps：The analog signal that data collecting system receives is divided into the roads n parallel signal, wherein n >=2；The roads n parallel signal is subjected to not equal amplitude scaling respectively, an ADC is respectively connected per signal all the way after being scaled through amplitude；Data after quantifying to multi-channel A/D C parallel samplings, are restored by corresponding amplitude in numeric field and data dynamic restructuring algorithm revert to single-channel sampling signal again.The present invention uses less ADC, increase can quantized signal amplitude range, while ensure that the quantified precision to small signal, overcome single ADC high sampling rates and high-resolution contradiction restricting relation, improve the dynamic range of data collecting system.
Description
Technical field
The invention belongs to data acquisition technology field, it is related specifically to improve analog-digital converter ADC in data collecting system
The method of dynamic range.
Background technology
The dynamic range of data collecting system refers to the ratio of the peak signal that ADC can quantify and minimum signal.ADC is
Core cell in data collecting system, its highest sample rate directly influences the bandwidth of acquisition system, and resolution ratio is to adopting
The dynamic range of collecting system plays decisive role.ADC devices are by realization principle and manufacturing process due to being limited in reality,
Sample rate and resolution ratio are a pair of conflicting index always.It is closed to overcome the contradiction between sample rate and resolution ratio to restrict
System, the ADC parallel sampling technologies based on multichannel have obtained certain application.
A kind of common form is known as time-interleaved sampling technique, as described in patent CN201320066816.5, pass through by
The ADC parallel samplings that the multi-channel sampling time is staggered, then sequentially in time synthesize multi-channel sampling data so that data
The sample rate of acquisition system further increases.This method will not change the resolution ratio of acquisition system, cannot improve its dynamic model
It encloses.
Document《A kind of the parallel combined sampling system signal reconfiguring method》（The 2014, the 30th phase of aerospace electronic warfare）It devises
A kind of the parallel combined sampling system is spliced by the range of multiple ADC to realize dynamic range expansion.It is this simple by increasing
The mode of ADC quantity is to the raising limitation of Dynamic Range, and when the quantity of ADC doubles, dynamic range is only capable of
The surge of the difficulty and cost in cloth line locking can be brought, be unfavorable for reality if the ADC of parallel sampling is more by improving 6dB
Project Realization.
Invention content
The present invention is intended to provide a kind of new method improving data collecting system dynamic range.
Technical program of the present invention lies in：
A method of data collecting system dynamic range is improved, is included the following steps：
（1）The analog signal that data collecting system receives is divided into the roads n parallel signal by power splitter, wherein n >=2；
（2）The roads n parallel signal is subjected to not equal amplitude scaling respectively, it is equal per signal all the way after being scaled through amplitude
It is separately connected an ADC；
（3）To multi-channel A/D C parallel samplings quantify after data, numeric field restored by corresponding amplitude and data dynamic
Restructing algorithm reverts to single-channel sampling signal again.
The same clock source of multi-channel A/D C connections.
After the amplitude scaling not waited in progress, it is additionally provided with simulation time delay adjustment circuit before into ADC.
The clock source is the additional phase-locked loop circuit PLL of low jitter High Precision Crystal Oscillator.
It is described after the quantization of multi-channel A/D C parallel samplings, time delay adjustment is also carried out by digital processing mode.
The digital processing mode is data buffer storage alignment and data interpolating, wherein data interpolating refers to passing through data
The sample point data for the correct position that the original sampling data of acquisition system generates.
The data dynamic restructuring algorithm is excellent in the case where signal is not limited according to minimum quantization error criterion
First select the channel sampled data of quantization error minimum.
The technical effects of the invention are that：
The dynamic range of data collecting system refers to the ratio of the peak signal that ADC can quantify and minimum signal.This hair
Bright that sampled signal is divided into the roads n, n >=2, each channel carries out different degrees of scaling to signal amplitude and improves, and use is fewer
The ADC of amount, increase can quantized signal amplitude range, while ensure that the quantified precision of small signal, number greatly improved
According to the dynamic range of acquisition system.Preferably, it is eliminated by being controlled using same clock source all ADC and being adjusted by time delay
Time delay error between each channel, to ensure that multidiameter delay sampled signal can be reconstructed into low distortion signal all the way.
Description of the drawings
Fig. 1 is data collecting system schematic diagram of the present invention.
Fig. 2 is signal interpolation time delay adjustment schematic diagram.
Specific implementation mode
A method of data collecting system dynamic range being improved, detailed process is shown in Fig. 1.Include the following steps：
（1）The analog signal that data collecting system receives is divided into the roads n parallel signal, n >=2；
（2）The roads n parallel signal is subjected to not equal amplitude scaling respectively, it is equal per signal all the way after being scaled through amplitude
It is separately connected an ADC；
（3）To multi-channel A/D C parallel samplings quantify after data, numeric field restored by corresponding amplitude and data dynamic
Restructing algorithm reverts to single-channel sampling signal again, wherein data dynamic restructuring algorithm is being believed according to minimum quantization error criterion
In the case of number not being limited, the preferential channel sampled data for selecting quantization error minimum.
Wherein, multi-channel A/D C is also associated with same clock source.After the amplitude scaling do not wait, gone back before into ADC
Equipped with simulation time delay adjustment circuit.Clock source is the additional phase-locked loop circuit PLL of low jitter High Precision Crystal Oscillator.Through multi-channel A/D C simultaneously
After row sample quantization, time delay adjustment is also carried out by digital processing mode, wherein digital processing mode be data buffer storage alignment and
Data interpolating, wherein data interpolating refers to the sampling of the correct position generated by the original sampling data of data collecting system
Point data.Specific schematic diagram is shown in Fig. 1.
Embodiment 1
It is illustrated with n=2 liang channel parallel sampling system：
The analog signal of reception is sent into power splitter, is divided into 2 road parallel signals, is contracted respectively into line amplitude to two paths of signals
It puts.I.e. channel 1 connects ADC1 after passing sequentially through signal conditioning circuit 1 and simulation time delay adjustment circuit 1；Channel 2 passes sequentially through
ADC2 is connected after signal conditioning circuit 2 and simulation time delay adjustment circuit 2；Wherein, signal conditioning circuit 1 is sequentially connected declines
Subtract device and limiter 1, signal conditioning circuit 2 is sequentially connected gain-programmed amplifier and limiter 2.Wherein, amplitude limit
The full scale value for being dimensioned to ADC of device 1 and limiter 2.I.e. channel 1 carries out amplitude compression by attenuator 1 to signal, leads to
Signal is amplified into line amplitude by gain-programmed amplifier 2 in road 2.
After conditioning, it is equivalent to range and larger quantization interval of the 1 corresponding ADC of channel with bigger, it is special to measure
Change big signal, 2 corresponding ADC of channel has smaller range and smaller quantized interval, specially quantifies small signal.ADC is sampled
Two paths of data after quantization, is restored by corresponding amplitude and data dynamic restructuring algorithm reverts to single-channel sampling signal again,
Complete the extension of dynamic range.Wherein the dynamic restructuring algorithm is not limited in signal according to minimum quantization error criterion
In the case of width, the preferential channel sampled data for selecting quantization error minimum.It is assumed that channel 1 decays to signalP DB, channel 2
Signal is exaggeratedQ DB, then the dynamic range of data collecting system can be improvedP+QdB。
Data collecting system not high to sample rate, synchronization accuracy is of less demanding, the letter after signal conditioning circuit
Number enter ADC before, by simulate time delay adjustment circuit to signal carry out time delay error adjustment.
Meanwhile the same clock source of ADC1 and ADC2 connections, clock source use the additional phaselocked loop of low jitter High Precision Crystal Oscillator
Circuit PLL is provided.
Embodiment 2
As different from Example 1, under high-speed data acquistion system, synchronization accuracy requires to improve, by simulating time delay
After the adjustment of adjustment circuit, it is possible to time delay or phase error that residual is certain.Digital signal can be used in numeric field at this time
The mode of processing is adjusted.The time delay in integral multiple sampling interval can be corrected by way of data buffer storage alignment；For small
It in the score times time delay in 1 sampling interval, needs to be adjusted by the way of data interpolating, as shown in Fig. 2, passing through data
The sampled point for the correct position that the original sampling data of acquisition system generates.Other steps are same as Example 1.
Claims (7)
1. a kind of method improving data collecting system dynamic range, it is characterised in that：Include the following steps
（1）The analog signal that data collecting system receives is divided into the roads n parallel signal, wherein n >=2；
（2）The roads n parallel signal is subjected to not equal amplitude scaling respectively, every signal all the way after being scaled through amplitude is respectively
Connect an ADC；
（3）Data after quantifying to multi-channel A/D C parallel samplings are restored and data dynamic restructuring in numeric field by corresponding amplitude
Algorithm reverts to single-channel sampling signal again.
2. a kind of method improving data collecting system dynamic range according to claim 1, it is characterised in that：Described
Multi-channel A/D C is also associated with same clock source.
3. a kind of method improving data collecting system dynamic range according to claim 2, it is characterised in that：Described
Carry out not equal amplitude scaling after, into ADC before be additionally provided with simulation time delay adjustment circuit.
4. a kind of method improving data collecting system dynamic range according to claim 3, it is characterised in that：When described
The additional phase-locked loop circuit PLL of Zhong Yuanwei low jitter High Precision Crystal Oscillators.
5. a kind of method improving data collecting system dynamic range according to claim 4, it is characterised in that：Through institute
After the multi-channel A/D C parallel samplings quantization stated, time delay adjustment is also carried out by digital processing mode.
6. a kind of method improving data collecting system dynamic range according to claim 5, it is characterised in that：Described
Digital processing mode is data buffer storage alignment and data interpolating, wherein data interpolating refers to by the original of data collecting system
The sample point data for the correct position that sampled data generates.
7. a kind of method improving data collecting system dynamic range according to claim 6, it is characterised in that：Described
Data dynamic restructuring algorithm preferentially selects quantization error according to minimum quantization error criterion in the case where signal is not limited
Minimum channel sampled data.
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9959856B2 (en) * | 2015-06-15 | 2018-05-01 | Cirrus Logic, Inc. | Systems and methods for reducing artifacts and improving performance of a multi-path analog-to-digital converter |
| CN106059591A (en) * | 2016-06-18 | 2016-10-26 | 海城市石油化工仪器厂 | Apparatus and method for expanding single-channel high-accuracy digital to analog converter (DAC) into multi-channel high-accuracy DAC |
| CN106571826B (en) * | 2016-11-11 | 2019-10-01 | 西安电子科技大学 | A kind of system and method improving single-chip microcontroller analog-digital converter dynamic range |
| CN108459201B (en) * | 2018-03-09 | 2021-01-19 | 中国科学院上海微系统与信息技术研究所 | Mixed sampling system and method for transient signal |
| CN109067397A (en) * | 2018-06-29 | 2018-12-21 | 电子科技大学 | One kind is based on vertical alternate broadband signal high precision collecting device |
| CN110321316B (en) * | 2019-06-19 | 2021-05-25 | 西安思丹德信息技术有限公司 | Multi-channel synchronous data acquisition self-adaptive training control device and method |
| CN111338596B (en) * | 2020-02-21 | 2023-04-11 | 北京瑞森新谱科技股份有限公司 | High dynamic range sound card analog signal data acquisition system and method |
| CN111327328B (en) * | 2020-03-04 | 2023-05-09 | 武汉中科牛津波谱技术有限公司 | Nuclear magnetic resonance data acquisition method and system based on multiple ADC |
| CN112511162B (en) * | 2020-11-11 | 2023-05-02 | 许继集团有限公司 | Analog quantity acquisition dynamic compensation method and system |
| CN112946337B (en) * | 2021-05-13 | 2021-08-03 | 深圳市鼎阳科技股份有限公司 | High-precision signal measuring method and digital oscilloscope |
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| CN101252358A (en) * | 2008-04-02 | 2008-08-27 | 中国电子科技集团公司第二十四研究所 | High speed 16 bit A/D converter modular circuit |
| CN103529409A (en) * | 2012-07-03 | 2014-01-22 | 上海联影医疗科技有限公司 | Digitalization magnetic resonance radio frequency receiving method and receiver, and imaging system |
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