CN102902570A - Embedded system register distribution method based on oscillator phase synchronization - Google Patents
Embedded system register distribution method based on oscillator phase synchronization Download PDFInfo
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- CN102902570A CN102902570A CN2012103349091A CN201210334909A CN102902570A CN 102902570 A CN102902570 A CN 102902570A CN 2012103349091 A CN2012103349091 A CN 2012103349091A CN 201210334909 A CN201210334909 A CN 201210334909A CN 102902570 A CN102902570 A CN 102902570A
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Abstract
The invention discloses an embedded system register distribution method based on oscillator phase synchronization and mainly solves the problem of relatively long distribution time of an embedded system register. The realization process comprises the following steps of: (1) drawing a mutual interference graph of intermediate variables; (2) taking a complement graph of the interference graph of the intermediate variables; (3) solving a phase value of an oscillator by utilizing nodes of the oscillator corresponding to the complement graph; (4) obtaining the phase synchronization condition of the oscillator according to the phase value of the oscillator at time t; (5) storing the corresponding nodes to a temporary register; (6) and unloading the intermediate variables in the temporary register to a system register to complete embedded system register distribution. By utilizing the embedded system register distribution method, a better embedded system register distribution result can be obtained in a short time. The embedded system register distribution method can be used for register distribution to the intermediate variables in the compilation process of an embedded system.
Description
Technical field
The invention belongs to field of computer technology, particularly compilation process is distributed the register of middle variable, can be used for embedded system.
Background technology
Along with the development of information network technique, more and more higher to the requirement of performance, real-time and reliability take computer technology as the embedded system on basis.In embedded system, compiler directly affects system performance, and register distributes the code quality important that compiler is generated.But the execution efficient of therefore distributing the technology Effective Raise programs in embedded system of angle Optimizing Compiler from register.With respect to storer, register manipulation speed is fast but limited amount needs as much as possible effective use.Therefore the register assignment problem is exactly to determine how to optimize the register that uses in the embedded system, reduces the operation to storer in the embedded system as far as possible.Specifically be exactly in the program compilation process as much as possible being kept in the register of intermediate variable that produces reduced the intermediate variable number that is forced to spill into storer, reduce and overflow cost.
Existing method for distributing register in embedded system mainly is based on the method for graph theory, converts the register assignment problem to the graph coloring model, then utilizes the algorithm that solves map colouring problem to obtain the result that register distributes.The heuritic approach OCH based on the graph coloring model early, simplicity of design, the time spent, seldom but distribution effects was poor.HYBRID EVOLUTIONARY ALGORITHMS HEA afterwards, after initialization of population, by the crossover operator CFPX that exempts to conflict the variable in each register is not conflicted, thereby then adjust the number of overflowing that intermediate variable in the individuality reduces intermediate variable by Local Search LSP, reduce the cost of overflowing of register.Although this method can access preferably register allocation result, need a large amount of time.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art, propose a kind of method for distributing register in embedded system based on oscillator phase synchronization, distribute the time to reduce register, thereby improve the execution efficient of embedded system program.
To achieve these goals, technical scheme of the present invention comprises the steps:
(1) intermediate variable in the embedded system compiling is represented with node, connect the corresponding node of intermediate variable of phase mutual interference, obtain interference figure H;
(2) keep the node among the interference figure H constant, remove the limit between connected node among the interference figure H, connect the node that does not connect among the interference figure H, obtain the complement G of interference figure H, generate the adjacency matrix A={a of complement G
Xy, x=1,2 ... N, y=1,2 ... N, wherein N is the interstitial content of complement G;
(3) with the node among the corresponding complement G of oscillator, be designated as respectively 1,2 ..., N, N oscillator initial phase of random generation in [0,2 π], produce at random N oscillator original frequency in [0.1,0.1], calculate the phase change value of oscillator according to following formula:
Wherein, i=1,2 ... N, ω
iThe natural frequency of expression oscillator i, k
1, k
2The stiffness of coupling of expression oscillator, θ
iThe phase value that represents i oscillator, θ
jRepresent j oscillator phase value, a
XyElement among the expression adjacency matrix A;
(4) according to oscillator initial phase and phase change value in the step (3), obtain constantly oscillator 1,2 of t ..., if the phase place of N is t moment i oscillator and j the cosine value cos (θ that oscillator phase is poor
j-θ
i) 0.99, then i oscillator and j oscillator phase synchronization;
(5) oscillator 1,2 ..., the corresponding node of phase locked oscillator is put into same temporary register among the N, until all nodes all are divided into L temporary register TR1
,TR
2..., TR
L, L 〉=1 and be integer;
(6) temporary register number L and embedded system register number M are compared, if temporary register number L is less than or equal to embedded system register number M, then with temporary register TR
1, TR
2..., TR
LIn node dump to embedded system register R
1, R
2..., R
LIn, this moment, embedded system register spilling variable number X was 0, overflowing cost fitness is 0; Otherwise, first with temporary register TR
1, TR
2..., TR
LBe divided into TR
1, TR
2..., TR
MAnd TR
M+1, TR
M+2..., TR
LTwo parts are then with temporary register TR
1, TR
2..., TR
MIn node dump to embedded system register R
1, R
2..., R
MIn, again with temporary register TR
M+1, TR
M+2..., TR
LIn node according to the conflict minimum principle join embedded system register R
1, R
2..., R
MIn, and use local search approach LSP to embedded system register R
1, R
2..., R
MAllocation result be optimized, obtain embedded system register R
1, R
2..., R
MNode, embedded system register spilling variable number X and embedded system register spilling cost fitness, finish the embedded system register and distribute.
The present invention has the following advantages compared with prior art:
1, because the present invention takes full advantage of graph theory knowledge, the intermediate variable interference figure of embedded system is set up complement, compare with the former figure that uses in traditional graph coloring method, the relation that the present invention is clearer and more definite between the intermediate variable;
2, because the oscillator phase synchronization method that the present invention adopts belongs to method for parallel processing, can disposable node be assigned in the register, compare HYBRID EVOLUTIONARY ALGORITHMS HEA, need through initialization, intersection, evolution node to be assigned to register, greatly reduced the time that register distributes, thereby accelerated the process of embedded system compiling, the Practical meaning has been arranged.
Description of drawings
Fig. 1 is FB(flow block) of the present invention;
Fig. 2 is the mutual interference figure of intermediate variable in the embodiment of the invention;
Fig. 3 is the complement of the mutual interference figure of intermediate variable in the embodiment of the invention;
Fig. 4 is the time dependent phase diagram of oscillator in the embodiment of the invention;
Fig. 5 is the mutual interference figure of 20 intermediate variables in the l-G simulation test of the present invention;
Fig. 6 is the mutual interference figure of 37 intermediate variables in the l-G simulation test of the present invention.
Embodiment
With reference to Fig. 1, specific implementation step of the present invention is described below:
Step 1. is drawn interference figure H
Embodiments of the invention select concrete embedded system to carry out the register distribution, and 11 intermediate variables of embedded system represent with node, are designated as 1,2 ..., 11, the corresponding node of intermediate variable of connection phase mutual interference is namely respectively with 1 and 2,1 and 4,1 and 7,1 and 9,2 and 3,2 and 6,2 and 8,3 and 5,3 and 7,3 and 10,4 and 5,4 and 6,4 and 10,5 and 8,5 and 9,6 and 11,7 and 11,8 and 11,9 and 11,10 are connected with 11, draw interference figure, as shown in Figure 2.
Keep the node among the interference figure H constant, remove the limit between connected node among the interference figure H, connect the node that does not connect among the interference figure H, obtain the complement G of interference figure H, generate the adjacency matrix A={a of complement G
Xy, x, y represents node, x=1,2 ... N, y=1,2 ... N, N are the interstitial content of complement G, if node x, y links to each other, a
Xy=1, otherwise a
Xy=0;
In the present embodiment, keep the node 1,2 of Fig. 2 ..., 11 is constant, removes the limit between the node that links to each other among Fig. 2, namely respectively with node 1 and 2,1 and 4,1 and 7,1 and 9,2 and 3,2 and 6,2 and 8,3 and 5,3 and 7,3 and 10,4 and 5,4 and 6,4 and 10,5 and 8,5 and 9,6 and 11,7 and 11,8 and 11, limit between 9 and 11,10 and 11 is removed, and the node that does not connect in the connection layout 2 is namely respectively with node 1 and 3,1 and 5,1 and 6,1 and 8,1 and 10,1 and 11,2 and 4,2 and 5,2 and 7,2 and 9,2 and 10,2 and 11,3 and 6,3 and 8,3 and 9,3 and 11,4 and 7,4 and 8,4 and 9,4 and 11,5 and 6,5 and 7,5 and 10,5 and 11,6 and 7,6 and 8,6 and 9,6 and 10,7 and 8,7 and 9,7 and 10,8 and 9,8 and 10,9 are connected with 10, obtain the complement G of Fig. 2, as shown in Figure 3, generate the adjacency matrix of Fig. 3:
Node with among the corresponding complement G of oscillator is designated as respectively 1,2 ..., N, N oscillator initial phase of random generation produces N oscillator free run frequency setting at random in [0.1,0.1] in [0,2 π], calculates the phase change value of oscillator according to following formula:
Wherein, i=1,2 ... N, ω
iThe natural frequency of expression oscillator i, k
1, k
2The stiffness of coupling of two different numerical value of expression oscillator, θ
iThe phase value that represents i oscillator, θ
iRepresent j oscillator phase value, a
XyElement among the expression adjacency matrix A;
In the present embodiment, oscillator is designated as 1,2 ..., 11, its initial phase is respectively 3.029,5.181, and 3.704,1.421,0.758,1.582,3.663,1.825,3.877,1.667,2.417 its natural frequency is respectively 0.060, and-0.022 ,-0.008,0.067,0.098 ,-0.054 ,-0.053,0.015,0.088 ,-0.017,0.065;
According to above-mentioned formula, as oscillator stiffness of coupling k
1=12, k
2, calculate the phase change value of oscillator, as shown in Figure 4 at=5 o'clock.
According to oscillator initial phase and the phase change value in the step 3, obtain constantly oscillator 1,2 of t ..., the phase value of N, in the present embodiment, oscillator 1,2 during t=10, ..., 11 phase value is respectively 5.137,6.081, and 5.840,5.860,6.073,2.890,2.897,2.914,2.905,2.951,6.101, if t moment i oscillator and j the cosine value cos (θ that oscillator phase is poor
j-θ
i) 0.99, then i oscillator and j oscillator phase synchronization; In the present embodiment, synchronous in twos between 10 by calculating as can be known oscillator 6,7,8,9, oscillator 2,5, synchronous in twos between 11, oscillator 3,4 is synchronous, oscillator 1 not with other oscillator synchronization.
In the present embodiment, deposit the corresponding node of phase locked oscillator in temporary register TR
1, TR
2, TR
3, TR
4In, i.e. TR
1={ 6,7,8,9,10}, TR
2={ 2,5,11}, TR
3={ 3,4}, TR
4={ 1}.
In the present embodiment, temporary register number L=4, embedded system register number M=3, L≤M is first with temporary register TR
1, TR
2, TR
3, TR
4Be divided into TR
1..., TR
3And TR
4Two parts are then with temporary register TR
1..., TR
3In node dump to embedded system register R
1, R
2, R
3In, again with temporary register TR
4In node according to the conflict minimum principle join embedded system register R
2In.
7a) calculate embedded system register R
1, R
2..., R
MEach node u's in the allocation result overflows factor S _ Factor (u)=S_Cost (u) * CF (u, m), u=1,2...N, 1≤m≤M, N is the node number, M is the register number, and wherein S_Cost (u) overflows cost, CF (u for node u, m) be to link to each other with node u among the interference figure H, and be stored in the register R at node u place
mIn the node number, be u with the node sequencing postscript from big to small according to the factor S _ Factor that overflows of each node
1, u
2... u
N
In the present embodiment, calculate according to above-mentioned formula, node 1 overflow factor S _ Factor (1)=3, node 4 overflow factor S _ Factor (4)=1, it is 0 that all the other nodes overflow the factor, the ordering postscript is Isosorbide-5-Nitrae, 2,3,5,6,7,8,9,10,11;
7b) according to 7a) ranking results u
1, u
2... u
N, the node u of calculation overflow factor maximum
1The register Rk at place is comprising node u
1With remove node u
1The time to overflow cost poor
1≤k≤M, wherein,
For comprising node u
1The time register R
kOverflow cost,
For removing node u
1The time register R
kOverflow cost,
In the present embodiment, calculate according to above-mentioned formula, overflow the register R at node 1 place of factor maximum
2To overflow cost poor for Δ fitness (2)=2;
7c) utilize above-mentioned formula to calculate other registers R
eComprising node u
1With remove node u
1The time overflow the poor Δ fitness of cost (e), e=1,2...M, and e ≠ k,
In the present embodiment, calculate according to above-mentioned formula, node 1 is at other registers R
1, R
3In to overflow cost poor for Δ fitness (1)=3, Δ fitness (3)=1;
7d) from 7c) other registers R of calculating
eOverflow and find out minimumly among the poor Δ fitness of cost (e), be designated as Δ fitness
Min, with Δ fitness
MinWith 7b) middle node u
1The register R at place
kThe poor Δ fitness of cost (k) that overflows compare, if Δ fitness
Min<Δ fitness (k) is with node u
1Adjust to Δ fitness
MinIn the corresponding register, otherwise, node u
1Do not adjust,
In the present embodiment, according to above-mentioned steps, with node 1 from register R
2Adjust to register R
3
7e) with reference to 7b)-7d), determine successively node u
2... u
NThe adjustment situation after, again obtain embedded system register R
1, R
2..., R
MNode,
In the present embodiment, according to above-mentioned steps, all the other nodes all do not adjust;
7f) repeating step 7a)-7e), until all overflow the non-zero node of the factor and 7d all do not occur behind certain minor sort) described in Δ fitness
MinDuring<Δ fitness (k) situation, finish embedded system register R
1, R
2..., R
MThe optimization of allocation result,
In the present embodiment, according to above-mentioned steps, all overflow the non-zero node of the factor and are the above-mentioned situation of appearance, and as a result R is optimized
1={ 6,7,8,9,10}, R
2={ 2,5,11}, R
3={ 1,3,4};
Whether the node of each register exists connection at interference figure H in step 8. determining step 7, and if there is no, then embedded system register spilling variable number X=0 overflows cost fitness=0; Overflow the little node of cost in all connected nodes otherwise overflow, add up its number, obtain embedded system register spilling variable number X, again all costs of overflowing of overflowing node are sued for peace, what obtain the embedded system register overflows cost fitness, finishes the embedded system register and distributes
In the present embodiment, register R
3In node 1 are connected with node and exist connect, because the cost 1 of overflowing of node 4 is overflowed cost 3 less than node 1, so the node of node 4 for overflowing, overflowing the node number is 1, be embedded system register spilling variable number X=1, the cost of overflowing of overflowing node 4 is 1, its embedded system register overflow cost fitness=1, the embedded system register of finishing in the present embodiment distributes.
Effect of the present invention can further specify by following experiment:
1. simulated conditions:
Be that the system of core2 2.4GHZ, internal memory 2G, WINDOWS XP uses Matlab 7.10.0 to carry out emulation at CPU.
2. emulation content:
Choose the embedded system intermediate variable of two kinds of disturbances as experimental subjects, Figure 5 shows that the interference figure of 20 intermediate variables, Figure 6 shows that the interference figure of 37 intermediate variables.Obtain respectively the register allocation result of the embedded system intermediate variable of these two kinds of disturbances with the method that proposes among existing HYBRID EVOLUTIONARY ALGORITHMS HEA and the present invention, and logging program working time, as shown in the table:
Register allocation result and the comparison of working time under two kinds of methods of table 1
As can be seen from Table 1, the method for distributing register in embedded system that the present invention is based on oscillator phase synchronization is suitable with existing HYBRID EVOLUTIONARY ALGORITHMS HEA on effect, but greatly improved the efficient that register distributes, especially when the register negligible amounts that provides, when having variable to overflow, the register allocative efficiency obviously improves, and has accelerated the compilation process of embedded system, and very high practical value is arranged.
Above-mentioned embodiment only is an example of the present invention, does not consist of any limitation of the invention, for example can also be to comprising different intermediate variable numbers with the inventive method, and the embedded system of different register numbers is carried out register and is distributed.
Claims (5)
1. the method for distributing register in embedded system based on oscillator phase synchronization comprises the steps:
(1) intermediate variable in the embedded system compiling is represented with node, connect the corresponding node of intermediate variable of phase mutual interference, obtain interference figure H;
(2) keep the node among the interference figure H constant, remove the limit between connected node among the interference figure H, connect the node that does not connect among the interference figure H, obtain the complement G of interference figure H, generate the adjacency matrix A={a of complement G
Xy, x=1,2 ... N, y=1,2 ... N, wherein N is the interstitial content of complement G;
(3) with the node among the corresponding complement G of oscillator, be designated as respectively 1,2 ..., N, N oscillator initial phase of random generation in [0,2 π], produce at random N oscillator free run frequency setting in [0.1,0.1], calculate the phase change value of oscillator according to following formula:
Wherein, i=1,2 ... N, ω
iThe natural frequency of expression oscillator i, k
1, k
2The stiffness of coupling of expression oscillator, θ
iThe phase value that represents i oscillator, θ
jRepresent j oscillator phase value, a
XyElement among the expression adjacency matrix A;
(4) according to oscillator initial phase and phase change value in the step (3), obtain constantly oscillator 1,2 of t ..., if the phase place of N is t moment i oscillator and j the cosine value cos (θ that oscillator phase is poor
j-θ
i) 0.99, then i oscillator and j oscillator phase synchronization;
(5) oscillator 1,2 ..., the corresponding node of phase locked oscillator is put into same temporary register among the N, until all nodes all are divided into L temporary register TR
1, TR
2..., TR
L, L 〉=1 and be integer;
(6) temporary register number L and embedded system register number M are compared, if temporary register number L is less than or equal to embedded system register number M, then with temporary register TR1
,TR
2..., TR
LIn node dump to embedded system register R
1, R
2..., R
LIn, this moment, embedded system register spilling variable number X was 0, overflowing cost fitness is 0; Otherwise, first with temporary register TR
1, TR
2..., TR
LBe divided into TR
1, TR
2..., TR
MAnd TR
M+1, TR
M+2..., TR
LTwo parts are then with temporary register TR
1, TR
2..., TR
MIn node dump to embedded system register R
1, R
2..., R
MIn, again with temporary register TR
M+1, TR
M+2..., TR
LIn node according to the conflict minimum principle join embedded system register R
1, R
2..., R
MIn, and use local search approach LSP to embedded system register R
1, R
2..., R
MAllocation result be optimized, obtain embedded system register R
1, R
2..., R
MNode, embedded system register spilling variable number X and embedded system register spilling cost fitness, finish the embedded system register and distribute.
2. method according to claim 1 is overflowed variable number in the wherein said step (6), is the intermediate variable number of the storer of the register spilling from embedded system in the embedded system.
3. method according to claim 1, wherein said step (6) overflow cost, overflow the time of intermediate variable cost for the memory access from embedded system.
4. method according to claim 1, the conflict minimum principle of wherein said step (6) refers in the embedded system register the mutual value minimum of conflicting between the existing intermediate variable in the new intermediate variable that adds and embedded system register.
5. method according to claim 1, wherein the described use local search approach of step (6) LSP is to embedded system register R
1, R
2..., R
MAllocation result be optimized, carry out as follows:
6a) calculate embedded system register R
1, R
2..., R
MEach node u's in the allocation result overflows factor S _ Factor (u)=S_Cost (u) * CF (u, m), u=1,2...N, 1≤m≤M, N is the node number, M is the register number, and wherein S_Cost (u) overflows cost, CF (u for node u, m) be to link to each other with node u among the interference figure H, and be stored in the register R at node u place
mIn the node number, be u with the node sequencing postscript from big to small according to the factor S _ Factor that overflows of each node
1, u
2... u
N
6b) according to 6a) ranking results u
1, u
2... u
N, the node u of calculation overflow factor maximum
1The register Rk at place is comprising node u
1With remove node u
1The time to overflow cost poor
1≤k≤M, wherein,
For comprising node u
1The time register R
kOverflow cost,
For removing node u
1The time register R
kOverflow cost;
6c) utilize above-mentioned formula to calculate other registers R
eComprising node u
1With remove node u
1The time overflow the poor Δ fitness of cost (e), e=1,2...M and e ≠ k;
6d) from 6c) other registers R of calculating
eOverflow and find out minimumly among the poor Δ fitness of cost (e), be designated as Δ fitness
Min, with Δ fitness
MinWith 6b) middle node u
1The register R at place
kThe poor Δ fitness of cost (k) that overflows compare, if Δ fitness
Min<Δ fitness (k) is with node u
1Adjust to Δ fitness
MinIn the corresponding register, otherwise, node u
1Do not adjust;
6e) with reference to 6b)-6d), determine successively node u
2... u
NThe adjustment situation after, again obtain embedded system register R
1, R
2..., R
MNode;
6f) repeat 6a)-6e), until all overflow the non-zero node of the factor and 6d all do not occur behind certain minor sort) described in Δ fitness
MinDuring<Δ fitness (k) situation, finish embedded system register R
1, R
2..., R
MThe optimization of allocation result.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106663019A (en) * | 2014-05-13 | 2017-05-10 | 甲骨文国际公司 | Handling value types |
CN107277820A (en) * | 2017-06-28 | 2017-10-20 | 陕西派瑞智能科技有限公司 | OFDMA network dynamic frequency spectrum distributing methods based on the positive and negative coupling of oscillator phase |
CN113535375A (en) * | 2020-04-16 | 2021-10-22 | 中标软件有限公司 | Optimized allocation method of registers |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102033773A (en) * | 2010-11-12 | 2011-04-27 | 西安电子科技大学 | Method for distributing register in embedded system based on inverse image description |
CN102186175A (en) * | 2011-05-04 | 2011-09-14 | 西安电子科技大学 | Cognitive network dynamic spectrum distribution method based on oscillator phase synchronization |
CN102331919A (en) * | 2011-09-09 | 2012-01-25 | 西安电子科技大学 | Maximum complete subgraph-based embedded system register allocation method |
CN102355393A (en) * | 2011-09-27 | 2012-02-15 | 西安电子科技大学 | Oscillator phase synchronization-based network community structure partitioning method |
-
2012
- 2012-09-11 CN CN2012103349091A patent/CN102902570A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102033773A (en) * | 2010-11-12 | 2011-04-27 | 西安电子科技大学 | Method for distributing register in embedded system based on inverse image description |
CN102186175A (en) * | 2011-05-04 | 2011-09-14 | 西安电子科技大学 | Cognitive network dynamic spectrum distribution method based on oscillator phase synchronization |
CN102331919A (en) * | 2011-09-09 | 2012-01-25 | 西安电子科技大学 | Maximum complete subgraph-based embedded system register allocation method |
CN102355393A (en) * | 2011-09-27 | 2012-02-15 | 西安电子科技大学 | Oscillator phase synchronization-based network community structure partitioning method |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106663019A (en) * | 2014-05-13 | 2017-05-10 | 甲骨文国际公司 | Handling value types |
CN106663019B (en) * | 2014-05-13 | 2020-02-07 | 甲骨文国际公司 | Processing value types |
CN107277820A (en) * | 2017-06-28 | 2017-10-20 | 陕西派瑞智能科技有限公司 | OFDMA network dynamic frequency spectrum distributing methods based on the positive and negative coupling of oscillator phase |
CN113535375A (en) * | 2020-04-16 | 2021-10-22 | 中标软件有限公司 | Optimized allocation method of registers |
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