CN102331919B - Maximum complete subgraph-based embedded system register allocation method - Google Patents

Maximum complete subgraph-based embedded system register allocation method Download PDF

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CN102331919B
CN102331919B CN2011102680612A CN201110268061A CN102331919B CN 102331919 B CN102331919 B CN 102331919B CN 2011102680612 A CN2011102680612 A CN 2011102680612A CN 201110268061 A CN201110268061 A CN 201110268061A CN 102331919 B CN102331919 B CN 102331919B
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register
node
individual
offspring
ind
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CN102331919A (en
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吴建设
焦李成
畅志艳
陈为胜
钟桦
王爽
侯彪
吴家骥
公茂果
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Xidian University
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Abstract

The invention provides a maximum complete subgraph-based embedded system register allocation method, which mainly solves the problems that a heuristic algorithm has poor allocation effect and overflow cost is too high due to no consideration of the overflow cost in a crossover operator part in an evolutionary algorithm. The method is implemented by the following steps of: (1) taking a complement from an intermediate variable mutual interference graph to obtain the complement G; (2) randomly dividing all nodes into two classes, respectively putting the nodes into a set A or a set B, and completing initialization of population; (3) crossing an individual in the population by using an overflow cost-based maximum complete subgraph crossover operator SC-MCX to generate a subgeneration individual; and (4) optimizing the subgeneration individual by using a local search operator LSP, replacing an individual having the maximum fitness function value in parent individuals by using the optimized subgeneration individual, and continuously participating in population evolution. By the method, the population evolution speed is improved, the overflow cost and the overflow variable number of the individual are reduced, and the method can be used for embedded system register allocation.

Description

Method for distributing register in embedded system based on maximum complete subgraph
Technical field
The invention belongs to field of computer technology, relate to embedded system, a kind of method for distributing register in embedded system based on maximum complete subgraph particularly, the method is distributed for the embedded system register, can be efficiently by the intermediate variable that produces in the program compilation process, as much as possible depositing in register, overflow cost and overflow the variable number thereby reduce, improve the utilization factor of register, and then improve the compile efficiency of programs in embedded system.
Background technology
In embedded system, program normally, for realizing what certain fixing function was write, so the program that requires to write can produce high-quality code after compiling, has higher execution efficiency.Storer and register all are used to the intermediate variable that produces in the stored routine compilation process.With respect to storer, what the access speed of register will be fast is many, but quantity seldom.In the program compilation process, if register can not be stored all intermediate variables, will be saved in storer by some intermediate variable so, this situation is called overflows.Embedded system is referred to as the cost of overflowing of this intermediate variable from the time that access intermediate variable storer spends.Therefore, can program obtain high-quality code and depend on to a great extent and more intermediate variable is saved in register after compiling, with minimizing, overflow the number of intermediate variable, the assignment problem of Here it is embedded system register.
Up to the present, most of register assignment problems are all that modeling becomes the graph coloring model and describes, the register allocation algorithm of the embedded system based on the graph coloring model early is the optimization graph coloring heuritic approach OCH that is proposed by people such as Briggs, design relatively simple, that distribution effects is poor to a kind of improvement of the graph coloring heuritic approach of chaitin proposition.A lot of scholars were devoted to solve embedded system register assignment problem with HYBRID EVOLUTIONARY ALGORITHMS HEA afterwards, take full advantage of the thought of genetic algorithm, at first population is carried out to initialization, then utilize crossover operator from two parents, producing a new register allocative decision, it is genetic to filial generation, crossover operator commonly used has greediness to cut apart crossover operator GPX and the crossover operator CFPX that exempts to conflict, thus finally by Local Search LSP allow between the register of variable in single individuality adjust reduce this individuality total overflow cost Spill Cost.Record the optimum individual that produces in iterative process each time, and then obtain final optimum individual, also just obtained register and distributed way.In two crossover operators mentioning in the above, GPX just simply is genetic in filial generation from parent, selecting to comprise the register that intermediate variable is maximum, do not consider the conflict relationship between the intermediate variable of this registers storage, do not make corresponding adjustment yet.Although be better than GPX in the CFPX design, taken into full account the conflict relationship between the intermediate variable of heritable registers storage, but it has only considered the number of intermediate variable, do not consider the cost of overflowing of each variable, so can not be called a perfect crossover operator, the register allocative decision that obtains still has more intermediate variable overflowed in storer, has reduced the efficiency that register distributes.
Summary of the invention
The object of the invention is to overcome the deficiency of above-mentioned prior art, a kind of method for distributing register in embedded system based on maximum complete subgraph has been proposed, with the intermediate variable by producing in the program compilation process, as much as possible depositing in register, reduce and overflow cost and overflow the variable number, improve the register allocative efficiency.
For achieving the above object, technical scheme of the present invention comprises the steps:
(1) initialization population step
The mutual interference figure H of the intermediate variable that 1a) produces in the drawing program compilation process, in interference figure H, each node represents an intermediate variable, two node phases mutual interference that each limit connects, and provide the cost of overflowing of each intermediate variable, overflow cost and be embedded system from time that access intermediate variable storer spends;
1b) take out the complement G={N of mutual interference figure H, S, V, E}, wherein, N represents the intermediate variable sum, S represents register quantity, each register R iI=1 ... S represents, V represents the nodal set of all intermediate variables, and node is labeled as respectively 0,1,2 ..., N-1, E represents the set of all nonoriented edges, in complement G, two nodes that each limit connects are placed in same register, make overflow cost and overflow the variable number as much as possible little;
1c) by N node in the nodal set V of intermediate variable random be divided into two classes, with A and B, represent respectively;
1d) according to complement G, draw the syntople G between all nodes in set A A=(V A, E A) V wherein A=A,
Figure BDA0000090474400000021
For V AIn two node v arbitrarily i, v j, work as v iAnd v jIn the time of being placed in same register, by v iWith v jBe connected;
1e) find adjacent map G AA maximum complete subgraph, by the node v that comprises in this maximum complete subgraph kPut into the dummy register of subscript minimum;
1f) from G AMiddle delete step 1e) put into the node v of register k, obtain G ASubgraph G after renewal A';
1g) to subgraph G A' repeating step 1e)-1f) until S register all be used, then by subgraph G ANode in ' middle residue node and set B is put in register according to the conflict minimum principle;
1h) given population scale is M, and M is set as any even number, by step 1c)-1g) repeat M time to produce M individuality, use respectively Ind i, i=1...M represents each individuality, completes the initialization of population;
(2) use crossover operator to produce a new offspring individual step
2a) use based on the maximum complete subgraph crossover operator SC-MCX that overflows cost the individual Ind in population pAnd Ind P+1Intersect and produce a new offspring individual, use offspring pExpression, p=1 wherein, 3,5 ... and p<M;
2b) according to complement G, draw two parent individualities Ind p = { R 1 p , . . . , R S p } With Ind p + 1 = { R 1 p + 1 , . . . , R S p + 1 } In the syntople figure that forms of the node that comprises of each register, use respectively
Figure BDA0000090474400000033
With
Figure BDA0000090474400000034
Expression;
2c) find out the maximum complete subgraph of each syntople figure, use respectively With Expression, therefrom select the maximum complete subgraph that overflows the cost maximum
Figure BDA0000090474400000037
Wherein t ∈ p, p+1}, l ∈ 1 ..., S}, will
Figure BDA0000090474400000038
The node that comprises takes the lead in putting into offspring individual offspring p = { R 1 os , . . . R S os } First register
Figure BDA00000904744000000310
In;
2d) from all nodes, choose with
Figure BDA00000904744000000311
The not afoul node of middle node is put into register
Figure BDA00000904744000000312
In, complete the individual offspring of filial generation pFirst register Structure, and will put into register
Figure BDA00000904744000000314
In node from all registers that two parents comprise, deleting;
2e) repeating step 2b)-2c) successively constructor for offspring pIn remaining register;
2f) by remaining node in the parent individuality, according to the conflict minimum principle, put into successively the corresponding register of filial generation, complete the individual Ind of parent pAnd Ind P+1Intersection, produce offspring individual offspring p.
(3) with Local Search operator LSP, optimize the offspring individual step
3a) to step 2f) middle each offspring individual offspring that produces p, adopt Local Search operator LSP to be optimized, with the individuality after optimizing, replace individual Ind in population pAnd Ind P+1One of fitness function value maximum, the sustainable participation Evolution of Population;
3b) setting iterations is K, to step 2a)-3a) repeat K time, just all nodes can be assigned in register efficiently, reach and overflow cost and overflow variable number minimum.
The present invention has the following advantages:
1) the present invention is due in the initialization of population process, introduced the thought of complement and maximum complete subgraph, each individuality that makes generation is preliminary has obtained a reasonable register allocative decision, has accelerated Evolution of Population speed, has improved the register allocative efficiency.
2) crossover operator of the present invention, owing to having adopted based on the maximum complete subgraph crossover operator that overflows cost, has been considered to overflow the cost factor fully in two parent intersection processes, has reduced total the overflowing cost and overflow the variable number of offspring individual.
The accompanying drawing explanation
Fig. 1 is process flow diagram of the present invention;
Fig. 2 is the mutual interference figure of instantiation intermediate variable of the present invention;
Fig. 3 is the complement G of the mutual interference figure of instantiation intermediate variable of the present invention;
Fig. 4 obtains the syntople figure G between all nodes in set A according to complement G A
Fig. 5 is syntople figure G ARenewal figure G A';
Fig. 6 draws the individual Ind of two parents according to complement G pAnd Ind P+1In the syntople figure that forms of the node that comprises of each register;
Fig. 7 is the individual Ind of two parents pAnd Ind P+1Intersect and produce filial generation offspring pThe operation chart of first register node.
Embodiment
With reference to accompanying drawing 1, specific implementation step of the present invention is described below:
Step 1. pair Advanced group species carries out initialization.
As shown in Figure 2, in figure, node 0-9 represents ten intermediate variables to the mutual interference figure of this example intermediate variable, and the intermediate variable of two node representatives of each limit connection can not be placed in same register.It is overflowed during to storer that table 1 has provided the intermediate variable of each node representative, and what consume overflows cost.The mutual interference figure of intermediate variable shown in Figure 2 is got to complement, obtain complement G, as shown in Figure 3.In Fig. 3, any two of G have the intermediate variable of the connected node representative in limit can be placed in same register.Set-up register quantity S is 4, and initialization produces a population at individual Ind i = { R 1 i , . . . , R 4 i } .
Each node of table 1 consumes while spilling into storer overflows the cost table
Node 0 1 2 3 4 5 6 7 8 9
Overflow cost 2 2 1 3 1 3 1 4 3 4
1.1) by ten nodes random be divided into two classes, be mapped to respectively in set A or set B, any one node is placed into set A or the probability of set B equates, suppose A={0,5,6,8,9}, B={1,2,3,4,7}, obtain the syntople figure G between all nodes in set A according to complement G A, as shown in Figure 4;
1.2) find G AA maximum complete subgraph { 5,8} puts it in the dummy register of subscript minimum, namely R 1 i = { 5,8 } ;
1.3) from G ARegister has been put in middle deletion
Figure BDA0000090474400000053
In node 5 and 8, obtain G ARenewal figure G A', as shown in Figure 5;
1.4) repeated execution of steps 1.2) and 1.3) until G AIn till all nodes all put into register or all registers and all are used, last, obtain R 1 i = { 5,8 } , R 2 i = { 0,6 } , R 3 i = { 9 } ;
1.5) by the node in set B according to the conflict minimum principle put into successively register, for example node 1 respectively with register
Figure BDA0000090474400000057
With
Figure BDA0000090474400000058
In node 8 and node 0 conflict, but with
Figure BDA0000090474400000059
In node 9 do not conflict, therefore node 1 is put into to register
Figure BDA00000904744000000510
In, obtain
Figure BDA00000904744000000511
In this way successively by node 2,3,4,7 obtain after putting into register: R 1 i = { 5,8,4 } , R 2 i = { 0,6,2 } , R 3 i = { 9,1,3 } , R 4 i = { 7 } ;
1.6) set population scale M=2, repeat step 1.1 twice)-1.5) produce two individualities, complete the initialization of population.
Step 2. intersection produces a new offspring individual.
Employing based on the maximum complete subgraph crossover operator SC-MCX that overflows cost to individuality Ind p = { R 1 p , . . . , R 4 p } With Ind p + 1 = { R 1 p + 1 , . . . , R 4 p + 1 } Intersect and produce a new offspring individual, use offspring p = { R 1 os , . . . R 4 os } Expression, p=1 wherein, 3,5 ... and p<M.
2.1) individual Ind pAnd Ind P+1By population, be initialized as respectively:
Ind p={{6},{9,5,3,},{7,2,1,},{0,8,4}}
Ind p+1={{6,3},{9,8},{7,2,1,4},{0,5}};
2.2) according to complement G, draw the individual Ind of two parents pAnd Ind P+1In the syntople figure that forms of the node that comprised by each register, use respectively
Figure BDA0000090474400000061
With
Figure BDA0000090474400000062
Expression, as shown in Figure 6;
2.3) find out the maximum complete subgraph of each syntople figure, obtain MC 1 p = { 6 } , MC 2 p = { 9,5 } , MC 3 p = { 2,1 } , MC 4 p = { 0,8,4 } With MC 1 p + 1 = { 3 } , MC 2 p + 1 = { 9 } , MC 3 p + 1 = { 2,1,4 } , MC 4 p + 1 = { 5 } , Therefrom select the maximum complete subgraph that overflows the cost maximum MC 2 p = { 9,5 } , And will
Figure BDA00000904744000000612
The node that comprises takes the lead in putting into offspring individual offspring pIn first register
Figure BDA00000904744000000613
In, at this moment namely R 1 os = { 9,5 } ;
2.4) from all the other all nodes, choosing the node that does not all conflict with node 9 and 5, put into
Figure BDA00000904744000000615
In, obtain
Figure BDA00000904744000000616
To this, completed individual first register of filial generation Structure, shown in Figure 7;
2.5) at the individual Ind of parent pAnd Ind P+1Offspring individual offspring has been put in middle deletion pFirst register
Figure BDA00000904744000000618
In node 9,5 and 7;
2.6) repeated execution of steps 2.2)-2.5), construct successively offspring individual offspring pIn remaining register;
2.7) will in the parent individuality, could not be assigned to the node in the filial generation register, according to the conflict minimum principle, put into successively offspring individual offspring pRegister in, obtain offspring individual offspring pFor:
offspring p={{9,5,7},{0,8,4,2},{3,1},{6}}。
Step 3 is optimized offspring individual with Local Search operator LSP.
Offspring individual offspring to step 2 generation pUse Local Search operator LSP to be optimized, with the offspring individual after optimizing, replace the individuality of fitness function value maximum in the parent individuality, the sustainable participation Evolution of Population, be shown in the detailed process that local optimum operator LSP is optimized Topcuoglu " Solving the register allocator with evolutionary algorithm from embedded system ".
Effect of the present invention can further illustrate by following experiment:
1. simulated conditions:
At CPU, be with the C++ program, to carry out emulation on AMD Athlon (tm) II * 2245, dominant frequency 2.91GHZ, internal memory 2G, WINDOWS XP system.
2. emulation content:
At experimental section, in order better to embody advantage of the present invention, the present invention is contrasted with the HYBRID EVOLUTIONARY ALGORITHMS based on the crossover operator CFPX that exempts to conflict.With the mutual interference figure of the intermediate variable of random generation, test, establishing nodal point number is n, introduces limit density α, register density β and overflow tri-concepts of cost density γ.The quantity that the limit density meter is shown in limit in the mutual interference figure of intermediate variable of random generation is α * (n * (n-1))/2, register density represents that register quantity is β * n, overflows cost density and represents that the cost of overflowing of any one intermediate variable gets the arbitrary integer between [1...2 γ].In experiment, regulation n equals respectively 100,300, and α is value 0.10,0.25,0.45,0.60,0.75,0.90 respectively, and β is value 0.04,0.08,0.10,0.15,0.20 respectively, and γ equals 5.Value to these four parameters is carried out combination in any, each situation produces 30 width Random Graph and tests, corresponding five the register density of each limit density, to carry out quantity statistics as shown in table 2 to the cost of overflowing of 150 simulation results of 30 width interference figures for experimental result like this, and experiment is as shown in table 3 to overflowing cost and overflowing the mean value statistics of variable number:
The fine or not distribution table of 150 groups of data from overflow costs of table 2
Figure BDA0000090474400000071
No matter from the data of table 2, can find out, be 100 or 300 figure for nodal point number, and the present invention is all good than the result that the evolution algorithm based on the CFPX crossover operator obtains.Work as n=100, α=0.90 o'clock, the present invention has 49 width to be better than CFPX.Work as n=300, α=0.90 o'clock, the present invention has 102 width to be better than CFPX, and other situations are also similar.Explanation is along with the advantage of this invention of increase of nodal point number can be more and more obvious.
150 groups of data from overflow costs of table 3 and overflow the mean value of variable number
Figure BDA0000090474400000081
Table 3 has contrasted two kinds of algorithms from measuring, and works as n=100, α=0.90 o'clock, and the present invention has only reduced by 0.742 than the evolution algorithm based on the crossover operator CFPX that exempts to conflict overflowing on cost.And work as n=300, and α=0.90 o'clock, the present invention has reduced by 6.12 than CFPX overflowing on cost.More confirmed the conclusion that table 2 draws: along with the increase of nodal point number, advantage of the present invention is more and more obvious.Other situations are similar, above analysis absolutely proves that the present invention is better than the evolution algorithm based on CFPX, can more efficiently the intermediate variable that produces in the program compilation process be kept in register, and minimizing is overflowed, the compile efficiency of raising program, obtain the code of better quality.
Above-mentioned embodiment is only an example of the present invention, does not form any limitation of the invention, can also be for different nodes as us, and different limit density and register density use the present invention to carry out the register distribution.

Claims (3)

1. method for distributing register in embedded system based on the operation of maximum complete subgraph comprises:
(1) initialization population step:
The mutual interference figure H of the intermediate variable that 1a) produces in the drawing program compilation process, in interference figure H, each node represents an intermediate variable, two node phases mutual interference that each limit connects, and provide the cost of overflowing of each intermediate variable, overflow cost and be embedded system from time that access intermediate variable storer spends;
1b) take out the complement G={N of mutual interference figure H, S, V, E}, wherein, N represents the intermediate variable sum, S represents register quantity, each register R iI=1 ... S represents, V represents the nodal set of all intermediate variables, node is labeled as respectively 0,1,2 ..., N-1, E represents the set of all nonoriented edges, in complement G, two nodes that each limit connects are placed in same register, make overflow cost and overflow the variable number as much as possible little;
1c) by N node in the nodal set V of intermediate variable random be divided into two classes, with A and B, represent respectively;
1d) according to complement G, draw the syntople figure G between all nodes in set A A=(V A, E A), V wherein A=A,
Figure FDA0000375231550000011
For V AIn two node v arbitrarily i, v j, work as v iAnd v jIn the time of being placed in same register, by v iWith v jBe connected;
1e) find adjacent map G AA maximum complete subgraph, by the node v that comprises in this maximum complete subgraph kPut into the dummy register of subscript minimum;
1f) from G AMiddle delete step 1e) put into the node v of register k, obtain G ASubgraph G after renewal A';
1g) to subgraph G A' repeating step 1e)-1f) until S register all be used, then by subgraph G ANode in ' middle residue node and set B is put in register according to the conflict minimum principle;
1h) given population scale is M, and M is set as any even number, by step 1c)-1g) repeat M time to produce M individuality, use respectively Ind i, i=1...M represents each individuality, completes the initialization of population;
(2) use crossover operator to produce a new offspring individual step:
2a) use based on the maximum complete subgraph crossover operator SC-MCX that overflows cost the individual Ind in population pAnd Ind P+1Intersect and produce a new offspring individual, use offspring pExpression, p=1 wherein, 3,5 ... and p<M;
2b) according to complement G, draw two parent individualities Ind p = { R 1 p , . . . , R S p } With Ind p + 1 = { R 1 p + 1 , . . . , R S p + 1 } In the syntople figure that forms of the node that comprises of each register, use respectively
Figure FDA0000375231550000023
With
Figure FDA0000375231550000024
Expression;
2c) find out the maximum complete subgraph of each syntople figure, use respectively
Figure FDA0000375231550000025
With
Figure FDA0000375231550000026
Expression, therefrom select the maximum complete subgraph that overflows the cost maximum
Figure FDA0000375231550000027
Wherein t ∈ p, p+1}, l ∈ 1 ..., S}, will
Figure FDA0000375231550000028
The node that comprises takes the lead in putting into offspring individual offspring p = { R 1 os , . . . R S os } First register
Figure FDA00003752315500000210
In;
2d) from all nodes, choose with
Figure FDA00003752315500000211
The not afoul node of middle node is put into register
Figure FDA00003752315500000212
In, complete the individual offspring of filial generation pFirst register
Figure FDA00003752315500000213
Structure, and will put into register
Figure FDA00003752315500000214
In node from all registers that two parents comprise, deleting;
2e) repeating step 2b)-2c) successively constructor for offspring pIn remaining register;
2f) by remaining node in the parent individuality, according to the conflict minimum principle, put into successively the corresponding register of filial generation, complete the individual Ind of parent pAnd Ind P+1Intersection, produce offspring individual offspring p
(3) with Local Search operator LSP, optimize the offspring individual step:
3a) to step 2f) middle each offspring individual offspring that produces p, adopt Local Search operator LSP to be optimized, with the individuality after optimizing, replace individual Ind in population pAnd Ind P+1One of fitness function value maximum, the sustainable participation Evolution of Population;
3b) setting iterations is K, to step 2a)-3a) repeat K time, just all nodes can be assigned in register efficiently, reach and overflow cost and overflow variable number minimum.
2. the register allocation method described according to claim 1, step 1b wherein) complement of the mutual interference figure H of described taking-up, the network topology structure that refers to node in the mutual interference figure H of maintenance is constant, by original fillet deletion between the every pair of node in interference figure H, add non-existent fillet in interference figure H, just obtain the complement of interference figure H.
3. the register allocation method described according to claim 1, wherein step 1g) described in by subgraph G ANode in ' middle residue node and set B is put in register according to the conflict minimum principle, refers to for node w ∈ B arbitrarily, finds a register R j, wherein j ∈ { 1 ... S}, make register R jIn with node w, in interference figure H, have the number of the node that limit is connected minimum.
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CN102033773A (en) * 2010-11-12 2011-04-27 西安电子科技大学 Method for distributing register in embedded system based on inverse image description

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CN101330417A (en) * 2008-07-24 2008-12-24 安徽大学 Quotient space overlay model for calculating network shortest path and building method thereof
CN101799839A (en) * 2010-01-19 2010-08-11 浙江工业大学 Method for establishing public traffic network model with controllable network diameter based on random overlapping faction and public traffic network model
CN102033773A (en) * 2010-11-12 2011-04-27 西安电子科技大学 Method for distributing register in embedded system based on inverse image description

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