CN104360906B - A kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould - Google Patents
A kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould Download PDFInfo
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Abstract
The invention discloses a kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould, it is characterised in that including：Corresponding control data flow graph is built after the circuit description for obtaining input；Control data flow graph is divided into cyclic part and acyclic part；It is scheduled using iteration modulo scheduling algorithm paired domination number according to the cyclic part of flow graph；It is scheduled using difference constrained system dispatching algorithm paired domination number according to the acyclic part of flow graph；Obtained scheduling result is carried out after mathematics integration, integrated dispatch result is obtained.The scheduling flow of High Level Synthesis is optimized the present invention, improves scheduling performance, and scheduling implementation process is easily and fast, and scheduling can be realized comprehensively, in time, and dispatching efficiency is high, can be widely applied in High Level Synthesis scheduling field.
Description
Technical field
It is particularly a kind of based on difference constrained system and iteration mould the present invention relates to a kind of High Level Synthesis dispatching method
High Level Synthesis dispatching method.
Background technology
The target of High Level Synthesis is that an algorithm level behavior for meeting set digital display circuit is obtained in goal set
Structure results on the basis of the conditions such as description, constraints.High Level Synthesis flow includes：Compiling with conversion, Operator Scheduling,
Resource allocation, register distribution, wire net generation and optimization.Wherein, Operator Scheduling is that dispatching algorithm is for compiling conversion life
Into control data flow graph in each operation and computing be assigned to each control step, met so as to realize under constraints
Optimal or more excellent Operator Scheduling scheme, is a mostly important step in High Level Synthesis flow.In high-level dispatching method
Substantially it is divided into two classes, a class is round-robin scheduling, and a class is non-round-robin scheduling, it is not bright in current high-level dispatching method
Really both of these case is made a distinction, is all using structured approach of the prior art, converter technique or integral linear programming method etc.
Method is scheduled, and scheduling process is complex, and can not in time, be comprehensively scheduled, and dispatching efficiency is low, gradually can not
Meet the growth requirement of IC design.
The content of the invention
In order to solve above-mentioned technical problem, it is an object of the invention to provide one kind based on difference constrained system and iteration mould
High Level Synthesis dispatching method.
The technical solution adopted for the present invention to solve the technical problems is：
A kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould, including：
Corresponding control data flow graph is built after S1, the circuit description of acquisition input；
S2, control data flow graph is divided into cyclic part and acyclic part；
S3, it is scheduled according to the cyclic part of flow graph using iteration modulo scheduling algorithm paired domination number；
S4, it is scheduled according to the acyclic part of flow graph using difference constrained system dispatching algorithm paired domination number；
S5, the scheduling result that is obtained in step S3 and S4 is carried out after mathematics integration, obtain integrated dispatch result.
Further, the step S2, including：
S21, it is ranked up according to all running nodes in flow graph using depth-priority-searching method paired domination number；
S22, the node of the control data flow graph after sequence is built into by corresponding Dominator Tree using dominating figure iterative algorithm；
After all back edges in S23, Detection and Extraction Dominator Tree, all loops being made up of back edge are obtained as control data
The cyclic part of flow graph, and then obtain the acyclic part of control data flow graph.
Further, the step S3, including：
S31, paired domination number carry out minimum iteration according to the cyclic part of flow graph and start interval time calculating；
S32, the minimum iteration for obtaining calculating start interval time as initial iteration and start interval time, use row
List scheduling algorithm paired domination number is scheduled according to the cyclic part of flow graph；
S33, iteration are scheduled trial when meeting following condition, continue executing with step S34：Dispatch successfully or adjust
The iteration number of attempt of degree is more than predetermined upper threshold value；
S34, judge whether that scheduling is finished, if so, then terminate, otherwise increase iteration started after interval time, was continuing with
List scheduling algorithm carries out next round scheduling, and returns to execution step S33.
Further, the step S4, including：
S41, paired domination number build corresponding scheduling variable according to the node of the acyclic part of flow graph；
S42, according to scheduling variable, all schedule constraints are converted to after corresponding difference constraint formulations, by acquisition
All difference constraint formulations change into shaping planning matrix；
S43, the demand result according to High Level Synthesis, build corresponding object function；
S44, using shaping planning matrix as bound for objective function, carry out linear programming for solution, judge whether energy
The optimal value for obtaining object function is solved, step S43 is performed if it is not, then returning, otherwise obtains the optimal value of the object function, together
When obtain the value of corresponding shaping planning matrix, and then obtain the dispatch value of each node.
Further, schedule constraints described in the step S42 include relying on constraint, temporal constraint and resource constraint.
Further, it is described rely on constraint include described as circuit in data dependency caused by data dependence constraint and
Control relies on constraint caused by control dependence in being described as circuit；
When the schedule constraints are that data dependence is constrained, corresponding difference is translated into using below equation and constrains public
Formula：
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svend(vi) represent node ViScheduling variable
End value, node ViWith node VjIt is two running nodes and node V constrained with data dependenceiMust be in node VjScheduling
It is preceding that scheduling is finished, e (vi,vj) represent node ViWith node VjData dependence binding side, EdRepresent in control data flow graph
The set of all data dependence binding sides；
When the schedule constraints rely on constraint for control, corresponding difference is translated into using below equation and constrains public
Formula：
In above formula, svbeg(ssrc(bbj)) represent basic blocks bbjScheduling variable initial value, svend(ssnk(bbi)) table
Show basic blocks bbiScheduling variable end value, basic blocks bbiWith basic blocks bbjIt is two basic blocks that constraint is relied on control
And basic blocks bbjRunning node must be in basic blocks bbiAll running nodes dispatch finish after just schedulable, ec
(bbi,bbj) represent basic blocks bbiWith basic blocks bbjControl rely on binding side, EcRepresent all controls in control data flow graph
System relies on the set of binding side.
Further, the temporal constraint includes relative timing constraint and delay constraints, and relative timing constraint includes minimum phase
To temporal constraint and maximum relative timing constraint；
When the schedule constraints are minimum relative timing constraint, using being converted into corresponding difference in below equation about
Beam formula：
svbeg(vi)-svbeg(vj)≤-lij
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svbeg(vi) represent node ViScheduling variable
Initial value, lijFor natural number, node ViWith node VjIt is two running nodes and node V with minimum relative timing constraintj's
Scheduling must be than node ViScheduling at least evening lijThe individual clock cycle；
When the schedule constraints are maximum relative timing constraint, using being converted into corresponding difference in below equation about
Beam formula：
svbeg(vj)-svbeg(vi)≤uij
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svend(vi) represent node ViScheduling variable
Initial value, uijFor natural number, node ViWith node VjIt is two running nodes and node V with maximum relative timing constraintjWith
Node ViBetween maximum delay path be uijThe individual clock cycle；
When the schedule constraints are delay constraints, using being converted into corresponding difference constraint formulations in below equation：
svend(ssnk(bbj))-svbeg(ssrc(bbi))≤Tlat
Wherein, svend(ssnk(bbj)) represent basic blocks bbjScheduling variable end value, svbeg(ssrc(bbi)) represent
Basic blocks bbiScheduling variable initial value, basic blocks bbiWith basic blocks bbjIt is two basic blocks and basis with delay constraints
Block bbiWith basic blocks bbjBetween maximum delay path be TlatThe individual clock cycle.
Further, when the schedule constraints are resource constraint, using being converted into corresponding difference in below equation about
Beam formula：
svbeg(vπ i)-svbeg(vπ j)≤-Latency(vπ i)
In above formula, svbeg(vπ i) represent node Vπ iScheduling variable initial value, svbeg(vπ j) represent node Vπ jScheduling become
Measure initial value, node Vπ iWith node Vπ jRepresent a pair of nodes with same asset, Latency (vπ i) represent node Vπ iPerform
Required time delay.
Further, the step S22, including：
S221, the domination set of the Ingress node of control data flow graph is initialized as the Ingress node, while will control
The domination set of other nodes of DFD is initialized as complete or collected works；
S222, any node in addition to Ingress node for control data flow graph, ask for the domination set of the node
After the common factor of the domination set of its forerunner's node, using the union of the node and the common factor as the node domination set；
S223, step S222 is repeated, after the domination set of all nodes no longer changes, according to all nodes
Domination set build Dominator Tree.
The beneficial effects of the invention are as follows：A kind of High Level Synthesis based on difference constrained system and iteration mould of the present invention is adjusted
Degree method, builds after corresponding control data flow graph after the circuit description for obtaining input, control data flow graph is divided into circulation
Part and acyclic part, and then iteration modulo scheduling algorithm and difference constrained system dispatching algorithm paired domination number is respectively adopted according to stream
The cyclic part of figure and acyclic part are scheduled, and the scheduling flow of High Level Synthesis is optimized, and improve scheduling
Performance, and scheduling implementation process is easily and fast, and scheduling can be realized comprehensively, in time, and dispatching efficiency is high.
Brief description of the drawings
The invention will be further described with reference to the accompanying drawings and examples.
Fig. 1 is the control in a kind of High Level Synthesis dispatching method based on difference constrained system and iteration mould of the present invention
The schematic diagram of DFD；
Fig. 2 is the circulation in a kind of High Level Synthesis dispatching method based on difference constrained system and iteration mould of the present invention
Structural representation；
Fig. 3 is a kind of processing stream based on difference constrained system Yu the High Level Synthesis dispatching method of iteration mould of the present invention
Journey schematic diagram；
Fig. 4 is that a kind of of the present invention is changed based on difference constrained system with being used in the High Level Synthesis dispatching method of iteration mould
Loop body is carried out to the local scheduling result of local scheduling for modulo scheduling algorithm；
Fig. 5 is to be iterated the final scheduling after scheduling to the local scheduling result in Fig. 4 using iteration modulo scheduling algorithm
As a result.
Embodiment
The invention provides a kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould, including：
Corresponding control data flow graph is built after S1, the circuit description of acquisition input；
S2, control data flow graph is divided into cyclic part and acyclic part；
S3, it is scheduled according to the cyclic part of flow graph using iteration modulo scheduling algorithm paired domination number；
S4, it is scheduled according to the acyclic part of flow graph using difference constrained system dispatching algorithm paired domination number；
S5, the scheduling result that is obtained in step S3 and S4 is carried out after mathematics integration, obtain integrated dispatch result.
It is further used as preferred embodiment, the step S2, including：
S21, it is ranked up according to all running nodes in flow graph using depth-priority-searching method paired domination number；
S22, the node of the control data flow graph after sequence is built into by corresponding Dominator Tree using dominating figure iterative algorithm；
After all back edges in S23, Detection and Extraction Dominator Tree, all loops being made up of back edge are obtained as control data
The cyclic part of flow graph, and then obtain the acyclic part of control data flow graph.
It is further used as preferred embodiment, the step S3, including：
S31, paired domination number carry out minimum iteration according to the cyclic part of flow graph and start interval time calculating；
S32, the minimum iteration for obtaining calculating start interval time as initial iteration and start interval time, use row
List scheduling algorithm paired domination number is scheduled according to the cyclic part of flow graph；
S33, iteration are scheduled trial when meeting following condition, continue executing with step S34：Dispatch successfully or adjust
The iteration number of attempt of degree is more than predetermined upper threshold value；
S34, judge whether that scheduling is finished, if so, then terminate, otherwise increase iteration started after interval time, was continuing with
List scheduling algorithm carries out next round scheduling, and returns to execution step S33.
It is further used as preferred embodiment, the step S4, including：
S41, paired domination number build corresponding scheduling variable according to the node of the acyclic part of flow graph；
S42, according to scheduling variable, all schedule constraints are converted to after corresponding difference constraint formulations, by acquisition
All difference constraint formulations change into shaping planning matrix；
S43, the demand result according to High Level Synthesis, build corresponding object function；
S44, using shaping planning matrix as bound for objective function, carry out linear programming for solution, judge whether energy
The optimal value for obtaining object function is solved, step S43 is performed if it is not, then returning, otherwise obtains the optimal value of the object function, together
When obtain the value of corresponding shaping planning matrix, and then obtain the dispatch value of each node.
It is further used as preferred embodiment, schedule constraints described in the step S42 include relying on constraint, sequential about
Beam and resource constraint.
It is further used as preferred embodiment, the dependence constraint causes including the data dependency in being described by circuit
Data dependence constraint and control dependence in being described as circuit caused by control rely on constraint；
When the schedule constraints are that data dependence is constrained, corresponding difference is translated into using below equation and constrains public
Formula：
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svend(vi) represent node ViScheduling variable
End value, node ViWith node VjIt is two running nodes and node V constrained with data dependenceiMust be in node VjScheduling
It is preceding that scheduling is finished, e (vi,vj) represent node ViWith node VjData dependence binding side, EdRepresent in control data flow graph
The set of all data dependence binding sides；
When the schedule constraints rely on constraint for control, corresponding difference is translated into using below equation and constrains public
Formula：
In above formula, svbeg(ssrc(bbj)) represent basic blocks bbjScheduling variable initial value, svend(ssnk(bbi)) table
Show basic blocks bbiScheduling variable end value, basic blocks bbiWith basic blocks bbjIt is two basic blocks that constraint is relied on control
And basic blocks bbjRunning node must be in basic blocks bbiAll running nodes dispatch finish after just schedulable, ec
(bbi,bbj) represent basic blocks bbiWith basic blocks bbjControl rely on binding side, EcRepresent all controls in control data flow graph
System relies on the set of binding side.
It is further used as preferred embodiment, the temporal constraint includes relative timing and constrained and delay constraints, relatively
Temporal constraint includes minimum relative timing constraint and maximum relative timing constraint；
When the schedule constraints are minimum relative timing constraint, using being converted into corresponding difference in below equation about
Beam formula：
svbeg(vi)-svbeg(vj)≤-lij
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svbeg(vi) represent node ViScheduling variable
Initial value, lijFor natural number, node ViWith node VjIt is two running nodes and node V with minimum relative timing constraintj's
Scheduling must be than node ViScheduling at least evening lijThe individual clock cycle；
When the schedule constraints are maximum relative timing constraint, using being converted into corresponding difference in below equation about
Beam formula：
svbeg(vj)-svbeg(vi)≤uij
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svend(vi) represent node ViScheduling variable
Initial value, uijFor natural number, node ViWith node VjIt is two running nodes and node V with maximum relative timing constraintjWith
Node ViBetween maximum delay path be uijThe individual clock cycle；
When the schedule constraints are delay constraints, using being converted into corresponding difference constraint formulations in below equation：
svend(ssnk(bbj))-svbeg(ssrc(bbi))≤Tlat
Wherein, svend(ssnk(bbj)) represent basic blocks bbjScheduling variable end value, svbeg(ssrc(bbi)) represent
Basic blocks bbiScheduling variable initial value, basic blocks bbiWith basic blocks bbjIt is two basic blocks and basis with delay constraints
Block bbiWith basic blocks bbjBetween maximum delay path be TlatThe individual clock cycle.
Be further used as preferred embodiment, the schedule constraints be resource constraint when, using in below equation by it
Be converted to corresponding difference constraint formulations：
svbeg(vπ i)-svbeg(vπ j)≤-Latency(vπ i)
In above formula, svbeg(vπ i) represent node Vπ iScheduling variable initial value, svbeg(vπ j) represent node Vπ jScheduling become
Measure initial value, node Vπ iWith node Vπ jRepresent a pair of nodes with same asset, Latency (vπ i) represent node Vπ iPerform
Required time delay.
It is further used as preferred embodiment, the step S22, including：
S221, the domination set of the Ingress node of control data flow graph is initialized as the Ingress node, while will control
The domination set of other nodes of DFD is initialized as complete or collected works；
S222, any node in addition to Ingress node for control data flow graph, ask for the domination set of the node
After the common factor of the domination set of its forerunner's node, using the union of the node and the common factor as the node domination set；
S223, step S222 is repeated, after the domination set of all nodes no longer changes, according to all nodes
Domination set build Dominator Tree.
The present invention is elaborated with reference to specific embodiment.
First, paired domination number is illustrated according to flow graph, and Fig. 1 is the schematic diagram of control data flow graph, control data flow graph
(Control data flow graph, abbreviation CDFG) is the execution operation object of dispatching algorithm, and it is to contain to be input to be
The digraph of the relevant informations such as data operation, data dependence, control skip in the circuit description of system.Control data flow graph can be with
It is divided into node (scheduling unit) and side (relation between scheduling unit) the two parts.Wherein, node includes running node
(Operation node) and basic blocks (Basic block).Running node refers to the fortune occurred in the circuit description of input
Operational set is calculated, and according to the difference of control planning, one or more running node set may make up a basic blocks.In Fig. 1
In, what bold portion signified is data dependence relation side, and what dotted portion signified is control dependence side, each oval
A running node is represented, each square frame represents a basic blocks.Each circuit description can use such a digraph to enter
Row is represented.In practical operation, DFD can be set up by LLVM compiling systems, by instruction type, data dependence relation and
The informations such as control skip turn into model, build control data flow graph, are easy to every optimization to include scheduling, resource allocation and again
With waiting in work, the application, building control data flow graph is used to carry out High Level Synthesis scheduling.
Reference picture 1, a kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould, including：
Corresponding control data flow graph is built after S1, the circuit description of acquisition input；
S2, control data flow graph is divided into cyclic part and acyclic part；
S3, it is scheduled according to the cyclic part of flow graph using iteration modulo scheduling algorithm paired domination number；
S4, it is scheduled according to the acyclic part of flow graph using difference constrained system dispatching algorithm paired domination number；
S5, the scheduling result that is obtained in step S3 and S4 is carried out after mathematics integration, obtain integrated dispatch result.
Specifically, step S2, including S21~S23：
S21, it is ranked up according to all running nodes in flow graph using depth-priority-searching method paired domination number；
S22, the node of the control data flow graph after sequence is built into by corresponding Dominator Tree using dominating figure iterative algorithm,
Specifically include S221~S223：
S221, the domination set of the Ingress node of control data flow graph is initialized as the Ingress node, while will control
The domination set of other nodes of DFD is initialized as complete or collected works；Here, complete or collected works refer to all sections of control data flow graph
Point.
S222, any node in addition to Ingress node for control data flow graph, ask for the domination set of the node
After the common factor of the domination set of its forerunner's node, using the union of the node and the common factor as the node domination set.Section
The domination set of point refers to the set for dominating all nodes of the node, forerunner's node of node refer in control data flow graph by
Node when being traveled through according to data flow direction before the node.For example, node A is Ingress node, node A dominates node B, C,
Node B dominates node D, then the domination for node B is combined, and node B domination set (node B domination set is tried to achieve first
It is initialized as complete or collected works) with the common factor of node A domination set it is { A }, then by union { A, B } conduct of node B and the common factor
Node B domination set；Similar, for node D domination set, node D domination set and node B branch is tried to achieve first
It is { A, B } with intersection of sets collection, then by domination set of the union { A, B, D } of node D and the common factor as node D.
S223, step S222 is repeated, after the domination set of all nodes no longer changes, according to all nodes
Domination set build Dominator Tree.The domination set of all nodes no longer changes, then obtains the domination of control data flow graph
Tree relation, therefore corresponding Dominator Tree can be built according to Dominator Tree relation.Step S221~S223 interative computation process is
The dominating figure iterative algorithm mentioned for step S22.
After all back edges in S23, Detection and Extraction Dominator Tree, all loops being made up of back edge are obtained as control data
The cyclic part of flow graph, and then obtain the acyclic part of control data flow graph.Shown in reference picture 2, loop is by back edge in figure
The circulation of the loop of composition, i.e., one, it is the circulation portions for constituting control data flow graph to obtain all circulations in control data flow graph
Point.
Fig. 3 is the handling process schematic diagram of this dispatching method, and this method is after control data flow graph is built, partition loops portion
Divide and acyclic part, then for cyclic part and acyclic part, different operations are performed respectively, as shown in Figure 3, most
Afterwards, the scheduling result two kinds of operations obtained is integrated, that is, obtains the scheduling result of this dispatching method.
Specifically, step S3, including S31~S34：
S31, paired domination number carry out minimum iteration according to the cyclic part of flow graph and start interval time calculating.
S32, the minimum iteration for obtaining calculating start interval time as initial iteration and start interval time, use row
List scheduling algorithm paired domination number is scheduled according to the cyclic part of flow graph.
List scheduling algorithm is also referred to as List scheduling algorithm, its basic thought be by the priority level to node be ranked up come
A dispatch list is constructed, following two steps is then repeated and is finished until all nodes are scheduled：1. it is suitable from dispatch list
Sequence according to priority takes out a node；2. on the basis of constraints is met by node scheduling to making its startup time earliest
Control step on, the algorithm is more ripe algorithm, here without being described in detail.
S33, iteration are scheduled trial when meeting following condition, continue executing with step S34：Dispatch successfully or adjust
The iteration number of attempt of degree is more than predetermined upper threshold value.
Dispatch and successfully refer to the specific dispatch value for obtaining node from the point of view of output result；Predetermined upper threshold value refers to limit
Scheduling time processed and dispatch the number of times of trial in the often wheel scheduling that limits, such as predetermined upper threshold value is 10, then if scheduling is tasted
Examination number of times, which reaches 10 times, does not dispatch success also, is also no longer scheduled trial, directly performs step S34.
S34, judge whether that scheduling is finished, if so, then terminate, otherwise increase iteration started after interval time, was continuing with
List scheduling algorithm carries out next round scheduling, and returns to execution step S33.Increase iteration startup interval time refers to increase iteration
Start the value of interval time, for example, iteration startup interval time is increased into 7 clock cycle by 6 clock cycle.
Fig. 4 and Fig. 5 can be combined and further understand use iteration modulo scheduling algorithm that step S31~S34 embodied to control
J in the process that the cyclic part of DFD processed is scheduled, Fig. 4 and in Fig. 5 represents iterations, by loop body progress office
Between the situation of a local scheduling result is obtained after ministry dispatching as shown in figure 4, the local scheduling result in Fig. 4 is started with iteration
Be iterated every the time, obtained final scheduling result as shown in figure 5, when the cycle-index of iteration increases to a certain extent,
The scope come is irised out in the oval part that program will enter in stable state, such as Fig. 5, i.e. this dispatching method is constantly repeated
The instruction of same sequence, realizes the parallel execution between different loop bodies, it is hereby achieved that the speed of service faster.
Next calculating process and the acquisition side of iteration startup interval time that minimum iteration starts interval time are introduced
Method, for the ease of description, represented with II iteration start interval time, represented with MII by calculate obtain expected from most
Small iteration starts interval time II.
Need to consider that Resource Dependence constraint and data dependence constrain two kinds for the calculating that minimum iteration starts interval time
Situation, the minimum iteration under Resource Dependence constraint starts interval time for ResMII, and the minimum under having been constrained since data changes
In generation, starts interval time for RecMII, ResMII and RecMII is tried to achieve respectively in the case where considering both of these case, so as to obtain MII=
Max (ResMII, RecMII), and then it is scheduled trial using the MII of acquisition as initial iteration startup interval time II.
When calculating ResMII, we pass through the available resources provided its target machine and appointing in final scheduling result
The calculating that the relation of total number resource shared by the instruction of one moment i all concurrent operations is modeled to obtain ResMII is public
Formula.
The available resources of target machine are made to be expressed as R=[r1,r2,r3...], wherein rj(j=1,2,3 ...)
Represent the useful number of jth types of resources.Obviously, in order to meet resource constraint relation, final scheduling result it is any when
Carving i should all meet：
RTS[i,j]≤rj
Wherein, RTS[i, j] represents the j classes shared by the instruction of i all concurrent operations at the time of in final scheduling result
The number of type resource.Understood with reference to Fig. 5, number is equal to II at the time of stable state is included, to the stabilization in final scheduling result
All moment of state are overlapped, then have：
It should be noted that because scheduling simply changes the order of computing execution, the number of instruction can't be decreased or increased
Mesh.Therefore one cycle is equally completed, resource consumption does not change before and after scheduling, then has：
Wherein,Represent to complete the j types money that one cycle is consumed in final scheduling result namely after scheduling
The sum in source.Represent to complete the j resource types that one cycle is consumed in local scheduling result namely before scheduling
Sum.
Then for the resource constraint for meeting j resource types, the iteration under having been constrained since resource starts interval time II should
Meet following formula：
And when consideration all types resource constraint, you can to obtain ResMII expression formulas：
And when calculating RecMII, because circulation can cause the presence of the same fortune that a computing is depended in preceding an iteration
The result of calculation, causes data dependence relation formation ring, and we will consider delay, iteration distance and distinguish the computing between different iteration
Example.Data dependence relation in iteration between iteration, can Unified Expression be：
(δ×II)+S(n2)-S(n1)≥d
Wherein δ represents iteration distance, and II represents that iteration starts interval time, n1、n2For two computings that there is dependence
Instruction, S (n1)、S(n2) n is represented respectively1、n2Scheduling result.
Therefore relying on ring for one can obtain：
Wherein, dcTo rely on total delay of ring.
It is contemplated that dependence ring all in control data flow graph, can obtain RecMII expression formulas：
Wherein, G represents constructed control data flow graph (i.e. CDFG's writes a Chinese character in simplified form), dcIt is total delay of data dependence ring,
And δcIt is total iteration distance of data dependence ring.
Corresponding minimum iteration is calculated according to Resource Dependence constraint and data dependence constraint respectively and starts interval time, will
Maximum in both starts interval time MII as minimum iteration, and the MII calculated is expected minimum iteration
Start interval time, but the scheduling for starting interval time II using MII as actual iteration is attempted not necessarily succeed,
MII meaning is the lower limit as iteration startup interval time II for being possible to be scheduled to work(.In fact, being retouched with reference to more than
State and understand, it is to calculate the intermediate result during iteration startup interval time II that minimum iteration, which starts interval time MII, therefore
It also using in MII formulation process in II concept, the application in order to preferably make a distinction in claim, respectively
It is described using different definition.
Reference picture 3, step S4, including S41~S44：
S41, paired domination number build corresponding scheduling variable according to the node of the acyclic part of flow graph.
S42, according to scheduling variable, all schedule constraints are converted to after corresponding difference constraint formulations, by acquisition
All difference constraint formulations change into shaping planning matrix.
Schedule constraints are converted into corresponding difference constraint formulations, that is, realizes the modeling to schedule constraints, will each dispatch
Constraint changes into similar x-y≤b form, wherein, x, y are scheduling variable, and b is constant.
S43, the demand result according to High Level Synthesis, build corresponding object function.
The demand result of High Level Synthesis refers to designer to the parameter requirements in IC design, such as computing speed
Degree, area etc., if demand result is area, build area expression formula as object function, if demand result is arithmetic speed,
The expression formula for then building arithmetic speed is used as object function.
S44, using shaping planning matrix as bound for objective function, carry out linear programming for solution, judge whether energy
The optimal value for obtaining object function is solved, step S43 is performed if it is not, then returning, otherwise obtains the optimal value of the object function, together
When obtain the value of corresponding shaping planning matrix, and then obtain the dispatch value of each node.
Here, combined objective function and the shaping planning matrix as constraints, using linear programming for solution mode
Solved, try to achieve optimal value of the object function on the premise of constraints (i.e. shaping planning matrix) is met, such as area
Minimum value or arithmetic speed maximum, correspondingly, obtain the value of shaping planning matrix now because shaping planning matrix be by
What scheduling variable was constituted, the value of scheduling variable can be obtained by obtaining the value of shaping planning matrix, equivalent to each node of acquisition
Dispatch value, completes scheduling.When carrying out linear programming for solution to object function, any linear gauge of the prior art can be used
Draw method for solving, solved for example with linear programming for solution instrument lp_solve5.5, in solution procedure, object function and
Shaping planning matrix is the linear programming model of difference constrained system.The purpose of this step is to solve for obtaining object function most
The figure of merit, in fact, when carrying out linear programming for solution, differing and surely obtaining optimal value, if optimal value can not be obtained, needs to return to step
Rapid S43, rebuilds and carries out linear programming for solution after object function again until solving acquisition optimal value.
Schedule constraints include relying on constraint, temporal constraint and resource constraint in step S42.
Data dependence caused by data dependency during constraint is relied on including being described as circuit is constrained and described by circuit
In control dependence caused by control rely on constraint；
When schedule constraints are that data dependence is constrained, corresponding difference constraint formulations are translated into using below equation：
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svend(vi) represent node ViScheduling variable
End value, node ViWith node VjIt is two running nodes and node V constrained with data dependenceiMust be in node VjScheduling
It is preceding that scheduling is finished, e (vi,vj) represent node ViWith node VjData dependence binding side, EdRepresent in control data flow graph
The set of all data dependence binding sides.
When schedule constraints rely on constraint for control, corresponding difference constraint formulations are translated into using below equation：
In above formula, svbeg(ssrc(bbj)) represent basic blocks bbjScheduling variable initial value, svend(ssnk(bbi)) table
Show basic blocks bbiScheduling variable end value, basic blocks bbiWith basic blocks bbjIt is two basic blocks that constraint is relied on control
And basic blocks bbjRunning node must be in basic blocks bbiAll running nodes dispatch finish after just schedulable, ec
(bbi,bbj) represent basic blocks bbiWith basic blocks bbjControl rely on binding side, EcRepresent all controls in control data flow graph
System relies on the set of binding side.
Temporal constraint includes relative timing and constrained and delay constraints, relative timing constraint include minimum relative timing constraint with
Maximum relative timing constraint；
When schedule constraints are minimum relative timing constraint, constrain public using corresponding difference is converted into below equation
Formula：
svbeg(vi)-svbeg(vj)≤-lij
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svbeg(vi) represent node ViScheduling variable
Initial value, lijFor natural number, node ViWith node VjIt is two running nodes and node V with minimum relative timing constraintj's
Scheduling must be than node ViScheduling at least evening lijThe individual clock cycle；
When schedule constraints are maximum relative timing constraint, constrain public using corresponding difference is converted into below equation
Formula：
svbeg(vj)-svbeg(vi)≤uij
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svend(vi) represent node ViScheduling variable
Initial value, uijFor natural number, node ViWith node VjIt is two running nodes and node V with maximum relative timing constraintjWith
Node ViBetween maximum delay path be uijThe individual clock cycle；
When schedule constraints are delay constraints, using being converted into corresponding difference constraint formulations in below equation：
svend(ssnk(bbj))-svbeg(ssrc(bbi))≤Tlat
Wherein, svend(ssnk(bbj)) represent basic blocks bbjScheduling variable end value, svbeg(ssrc(bbi)) represent
Basic blocks bbiScheduling variable initial value, basic blocks bbiWith basic blocks bbjIt is two basic blocks and basis with delay constraints
Block bbiWith basic blocks bbjBetween maximum delay path be TlatThe individual clock cycle.
When schedule constraints are resource constraint, using being converted into corresponding difference constraint formulations in below equation：
svbeg(vπ i)-svbeg(vπ j)≤-Latency(vπ i)
In above formula, svbeg(vπ i) represent node Vπ iScheduling variable initial value, svbeg(vπ j) represent node Vπ jScheduling become
Measure initial value, node Vπ iWith node Vπ jRepresent a pair of nodes with same asset, Latency (vπ i) represent node Vπ iPerform
Required time delay.The formula is represented and node Vπ jScheduling must be than node Vπ iScheduling at least evening Latency (vπ i) individual
Clock cycle.
Above is the preferable implementation to the present invention is illustrated, but the invention is not limited to embodiment, ripe
A variety of equivalent variations or replacement can also be made on the premise of without prejudice to spirit of the invention by knowing those skilled in the art, these
Equivalent modification or replacement is all contained in the application claim limited range.
Claims (6)
1. a kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould, it is characterised in that including：
Corresponding control data flow graph is built after step S1, the circuit description of acquisition input；
Step S2, control data flow graph is divided into cyclic part and acyclic part；
Step S3, it is scheduled according to the cyclic part of flow graph using iteration modulo scheduling algorithm paired domination number；
Step S4, it is scheduled according to the acyclic part of flow graph using difference constrained system dispatching algorithm paired domination number；
Step S5, the scheduling result that is obtained in step S3 and S4 is carried out after mathematics integration, obtain integrated dispatch result；
The step S3, including step S31~S34：
Step S31, paired domination number carry out minimum iteration according to the cyclic part of flow graph and start interval time calculating；
Step S32, the minimum iteration for obtaining calculating start interval time as initial iteration and start interval time, use row
List scheduling algorithm paired domination number is scheduled according to the cyclic part of flow graph；
Step S33, iteration are scheduled trial when meeting following condition, continue executing with step S34：Dispatch successfully or adjust
The iteration number of attempt of degree is more than predetermined upper threshold value；
Step S34, judge whether that scheduling is finished, if so, then terminate, otherwise increase iteration started after interval time, was continuing with
List scheduling algorithm carries out next round scheduling, and returns to execution step S33；
The step S4, including step S41~S44：
Step S41, paired domination number build corresponding scheduling variable according to the node of the acyclic part of flow graph；
Step S42, according to scheduling variable, all schedule constraints are converted to after corresponding difference constraint formulations, by acquisition
All difference constraint formulations change into shaping planning matrix；
Step S43, the demand result according to High Level Synthesis, build corresponding object function；
Step S44, using shaping planning matrix as bound for objective function, carry out linear programming for solution, judge whether energy
The optimal value for obtaining object function is solved, step S43 is performed if it is not, then returning, otherwise obtains the optimal value of the object function, together
When obtain the value of corresponding shaping planning matrix, and then obtain the dispatch value of each node.
2. a kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould according to claim 1, its
It is characterised by, the step S2, including：
Step S21, it is ranked up according to all running nodes in flow graph using depth-priority-searching method paired domination number；
Step S22, the node of the control data flow graph after sequence is built into by corresponding Dominator Tree using dominating figure iterative algorithm；
After all back edges in step S23, Detection and Extraction Dominator Tree, all loops being made up of back edge are obtained as control data
The cyclic part of flow graph, and then obtain the acyclic part of control data flow graph；
The step S22, including step S221~S223：
Step S221, the domination set of the Ingress node of control data flow graph is initialized as the Ingress node, while will control
The domination set of other nodes of DFD is initialized as complete or collected works；
Step S222, any node in addition to Ingress node for control data flow graph, ask for the domination set of the node
After the common factor of the domination set of its forerunner's node, using the union of the node and the common factor as the node domination set；
Step S223, step S222 is repeated, after the domination set of all nodes no longer changes, according to all nodes
Domination set build Dominator Tree.
3. a kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould according to claim 1, its
It is characterised by, schedule constraints described in the step S42 include relying on constraint, temporal constraint and resource constraint.
4. a kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould according to claim 3, its
It is characterised by, it is described to rely on data dependence constraint caused by the data dependency for constraining and including in being described as circuit and by circuit
Control relies on constraint caused by control dependence in description；
When the schedule constraints are that data dependence is constrained, corresponding difference constraint formulations are translated into using below equation：
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In above formula, svbeg(vj) represent node VjScheduling variable initial value, svend(vi) represent node ViScheduling variable terminate
Value, node ViWith node VjIt is two running nodes and node V constrained with data dependenceiMust be in node VjBefore scheduling just
Scheduling is finished, e (vi,vj) represent node ViWith node VjData dependence binding side, EdRepresent all in control data flow graph
The set of data dependence binding side；
When the schedule constraints rely on constraint for control, corresponding difference constraint formulations are translated into using below equation：
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In above formula, svbeg(ssrc(bbj)) represent basic blocks bbjScheduling variable initial value, svend(ssnk(bbi)) represent base
Plinth block bbiScheduling variable end value, basic blocks bbiWith basic blocks bbjIt is two basic blocks and base that constraint is relied on control
Plinth block bbjRunning node must be in basic blocks bbiAll running nodes dispatch finish after just schedulable, ec(bbi,
bbj) represent basic blocks bbiWith basic blocks bbjControl rely on binding side, EcRepresent control data flow graph in all controls according to
Rely the set of binding side.
5. a kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould according to claim 3, its
It is characterised by, the temporal constraint includes relative timing and constrained and delay constraints, relative timing constraint includes minimum relative timing
Constraint and maximum relative timing constraint；
When the schedule constraints are minimum relative timing constraint, constrain public using corresponding difference is converted into below equation
Formula：
svbeg(vi)-svbeg(vj)≤-lij
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svbeg(vi) represent node ViScheduling variable starting
Value, lijFor natural number, node ViWith node VjIt is two running nodes and node V with minimum relative timing constraintjScheduling
Must be than node ViScheduling at least evening lijThe individual clock cycle；
When the schedule constraints are maximum relative timing constraint, constrain public using corresponding difference is converted into below equation
Formula：
svbeg(vj)-svbeg(vi)≤uij
In above formula, svbeg(vj) represent node VjScheduling variable initial value, svend(vi) represent node ViScheduling variable starting
Value, uijFor natural number, node ViWith node VjIt is two running nodes and node V with maximum relative timing constraintjWith node
ViBetween maximum delay path be uijThe individual clock cycle；
When the schedule constraints are delay constraints, using being converted into corresponding difference constraint formulations in below equation：
svend(ssnk(bbj))-svbeg(ssrc(bbi))≤Tlat
Wherein, svend(ssnk(bbj)) represent basic blocks bbjScheduling variable end value, svbeg(ssrc(bbi)) represent basis
Block bbiScheduling variable initial value, basic blocks bbiWith basic blocks bbjIt is two basic blocks and basic blocks with delay constraints
bbiWith basic blocks bbjBetween maximum delay path be TlatThe individual clock cycle.
6. a kind of High Level Synthesis dispatching method based on difference constrained system Yu iteration mould according to claim 3, its
It is characterised by, when the schedule constraints are resource constraint, using being converted into corresponding difference constraint formulations in below equation：
svbeg(vπ i)-svbeg(vπ j)≤-Latency(vπ i)
In above formula, svbeg(vπ i) represent node Vπ iScheduling variable initial value, svbeg(vπ j) represent node Vπ jScheduling variable rise
Initial value, node Vπ iWith node Vπ jRepresent a pair of nodes with same asset, Latency (vπ i) represent node Vπ iNeeded for performing
Time delay.
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