CN102881629A - Preparation method of floating grid capable of increasing height of shallow-trench isolating platform column - Google Patents
Preparation method of floating grid capable of increasing height of shallow-trench isolating platform column Download PDFInfo
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- CN102881629A CN102881629A CN2012104146944A CN201210414694A CN102881629A CN 102881629 A CN102881629 A CN 102881629A CN 2012104146944 A CN2012104146944 A CN 2012104146944A CN 201210414694 A CN201210414694 A CN 201210414694A CN 102881629 A CN102881629 A CN 102881629A
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Abstract
The invention provides a preparation method of a floating grid capable of increasing the height of a shallow-trench isolating platform column. The preparation method comprises the following steps of: a step of forming laminated layers: forming a floating-grid oxidation layer, a floating-grid polycrystalline silicon layer, an additional oxide layer, an additional polycrystalline silicon layer and a hard-mask layer in sequence on a semiconductor substrate; a step of forming a shallow-trench isolating area: utilizing the hard-mask layer to etch to form the shallow-trench isolating area; and a step of forming the shallow-trench isolating platform column: executing the growth of a lined oxidation layer, backfilling a silicon oxide medium layer and performing chemical and mechanical grinding to realize flattening, removing the silicon-nitride hard-mask layer by etching, carrying out polycrystalline-silicon etching, and removing the additional polycrystalline-silicon layer. The preparation method provided by the invention has the advantages that the precomputed height of the shallow-trench isolating platform column can be effectively prevented from being changed to be small gradually along with the reduction of the characteristic size of a device, and the problem of sinking at the edge of an active area can be effectively prevented.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly, the present invention relates to a kind of floating boom preparation method who improves shallow-trench isolation important actor height.
Background technology
Flash memory (Flash memory) is a kind of important semiconductor product, have a wide range of applications in all many-sides such as data storage, communication, consumer electronics, for continuous satisfying the market to high integration, cheaply requirement, the lifting of the manufacturing technology level of flash memory is constantly upgrading also, show as dwindling of critical size at device architecture, also require the thickness of attenuate polysilicon layer to satisfy the requirement of floating boom coupling coefficient simultaneously.
Like this, because reducing of the thickness of polysilicon layer just reduced as the precomputed altitude for the shallow-trench isolation important actor that separates the transistorized shallow trench isolation region of each floating boom thus in advance.
And on the other hand, because device feature size diminishes gradually, the top of shallow-trench isolation important actor is also easier
Dwindled by the related process erosion, the situation of this two aspect all can cause the height possibility of shallow-trench isolation important actor inadequate, thereby might cause the problem of active area marginal trough in follow-up etch process.Fig. 2 schematically shows because isolation important actor insufficient height causes the example of active area marginal trough behind subsequent technique.Isolated area A3 (with the shallow-trench isolation important actor) between active area A1 and the active area A2, because isolated area A3 insufficient height, thereby there is marginal trough in the position shown in active area A1 and the active area A2 top dotted line circle.
Therefore, hope can provide a kind of precomputed altitude that prevents the shallow-trench isolation important actor to diminish gradually along with dwindling of device feature size and prevent the technical scheme of the problem of active area marginal trough.
Summary of the invention
Technical problem to be solved by this invention is for there being defects in the prior art, provides a kind of precomputed altitude that can effectively prevent the shallow-trench isolation important actor to diminish gradually along with dwindling of device feature size and prevents the floating boom preparation method of raising shallow-trench isolation important actor height of the problem of active area marginal trough.
According to prior art, be directly silicon nitride hardmask layer to be thickeied than the method that is easier to consider, with the polysilicon layer of compensation attenuate, keep total thickness.But in fact also infeasible, because silicon nitride can be injected by light, the light of upper and lower surface is along with the variation of thickness can produce interference effect relevant or that disappear mutually, so follow-up photoetching process has specific thickness requirement to silicon nitride hardmask layer, to eliminate standing wave effect.
Thus, in order to realize above-mentioned technical purpose, according to the present invention, a kind of floating boom preparation method who improves shallow-trench isolation important actor height is provided, it comprises: lamination forms step, is used for forming successively on Semiconductor substrate floating gate oxide layers, floating gate polysilicon layer, additional oxide layer, additional polysilicon layer and hard mask layer; Shallow trench isolation region forms step, is used for utilizing the hard mask layer etching to form shallow trench isolation region; The shallow-trench isolation important actor forms step, is used for carrying out the pad oxide layer growth, the backfill of silica medium layer, and cmp to be realizing planarization, and after removing the silicon nitride hard mask layer by etching, carries out the polysilicon etching, removes additional polysilicon layer.Wherein, because polysilicon layer is light tight, the additional polysilicon layer of increase and following additional oxide layer do not affect follow-up photoetching process.
Preferably, in the floating boom preparation method of above-mentioned raising shallow-trench isolation important actor height, described hard mask layer is silicon nitride layer.
Preferably, in the floating boom preparation method of above-mentioned raising shallow-trench isolation important actor height, form in the step at described shallow trench isolation region, at first hard mask layer is carried out photoetching to form the pattern corresponding with shallow trench isolation region, utilize the hard mask layer that forms pattern with photoresist Semiconductor substrate, floating gate oxide layers, floating gate polysilicon layer, additional oxide layer and additional polysilicon layer to be carried out etching to form the groove corresponding with shallow trench isolation region, form shallow trench isolation region thereby in described groove, fill subsequently spacer.
Preferably, in the floating boom preparation method of above-mentioned raising shallow-trench isolation important actor height, spacer is silica.
Preferably, in the floating boom preparation method of above-mentioned raising shallow-trench isolation important actor height, form in the step at shallow trench isolation region, in described groove, fill spacer and carry out cmp afterwards.
Preferably, in the floating boom preparation method of above-mentioned raising shallow-trench isolation important actor height, form in the step at described shallow-trench isolation important actor, utilize hot phosphoric acid to come wet method to remove hard mask layer.
Preferably, in the floating boom preparation method of above-mentioned raising shallow-trench isolation important actor height, in the step of removing additional polysilicon layer, adopt isotropic dry etching.
In the floating boom preparation method of raising shallow-trench isolation important actor height according to the present invention, in originally thicker polysilicon layer, insert an additional oxide layer, thereby thicker polysilicon layer is divided into two into floating gate polysilicon layer and additional polysilicon layer originally, utilize thus the thicker polysilicon layer of script to improve the precomputed altitude of shallow-trench isolation important actor, after forming, the shallow-trench isolation important actor utilize simultaneously the selection ratio between the material to remove the additional polysilicon layer on upper strata, satisfy the floating gate polysilicon layer with little thickness and stay, to satisfy the requirement of dwindling of device feature size, both satisfy thus the height of important actor, realized again the floating boom that final thickness is thinner.
Thus, the invention provides a kind of precomputed altitude that can effectively prevent the shallow-trench isolation important actor diminishes gradually along with dwindling of device feature size, and can effectively prevent the floating boom preparation method of raising shallow-trench isolation important actor height of the problem of active area marginal trough.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the flow chart according to the floating boom preparation method of the raising shallow-trench isolation important actor height of prior art.
Fig. 2 schematically shows because isolation important actor insufficient height causes the example of active area marginal trough behind subsequent technique.
Fig. 3 schematically shows the schematic diagram that forms step according to the floating boom preparation method's of the raising shallow-trench isolation important actor height of the embodiment of the invention lamination.
Fig. 4 schematically shows according to the present invention the schematic diagram that forms step according to the floating boom preparation method's of the raising shallow-trench isolation important actor height of the embodiment of the invention shallow trench isolation region.
Fig. 5 schematically shows according to the present invention the schematic diagram that forms step according to the floating boom preparation method's of the raising shallow-trench isolation important actor height of the embodiment of the invention shallow-trench isolation important actor.
Need to prove that accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
Fig. 3 schematically shows the schematic diagram that forms step according to the floating boom preparation method's of the raising shallow-trench isolation important actor height of the embodiment of the invention lamination.
As shown in Figure 3, the floating boom preparation method according to the raising shallow-trench isolation important actor height of the embodiment of the invention comprises:
Lamination forms step S1, is used for forming successively on Semiconductor substrate 1 floating gate oxide layers 2, floating gate polysilicon layer 3, additional oxide layer 4, additional polysilicon layer 5 and hard mask layer 6.Wherein, because polysilicon layer is light tight, the additional polysilicon layer 5 of increase does not affect follow-up photoetching process with following additional oxide layer 4.
For example, hard mask layer 6 is silicon nitride layer (SiN).The structure that obtains after the lamination formation step S1 as shown in Figure 3.
Shallow trench isolation region forms step S2, is used for utilizing hard mask layer 6 etchings to form shallow trench isolation region 7.
Specifically, form among the step S2 at shallow trench isolation region, for example, at first hard mask layer 6 is carried out photoetching to form the pattern corresponding with shallow trench isolation region 7, the hard mask layer 6 that utilize to form pattern and photoresist carry out etching to form the groove corresponding with shallow trench isolation region 7 to Semiconductor substrate 1, floating gate oxide layers 2, floating gate polysilicon layer 3, additional oxide layer 4 and additional polysilicon layer 5, thereby form shallow trench isolation region 7, can in described groove, fill spacer subsequently, for example oxide (such as silica).
The structure that obtains after the shallow trench isolation region formation step S2 as shown in Figure 4.
The shallow-trench isolation important actor forms step S3, be used for carrying out the pad oxide layer growth, the backfill of silica medium layer, cmp is to realize planarization, and after removing silicon nitride hard mask layer 6 by wet etching, carry out the polysilicon etching, remove additional polysilicon layer 5, because to the high selectivity of silica, the shallow-trench isolation important actor 8 that lifts is kept.Can adopt any suitable technique that exists in the prior art to add polysilicon layer 5 and hard mask layer 6; For example, can utilize hot phosphoric acid to come wet method to remove the silicon nitride of hard mask layer 6.And, for example, in the step of removing additional polysilicon layer, adopt isotropic dry etching to remove additional polysilicon layer.The structure that obtains after the shallow-trench isolation important actor formation step S3 as shown in Figure 5.
In the floating boom preparation method according to the raising shallow-trench isolation important actor height of the embodiment of the invention, can understand like this, in originally thicker polysilicon layer, insert a thin oxide layer (additional oxide layer 4), thereby thicker polysilicon layer is divided into two into floating gate polysilicon layer 3 and additional polysilicon layer 5 originally, utilize thus the thicker polysilicon layer of script to improve the precomputed altitude of shallow-trench isolation important actor, after forming, the shallow-trench isolation important actor utilize simultaneously the selection ratio between the material to remove the additional polysilicon layer 5 on upper strata, satisfy the floating gate polysilicon layer 3 with little thickness and stay, to satisfy the requirement of dwindling of device feature size, both satisfy thus the height of important actor, realized again the floating boom that final thickness is thinner.
Be understandable that although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (7)
1. floating boom preparation method who improves shallow-trench isolation important actor height is characterized in that comprising:
Lamination forms step, is used for forming successively on Semiconductor substrate floating gate oxide layers, floating gate polysilicon layer, additional oxide layer, additional polysilicon layer and hard mask layer;
Shallow trench isolation region forms step, is used for utilizing the hard mask layer etching to form shallow trench isolation region;
The shallow-trench isolation important actor forms step, is used for carrying out the pad oxide layer growth, the backfill of silica medium layer, and cmp to be realizing planarization, and after removing the silicon nitride hard mask layer by etching, carries out the polysilicon etching, removes additional polysilicon layer.
2. the floating boom preparation method of raising shallow-trench isolation important actor height according to claim 1 is characterized in that described hard mask layer is silicon nitride layer.
3. the floating boom preparation method of raising shallow-trench isolation important actor height according to claim 1 and 2, it is characterized in that, form in the step at described shallow trench isolation region, at first hard mask layer is carried out photoetching and with photoresist Semiconductor substrate, floating gate oxide layers, floating gate polysilicon layer, additional oxide layer and additional polysilicon layer are carried out etching to form the groove corresponding with shallow trench isolation region to form the pattern corresponding with shallow trench isolation region, to utilize the hard mask layer that forms pattern.
4. the floating boom preparation method of raising shallow-trench isolation important actor height according to claim 3 is characterized in that spacer is silica.
5. according to claim 1 or the floating boom preparation method of 4 described raising shallow-trench isolation important actor height, it is characterized in that, form in the step at shallow trench isolation region, carry out cmp after in described groove, filling spacer.
6. the floating boom preparation method of raising shallow-trench isolation important actor height according to claim 1 and 2 is characterized in that, forms in the step at described shallow-trench isolation important actor, utilizes hot phosphoric acid to come wet method to remove hard mask layer.
7. the floating boom preparation method of raising shallow-trench isolation important actor height according to claim 1 and 2 is characterized in that, adopts isotropic dry etching to remove additional polysilicon layer.
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Citations (4)
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| US20030119257A1 (en) * | 2001-12-22 | 2003-06-26 | Dong Cha Deok | Method of manufacturing a flash memory cell |
| CN1577803A (en) * | 2003-06-30 | 2005-02-09 | 海力士半导体有限公司 | Method for manufacturing flash memory device |
| CN101083209A (en) * | 1999-02-23 | 2007-12-05 | 西利康存储技术股份有限公司 | Flash memory cell with self-aligned gates and fabrication process |
| US20090008699A1 (en) * | 2007-04-04 | 2009-01-08 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory device and method of manufacturing the same |
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- 2012-10-25 CN CN2012104146944A patent/CN102881629A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101083209A (en) * | 1999-02-23 | 2007-12-05 | 西利康存储技术股份有限公司 | Flash memory cell with self-aligned gates and fabrication process |
| US20030119257A1 (en) * | 2001-12-22 | 2003-06-26 | Dong Cha Deok | Method of manufacturing a flash memory cell |
| CN1577803A (en) * | 2003-06-30 | 2005-02-09 | 海力士半导体有限公司 | Method for manufacturing flash memory device |
| US20090008699A1 (en) * | 2007-04-04 | 2009-01-08 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory device and method of manufacturing the same |
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